CN101938454A - A mapping device and method for an optical transmission data unit - Google Patents

Abstract

The invention discloses a mapping device for optical transport data units, which comprises a first-in first-out (FIFO) cache and a data assembly and output module, wherein the FIFO cache is used for reading optical data unit (ODUk) data; and the data assembly and output module is used for reassembling the ODUk data in the FIFO cache, and writing the reassembled ODUk data into a backboard bus interface standard (TFI-5) bus. The invention also provides a mapping method for the optical transport data units. Through the device and the method, the ODUk data can be mapped onto the TFI-5 bus.

Description

A mapping device and method for an optical transmission data unit

technical field

The invention relates to the field of optical transmission, in particular to a mapping device and method for an optical transmission data unit.

Background technique

With the rapid development of communication technology, the amount of data services carried by communication networks has increased rapidly, especially the rapid development of data services such as broadband, IPTV, and video, which puts forward new requirements for operators' transmission networks. The transmission network must be able to provide massive bandwidth to adapt to this kind of data growth, and more importantly, the transmission network must be able to perform fast and flexible business scheduling, and provide comprehensive and convenient network maintenance and management, such as OAM (Operation Administration and Maintenance) functions , to meet the needs of data services.

Optical Transport Network (OTN, Optical Transport Network) is an optical communication backbone transport network standard formulated by the International Telecommunication Union Telecommunication Standardization Sector (ITU-T, ITU Telecommunications Standardization Sector). The emergence of OTN has brought new challenges to the development of transport networks. opportunity. Compared with Synchronous Digital Hierarchy (SDH, Synchronous Digital Hierarchy), OTN has strong networking capabilities, good scalability, supports multiple upper-layer services or protocols, fully transparent transmission of customer signals, and provides multi-level Serial connection monitoring function and stronger forward error correction capability; at the same time, OTN can also provide the same high bandwidth as Wavelength Division Multiplexing (WDM, Wavelength Division Multiplexing). Therefore, OTN will become the main networking technology of the next generation transmission network, especially the backbone layer.

TFI-5 (TDM Fabric to Framer Interface-5) is a backplane bus interface standard similar to Synchronous Optical Network (SONET, Synchronous Optical Network)/SDH developed by the Optical Internetworking Forum (OIF, Optical Internetworking Forum). Connect framer and time division multiplexer (TDM, Time Division Multiplex and Multiplexer) crossover devices of various services, TFI-5 supports service signals of protocols such as SONET/SDH and OTN.

The transmission data in the OTN needs to be mapped to the TFI-5 bus during crossover, and the crossover device crosses the TFI-5 bus, and then demaps the transmission data of the optical network from the TFI-5 bus after the crossover is completed. Among them, the existing OIF-TFI-5-01.0 protocol proposes a mapping idea of the optical transmission data unit for the mapping of transmission data to the TFI-5 bus: the whole mapping process is divided into two steps to complete, specifically, the data is first transferred from The optical data unit (ODUk, Optical Data Unit, k=1, 2, 3) is mapped to the virtual container C-4-Xc, and then mapped to the TFI-5 bus from C-4-Xc. However, there is currently no specific implementation manner to support and realize the above idea.

Contents of the invention

In view of this, the main purpose of the present invention is to provide an optical transmission data unit mapping device and method, which can map OTN transmission data to a TFI-5 bus.

In order to achieve the above object, technical solution of the present invention is achieved in that way:

The present invention provides a mapping device for optical transmission data unit, the device includes: a first-in-first-out FIFO buffer and a data assembly output module, wherein,

The FIFO buffer is used to read optical data unit ODUk data;

The data assembly output module is used to reassemble the ODUk data in the FIFO buffer, and write the reassembled ODUk data into the backplane bus interface standard TFI-5 bus.

Wherein, the device further includes a control module, which is used to control the FIFO buffer to read the ODUk data; it is also used to control the reassembly of the ODUk data by the data assembly output module, and control the data assembly output The module writes the reassembled data into the TFI-5 bus.

The device further includes: an address setting module, configured to divide the FIFO buffer into a plurality of FIFO small blocks as required, and set a FIFO address, a FIFO write address and a FIFO read address for the FIFO small blocks.

The FIFO buffer is also used to write the read ODUk data into the FIFO small block according to the FIFO address and the FIFO write address;

The device further includes: an address monitoring module, configured to monitor the state of the FIFO buffer writing the ODUk data into the FIFO small block according to the FIFO address and the FIFO write address; and an error occurs in the state , notify the FIFO buffer to reset immediately.

The device further includes a data source module and a counter, wherein,

The data source module is used to provide adjustment bytes and fixed filling bytes for the data assembly output module;

The counter is used to calculate the data that currently needs to be written into the TFI-5 bus according to the data structure of the TFI-5 bus;

Correspondingly, the data assembly output module is also used to read the ODUk data from the FIFO small block or read the ODUk data from the data source module according to the current data that needs to be written into the TFI-5 bus. Output the adjustment byte or the fixed padding byte, and reassemble.

It is characterized in that the data assembly output module is also used to read the ODUk data from the FIFO block according to the FIFO address and the FIFO read address;

The address monitoring module is also used to monitor the state of the ODUk data read by the data assembly output module from the FIFO block according to the FIFO address and the FIFO read address; and an error occurs in the state , notify the FIFO buffer to reset immediately.

The data assembly output module is also used to reassemble the ODUk data in the FIFO buffer, and write the reassembled ODUk data into the virtual container C-4-Xc;

Correspondingly, the FIFO buffer is also used to read the C-4-Xc data.

The data assembly output module is also used to reassemble the C-4-Xc data in the FIFO buffer, and write the reassembled C-4-Xc data into the TFI- 5 buses.

The present invention also provides a method for mapping an optical transmission data unit, the method comprising:

FIFO buffer reads ODUk data;

The data assembly output module reassembles the ODUk data in the FIFO buffer, and writes the reassembled ODUk data into the TFI-5 bus.

The method further includes:

The data assembly output module reassembles the ODUk data in the FIFO buffer, and writes the reassembled ODUk data into C-4-Xc;

The FIFO buffer reads the C-4-Xc data;

The data assembly output module reassembles the C-4-Xc data and writes it into the TFI-5 bus.

The mapping device of the optical transmission data unit of the present invention reads the ODUk data by the FIFO buffer through the coordinated work of the first-in-first-out (FIFO) buffer and the data assembly output module; The ODUk data is reassembled, and the reassembled ODUk data is written into the TFI-5 bus, so that the ODUk data can be directly mapped to the TFI-5 bus; the mapping device of the optical transmission data unit of the present invention can also pass through the FIFO The coordination of the buffer and the data assembly output module first maps the ODUk data to the C-4-Xc; then maps the C-4-Xc data to the TFI-5 bus, so that the ODUk data can be indirectly mapped to the TFI- 5 on the bus.

Description of drawings

Figure 1 is a schematic diagram of the C-4-17c data block;

Fig. 2 is the time slot allocation schematic diagram of C-4-17c data block on TFI-5 bus line;

3 is a schematic structural diagram of a mapping device for an optical transmission data unit of the present invention;

FIG. 4 is a schematic structural diagram of a mapping device for an implementation 1 of an optical transmission data unit of the present invention;

Fig. 5 is the data structure schematic diagram of FIFO register of the present invention;

FIG. 6 is a schematic structural diagram of a mapping device in Embodiment 2 of the optical transmission data unit of the present invention;

FIG. 7 is a schematic flowchart of an optical transport data unit mapping method according to the present invention.

Detailed ways

The technical solutions of the present invention will be further elaborated below in conjunction with the accompanying drawings and specific embodiments.

The mapping device of the optical transport data unit of the present invention can directly map data from ODUk, such as ODU1, ODU2 to the TFI-5 bus; it can also first map data from ODUk to virtual container C-4-Xc, such as C-4- 17c, C_4_68c, and then mapped to the TFI-5 bus from C-4-Xc.

Among them, the data transmission rate of ODU1 is 2.498775126Gbps, the data transmission rate of ODU2 is 10.037273924Gbps, and the data transmission rate of TFI-5 is 2.48832Gbps, then 5 TFI-5 buses can accommodate 4 channels of ODU1 or 1 channel of ODU2. When mapping data from ODUk to virtual container C-4-Xc, according to the OIF-TFI-5-01.0 agreement, the data of ODU1 can be mapped to C-4-17c, and the data of ODU2 can be mapped to C-4 -68c.

The following takes the mapping of ODU1 data as an example to illustrate the data structures of C-4-17c and TFI-5. The OIF-TFI-5-01.0 protocol stipulates that there are 884 bytes in a C-4-17c data block, divided into 17 small blocks, each with 52 bytes, and the first byte of each small block It is an adjustment byte, including adjustment bytes R, J and a negative adjustment opportunity byte S, and the last 51 bytes are data bytes, which are valid data used to fill ODU1. Figure 1 shows a schematic diagram of the C-4-17c data block, which contains 17 small blocks, a total of 11 R bytes and 5 J bytes, and the filling basis of R and J bytes in the C-4-17c data block The fixed principle stipulated in the OIF-TFI-5-01.0 agreement; D is valid data of 51 bytes per small block; it should be pointed out that the first byte of the last small block can be filled with S bytes or The valid data of ODU1, that is, the byte is a data byte; among them, it can be judged based on 5 J bytes whether the first byte of the last small block is S byte, specifically, the last byte of J byte The bit is the adjustment opportunity bit C, 5 J bytes of C form CCCCC, if CCCCC=00000, the first byte of the last small block is a data byte; if CCCCC=11111, the first byte of the last small block One byte fills S bytes. It should be pointed out that the value of CCCCC follows the principle of majority judgment, that is, when the values of five Cs are mostly 1, judge CCCCC=11111, and when the values of five Cs are mostly 0, judge CCCCC=00000.

After mapping the data of ODU1 to C-4-17c, map the data in C-4-17c to the TFI-5 bus. Figure 2 is a schematic diagram of the time slot allocation of the C-4-17c data block on the TFI-5 bus, including 5 TFI-5 buses, which are used to accommodate 4 ODU1s, and each ODU1 occupies a column of the TFI-5 in turn. For example, the 161st column, 165th column, 169th column, 173rd column, etc. are the first ODU1, where the number padding corresponds to the sequence of valid data bytes in C-4-17c; the column occupied by the twill padding is the second ODU1, dot The column occupied by the shape fill is the third ODU1, and the column occupied by the grid fill is the fourth ODU1. Each TFI-5 bus has 4320 time slots, and each time slot can be filled with one byte, among which the first 160 time slots are filled with overhead bytes, from the 161st time slot to the 4320th time slot are used to fill C- Data from 4-17c. It should be pointed out that the data of the C-4-17c data block corresponding to 1 ODU1 is written into a column of TFI-5 in byte order, and 3 time slots are free every 17 time slots. Free time slots are used to fill fixed filling bytes, as shown in Figure 2, the time slots filled in gray are free time slots.

It should be pointed out that the TFI-5 data structure obtained by directly mapping the ODUk data to the TFI-5 bus is the same as the TFI-5 data structure obtained by mapping the data to the TFI-5 bus through C-4-17c above, Taking the mapping of ODU1 data as an example, the data structures of TFI-5 obtained by the two mapping methods are shown in Figure 2.

In order to realize the mapping of the above-mentioned ODUk data, the mapping device of the optical transmission data unit of the present invention is as shown in Figure 3, comprising: a first-in-first-out (FIFO, First Input First Output) buffer 10 and a data assembly output module 20, wherein,

FIFO buffer 10, for reading ODUk data;

The data assembly output module 20 is configured to reassemble the data in the FIFO buffer 10, and write the reassembled ODUk data into the TFI-5 bus.

The device of the present invention will be described below in conjunction with specific embodiments. As shown in FIG. Monitoring module 40, counter 50, data source module 60 and control module 70, wherein,

1. The FIFO buffer 10 is used to read data in the ODUk. In practical applications, multiple FIFO buffers are required to read data in the ODUk at the same time, and the specific number of FIFO buffers depends on the data input bit width required by the system. The data input bit width refers to the number of bits of ODUk data that can be read by the FIFO buffer 10 at one time, and the data input bit width≤(FIFO data bit width×FIFO number), wherein the FIFO data bit width is 2n, and ⁿ is positive integer. Assuming that the data input bit width required by the system is 16 bits, and the FIFO data bit width is 2 ³ =8 bits, the number of FIFO buffers required is 2.

According to the embodiment of Fig. 3, it can be seen that after the FIFO buffer 10 reads the data in the ODUk, the data needs to be output to the data assembly output module 20, therefore, the present invention refers to the reading of the ODUk data by the FIFO buffer 10 as writing Data, outputting data to the data assembly output module 20 is referred to as read data. Following the above example where the number of FIFO buffers is 2, when FIFO buffer 10 writes ODUk data, two FIFO buffers need to be started at the same time; when writing data, write ODUk data into the FIFO buffer in sequence 1 column, as shown in Figure 5, is the data structure of FIFO buffer of the present invention, the data block of a FIFO buffer is divided into n FIFO fritters, then FIFO buffer 10 has n columns altogether, the size of each FIFO fritter Be FIFO data bit width, such as 8bit; Can set an identification address, i.e. FIFO address, for each FIFO small block by address setting module 30, this address also indicates the writing order of ODUk data simultaneously, as shown in Fig. 5 in FIFO register The FIFO address of the first FIFO small block of 1 is 1, the address of the first FIFO small block of FIFO buffer 2 is 2, the FIFO address of the second FIFO small block of FIFO buffer 1 is 3, and the FIFO buffer 2 The address of the second FIFO block is 4, and so on. When the data input bit width required by the system is 16 bits, FIFO buffer 1 and FIFO buffer 2 write 8-bit ODUk data at the same time. According to the FIFO address, FIFO buffer 1 writes the first 8-bit data of ODUk into the FIFO address. 1 FIFO small block; FIFO buffer 2 writes the second 8bit data of ODUk into the FIFO small block whose FIFO address is 2, and so on, FIFO buffer 10 writes ODUk data according to the FIFO address; among them, FIFO buffer 1 Data can be written simultaneously with FIFO buffer 2, or data can be written in the order of ODUk data. For example, after FIFO buffer 1 writes the first 8-bit data of ODUk, FIFO buffer 2 writes the second 8-bit data of ODUk .

At the same time, a FIFO write address can also be set for each FIFO small block in the FIFO buffer 10 through the address setting module 30. Preferably, when the initial state, that is, when no data is written, each FIFO small block is set The FIFO write address of each is 0. When writing data to the current FIFO small block for the first time, add 1 to the FIFO write address, then the current FIFO write address is 1; when writing data to the current FIFO small block for the second time , add 1 to the current FIFO write address, then the current FIFO write address is 2, and so on; it can be seen that two adjacent FIFO write addresses can be equal, or the previous FIFO write address 1 larger than the last FIFO write address, as shown in Figure 5, the two FIFO blocks with FIFO addresses 1 and 2 are adjacent FIFO blocks, when FIFO buffer 1 and FIFO buffer 2 write data at the same time , the FIFO write addresses of the above two FIFO small blocks are equal, and after the data is written, the FIFO write addresses of the two are increased by 1 at the same time; when the data is written in the FIFO buffer 1, the FIFO buffer 2 starts to write Data, at this time, the FIFO write address of the FIFO small block whose FIFO address is 1 is 1 larger than the FIFO write address of the FIFO small block whose FIFO address is 2.

In order to prevent the FIFO buffer 10 from writing address errors when writing data, that is, to write data into wrong FIFO small blocks, preferably, the device shown in Figure 4 can also include an address monitoring module 40, according to the FIFO set above The FIFO address and FIFO write address of the FIFO small block in the buffer 10 are used to monitor the state of the data written in the FIFO buffer 10. When an error occurs in the FIFO write address, the FIFO buffer 10 is notified to reset immediately, that is, an error occurs in the FIFO write address In the previous state, the FIFO buffer 10 continues to write data.

2. The data assembly output module 20 reassembles the data in the FIFO buffer 10, and writes the reassembled data into the TFI-5 bus.

Since the data structure of the TFI-5 bus contains ODUk data, fixed filling bytes and adjustment bytes, the data assembly output module 20 needs to select which data source can currently read data from, and the data source is the FIFO buffer ODUk data in 10, fixed filling byte and adjustment byte, preferably, the device of the present invention can also comprise a counter 50, when carrying out the selection of data source, can according to the data structure of TFI-5 bus line and counter 50 The current data that needs to be written to the TFI-5 time slot is obtained through calculation. As can be seen from the embodiments shown in Figures 1 and 2, for a specific ODUk type, such as ODU1, the data structure of the TFI-5 bus is fixed and will not be described here. Therefore, the current TFI can be calculated through the counter 50 -5 slots need to write data.

According to the calculation of the counter 50, if the ODUk data needs to be filled into the TFI-5 time slot currently, the data assembly output module 20 reads the data from the FIFO buffer 10, and writes the data into the current time slot of the TFI-5. Specifically, the data can be read out according to the FIFO address of the FIFO block in the FIFO buffer 10 and the FIFO read address. Wherein, the FIFO read address can be set for the FIFO small block in the FIFO buffer 10 by the address setting module 30, preferably, the FIFO read address initial value of all FIFO small blocks can be set to 0, when the first time from the current FIFO small block When reading data from a block, add 1 to its FIFO read address, then the FIFO read address will be changed to 1; 2, and so on. Assuming that the FIFO read address of a certain FIFO small block is x, according to the FIFO address, when confirming that the FIFO read address of the previous adjacent FIFO small block is x+1, then read from the FIFO small block whose FIFO read address is x out the data. When the data assembly output module 20 reads the required data according to the FIFO address and FIFO read address of the FIFO block in the FIFO buffer 10, the FIFO buffer 10 deletes the data from the corresponding FIFO block. Simultaneously, the address monitoring module 40 can also monitor the FIFO read address of the FIFO small block. When an error occurs in the FIFO read address, as the data assembly output module 20 reads data from a FIFO small block twice in a row, or does not read the data from the FIFO according to the FIFO address. When the data is read out from the small block, the address monitoring module 40 notifies the FIFO buffer 10 to reset immediately, and at the same time, the data assembly output module 20 re-reads the data whose FIFO read address is wrong.

It should be pointed out that since the data transmission rate of TFI-5 is different from that of ODUk, the data that the data assembly output module 20 can read from the FIFO buffer 10 at one time is different from the data bits that the FIFO buffer 10 can write at one time. The width may be different, assuming that the FIFO buffer 10 data output bit width set by the system is 40 bits, and the FIFO data bit width is 8 bits, then the data assembly output module 20 can simultaneously obtain FIFO small blocks with continuous FIFO addresses in five FIFO buffers 10 read data from.

According to the calculation of the counter 50, if the current TFI-5 time slot needs to be filled with fixed filling bytes, the data assembly output module 20 stops reading the ODUk data or stops reading the adjustment bytes, but reads the fixed filling bytes, And write the current time slot of TFI-5.

According to the calculation of the counter 50, if the current needs to fill the adjustment byte to the TFI-5 time slot, such as R, J or S byte, the data assembly output module 20 stops reading ODUk data, or stops reading the fixed filling byte , instead read the R, J or S byte and write to the current slot of the TFI-5. The specific choice of R, J or S byte is: R, J byte has a fixed position in the TFI-5 time slot, and S byte can be determined according to the last bit C of J byte, as shown in Figure 1 The determination of the S byte in the illustrated embodiment will not be repeated here.

Regarding the above-mentioned fixed stuffing bytes and adjustment bytes, the device of the present invention may further include a data source module 60 for providing the data assembly output module 20 with fixed stuffing bytes and adjustment bytes.

ODUk data can be directly mapped to the TFI-5 bus based on the coordination among the FIFO buffer 10, data assembly output module 20, address setting module 30, address monitoring module 40, counter 50 and data source module 60.

3. In order to ensure the normal and efficient work of the FIFO buffer 10 and the data assembly output module 20, the device of the present invention may also include a control module 70 for controlling the FIFO buffer 10 to read data from the ODUk; The data assembly output module 20 reassembles the data in the FIFO buffer 10 . For example, the control module 70 can generate the FIFO read and write enable signals according to the fullness status of the FIFO buffer 10 and the FIFO address. Since the data input bit width of the FIFO buffer 10 is different from the data output bit width, the data input and output of the FIFO buffer 10 are unbalanced. When the data stored in the FIFO buffer 10 data blocks is almost full, the control module 70 generates a FIFO read , write enable signal, speed up the readout of data in the FIFO buffer 10, slow down the writing of data; when the FIFO buffer 10 was fast empty, the control module 70 generates FIFO read and write enable signals, slow down the reading of data output and speed up the writing of data, maintain the FIFO buffer 10 in a balanced state, and maintain the stability of the FIFO buffer 10.

Simultaneously, FIFO read, write enabling signal also needs to produce according to the FIFO address, FIFO write address and FIFO read address of FIFO small block in FIFO buffer 10, as, can determine current can write data according to FIFO address and FIFO write address The FIFO address of the FIFO small block; the FIFO address of the FIFO small block that can currently read data can be determined according to the FIFO address and the FIFO read address.

In addition, the control module 70 can also control the data assembly output module 20 to select a data source according to the data structure of the TFI-5 bus and the counter 50, and control the data assembly output module 20 to write the selected data source into the TFI-5 bus, such as, According to the currently selected data source, the control module 70 controls the data assembly output module 20 to read data from the corresponding data source in the data source module 60, and write the data into the corresponding time slot of the TFI-5 bus.

Figure 6 shows the structure of the mapping device of Embodiment 2 of the optical transmission data unit of the present invention. Based on the device of this embodiment, data can be mapped from ODUk to C-4-Xc first, and then from C-4-Xc to TFI -5 bus, the device includes two parts ODUk_TO_C-4-Xc, the device that maps data from ODUk to C-4-Xc part and C-4-Xc_TO_TFI-5, that maps data from C-4-Xc to TFI- 5 bus part of the device. It can be seen from Figure 6 that the device structures of ODUk_TO_C-4-Xc and C-4-Xc_TO_TFI-5 are the same, and are the same as those of the device shown in Figure 4, and the coordinated working principle of each module is the same as the implementation shown in Figure 4 example, which will not be repeated here. The difference between Fig. 6 and the embodiment shown in Fig. 4 has the following points:

1. In the device of the ODUk_TO_C-4-Xc part, the data assembly output module 20 writes the ODUk data read from the FIFO buffer 10 into the C-4-Xc according to the data structure of C-4-Xc; at the same time, C-4 -In the device of the Xc_TO_TFI-5 part, the ODUk data to be written into the FIFO buffer 10 is read from the C-4-Xc, that is, the data assembly output module 20 of the ODUk_TO_C-4-Xc part passes the ODUk data through the C- 4-Xc provides the FIFO buffer 10 of the C-4-Xc_TO_TFI-5 part;

2. In the device of the ODUk_TO_C-4-Xc part, the data sources provided by the FIFO buffer 10 and the data source module 60 for the data assembly output module 20 are ODUk data and adjustment bytes respectively; the device of the C-4-Xc_TO_TFI-5 part Among them, the data source provided by the data source module 60 for the data assembly output module 20 is only fixed padding bytes, and the data provided by the FIFO buffer 10 for the data assembly output module 20 is C-4-Xc data, that is, ODUk data and adjustment byte;

3. In the device of the ODUk_TO_C-4-Xc part, the counter 50 needs to calculate the ODUk data and adjustment bytes that need to be written into the C-4-Xc according to the data structure of the C-4-Xc; C-4-Xc_TO_TFI -In the device of part 5, the counter 50 needs to calculate the C-4-Xc data and fixed filling bytes that need to be written to the TFI-5 bus according to the data structure of TFI-5;

4. The number of FIFO buffers 10 in the ODUk_TO_C-4-Xc part and the FIFO buffers 10 in the C-4-Xc_TO_TFI-5 part may be different, or the FIFO data bit width may be different. If the system sets the data input bit width of the FIFO buffer 10 in the device of the ODUk_TO_C-4-Xc part to 16 bits, and the FIFO data bit width is 8 bits, then the number of FIFO buffers is 2, and the FIFO buffer 10 outputs to the data assembly The output bit width of module 20 is 16 bits, that is, the output bit width of data assembly output module 20 to the FIFO buffer 10 of C-4-Xc_TO_TFI-5 part is 16 bits; The data output bit width of the FIFO buffer 10 is 40 bits, so the FIFO buffer 10 of this part needs to adopt three FIFO buffers with a FIFO data bit width of 16 bits.

In order to realize the above-mentioned mapping device, the present invention also provides a mapping method, as shown in FIG. 7 , including: a mapping method of an optical transmission data unit, the method including:

In step 701, the FIFO buffer reads ODUk data.

The FIFO buffer needs to read ODUk data according to the data input bit width preset by the system, and provide the ODUk data to the data assembly output module.

Step 702, the data assembly output module reassembles the ODUk data in the FIFO buffer, and writes the reassembled ODUk data into the TFI-5 bus.

The data assembly output module reassembles the ODUk data in the FIFO buffer as follows: the counter preset by the system calculates the data that needs to be written into the TFI-5 bus, such as ODUk data and adjustment words, based on the data structure of the TFI-5 bus. section, or fixed padding bytes, and then the data assembly output module reads the corresponding data and writes it into the TFI-5 bus.

In addition, the ODUk mapping method of the present invention can also first map ODUk data to C-4-Xc, and then map from C-4-Xc to TFI-5 bus, specifically: based on the embodiment of Figure 7, The data assembly output module reassembles the ODUk data in the FIFO buffer, and writes the reassembled ODUk data into C-4-Xc first; then, the FIFO buffer reads the C-4-Xc data; the data assembly output The module reassembles the C-4-Xc data in the FIFO buffer and writes it into the TFI-5 bus, thus completing the mapping of the ODUk data to the TFI-5 bus.

The above descriptions are only preferred embodiments of the present invention, and are not intended to limit the protection scope of the present invention.

Claims (10)

1. a light transmits the mapping device of data cell, it is characterized in that this device comprises: fifo fifo buffer and data assembling output module, wherein,

Described FIFO buffer is used to read light data cell ODUk data;

Described data assembling output module be used for the ODUk data of described FIFO buffer are re-assemblied, and the described ODUk data after will re-assemblying writes core bus interface standard TFI-5 bus.

2. transmit the mapping device of data cell according to the described light of claim 1, it is characterized in that this device further comprises control module, be used to control described FIFO buffer and read described ODUk data; Also be used to control described data assembling output module to the re-assemblying of described ODUk data, and control the data of described data assembling output module after and write described TFI-5 bus described re-assemblying.

3. transmit the mapping device of data cell according to the described light of claim 1, it is characterized in that, this device further comprises: the address setting module, be used for as required described FIFO buffer being divided into a plurality of FIFO fritters, and read the address for described FIFO fritter is provided with fifo address, FIFO write address and FIFO.

4. transmit the mapping device of data cell according to the described light of claim 3, it is characterized in that, described FIFO buffer also is used for according to described fifo address and described FIFO write address the described ODUk data that read being write described FIFO fritter;

This device further comprises: the address monitoring module is used for monitoring the state that described FIFO buffer writes described ODUk data described FIFO fritter according to described fifo address and described FIFO write address; And when described state makes a mistake, notify described FIFO buffer to reset immediately.

5. transmit the mapping device of data cell according to the described light of claim 3, it is characterized in that this device further comprises data source module sum counter, wherein,

Described data source module is used to described data assembling output module to provide to adjust byte and fixing byte of padding;

Described counter is used for calculating the data that current needs write described TFI-5 bus according to the data structure of described TFI-5 bus;

Correspondingly, described data assembling output module, also be used for writing the data of TFI-5 bus, from described FIFO fritter, read described ODUk data or from described data source module, read described adjustment byte or described fixedly byte of padding, and re-assembly according to described current needs.

6. according to the mapping device of claim 3 or 4 or 5 described light transmission data cells, it is characterized in that described data assembling output module also is used for reading the address according to described fifo address and described FIFO and reads described ODUk data from described FIFO fritter;

Described address monitoring module also is used for reading the address according to described fifo address and described FIFO and monitors described data assembling output module and read the state of described ODUk data from described FIFO fritter; And when described state makes a mistake, notify described FIFO buffer to reset immediately.

7. transmit the mapping device of data cell according to the described light of claim 1, it is characterized in that, described data assembling output module also be used for the ODUk data of described FIFO buffer are re-assemblied, and the described ODUk data after will re-assemblying writes virtual container C-4-Xc;

Correspondingly, described FIFO buffer also is used to read described C-4-Xc data.

8. transmit the mapping device of data cell according to the described light of claim 7, it is characterized in that,

Described data assembling output module also be used for the described C-4-Xc data of described FIFO buffer are re-assemblied, and the described C-4-Xc data after will re-assemblying writes described TFI-5 bus.

9. a light transmits the mapping method of data cell, it is characterized in that this method comprises:

The FIFO buffer reads the ODUk data;

Data assembling output module re-assemblies the ODUk data in the described FIFO buffer, and the described ODUk data after will re-assemblying write the TFI-5 bus.

10. transmit the mapping method of data cell according to the described light of claim 9, it is characterized in that this method further comprises:

Described data assembling output module re-assemblies the ODUk data in the described FIFO buffer, and the described ODUk data after will re-assemblying write C-4-Xc;

Described FIFO buffer reads described C-4-Xc data;

Described data assembling output module re-assemblies described C-4-Xc data, and writes described TFI-5 bus.

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