CN101938454A - Mapping device and method for optical transport data units - Google Patents

Abstract

The invention discloses a mapping device for optical transport data units, which comprises a first-in first-out (FIFO) cache and a data assembly and output module, wherein the FIFO cache is used for reading optical data unit (ODUk) data; and the data assembly and output module is used for reassembling the ODUk data in the FIFO cache, and writing the reassembled ODUk data into a backboard bus interface standard (TFI-5) bus. The invention also provides a mapping method for the optical transport data units. Through the device and the method, the ODUk data can be mapped onto the TFI-5 bus.

Description

A kind of light transmits the mapping device and the method for data cell

Technical field

The present invention relates to light and transmit the field, be meant that especially a kind of light transmits the mapping device and the method for data cell.

Background technology

Along with the develop rapidly of the communication technology, the develop rapidly of data services such as communication network institute data carried by data traffic carrying capacity sharp increase, particularly broadband, IPTV, video has proposed new requirement to the transmission network of operator.Transmitting network wants the magnanimity bandwidth that adapts to this Data Growth can be provided, the more important thing is and transmit the service dispatching that network wants to carry out fast and flexible, provide and improve network operation management easily, as operation management maintain (OAM, Operation Administration and Maintenance) function is to adapt to the demand of data service.

Optical transfer network (OTN, Optical Transport Network) is the telecommunication standards group (ITU-T of International Telecommunications Union, ITU Telecommunication Standardization Sector) the optical communication Backbone Transport Network network standard of Zhi Dinging, the appearance of OTN have brought new opportunity for the transmission networks development.With synchronous digital hierarchy (SDH, Synchronous Digital Hierarchy) compare, OTN has stronger networking capability, possesses good extensibility, supports multiple upper-layer service or agreement, client signal is carried out transparent fully transmission, provides plural serial stage to connect function for monitoring and has stronger forward error correction ability; OTN can also provide and the same high bandwidth of wavelength division multiplexing (WDM, Wavelength Division Multiplexing) simultaneously.Therefore, OTN will become the main networking technology that transmits network, particularly backbone layer of future generation.

TFI-5 (TDM Fabric to Framer Interface-5) is by the light interconnected (OIF of forum that networks, OpticalInternetworking Forum) a kind of synchronous optical network (SONET that is similar to of Zhi Dinging, SynchronousOptical Network)/the core bus interface standard of SDH, be used for connecting framer and the time division multiplexing and the multiplexer (TDM of miscellaneous service, Time Division Multiplex and Multiplexer) intersection equipment, TFI-5 supports the service signal of agreements such as SONET/SDH, OTN.

Transmission data among the OTN will be shone upon when intersecting on the TFI-5 bus, and intersection equipment intersects to the TFI-5 bus, separates the transmission data that map out optical-fiber network from the TFI-5 bus again after having intersected.Wherein, existing OIF-TFI-5-01.0 agreement has proposed the mapping thought that a kind of light transmits data cell at transmitting data map to the TFI-5 bus: whole mapping process is divided into two goes on foot and finish, be specially earlier data from light data cell (ODUk, Optical Data Unit, k=1,2,3) be mapped to virtual container C-4-Xc, be mapped to the TFI-5 bus from C-4-Xc again.But, also do not have a kind of concrete execution mode to support and realize above-mentioned thought at present.

Summary of the invention

In view of this, main purpose of the present invention is to provide a kind of light to transmit the mapping device and the method for data cell, OTN can be transmitted data map to the TFI-5 bus.

For achieving the above object, technical scheme of the present invention is achieved in that

The invention provides the mapping device that a kind of light transmits data cell, this device comprises: fifo fifo buffer and data assembling output module, wherein,

Described FIFO buffer is used to read light data cell ODUk data;

Described data assembling output module be used for the ODUk data of described FIFO buffer are re-assemblied, and the described ODUk data after will re-assemblying writes core bus interface standard TFI-5 bus.

Wherein, this device further comprises control module, is used to control described FIFO buffer and reads described ODUk data; Also be used to control described data assembling output module to the re-assemblying of described ODUk data, and control the data of described data assembling output module after and write described TFI-5 bus described re-assemblying.

This device further comprises: the address setting module is used for as required described FIFO buffer being divided into a plurality of FIFO fritters, and reads the address for described FIFO fritter is provided with fifo address, FIFO write address and FIFO.

Described FIFO buffer also is used for according to described fifo address and described FIFO write address the described ODUk data that read being write described FIFO fritter;

This device further comprises: the address monitoring module is used for monitoring the state that described FIFO buffer writes described ODUk data described FIFO fritter according to described fifo address and described FIFO write address; And when described state makes a mistake, notify described FIFO buffer to reset immediately.

This device further comprises data source module sum counter, wherein,

Described data source module is used to described data assembling output module to provide to adjust byte and fixing byte of padding;

Described counter is used for calculating the data that current needs write described TFI-5 bus according to the data structure of described TFI-5 bus;

Correspondingly, described data assembling output module, also be used for writing the data of TFI-5 bus, from described FIFO fritter, read described ODUk data or from described data source module, read described adjustment byte or described fixedly byte of padding, and re-assembly according to described current needs.

It is characterized in that described data assembling output module also is used for reading the address according to described fifo address and described FIFO and reads described ODUk data from described FIFO fritter;

Described address monitoring module also is used for reading the address according to described fifo address and described FIFO and monitors described data assembling output module and read the state of described ODUk data from described FIFO fritter; And when described state makes a mistake, notify described FIFO buffer to reset immediately.

Described data assembling output module also be used for the ODUk data of described FIFO buffer are re-assemblied, and the described ODUk data after will re-assemblying writes virtual container C-4-Xc;

Correspondingly, described FIFO buffer also is used to read described C-4-Xc data.

Described data assembling output module also be used for the described C-4-Xc data of described FIFO buffer are re-assemblied, and the described C-4-Xc data after will re-assemblying writes described TFI-5 bus.

The present invention also provides a kind of light to transmit the mapping method of data cell, and this method comprises:

The FIFO buffer reads the ODUk data;

Data assembling output module re-assemblies the ODUk data in the described FIFO buffer, and the described ODUk data after will re-assemblying write the TFI-5 bus.

This method further comprises:

Described data assembling output module re-assemblies the ODUk data in the described FIFO buffer, and the described ODUk data after will re-assemblying write C-4-Xc;

Described FIFO buffer reads described C-4-Xc data;

Described data assembling output module re-assemblies described C-4-Xc data, and writes described TFI-5 bus.

Light of the present invention transmits the mapping device of data cell, by the co-ordination of first in first out (FIFO) buffer and data assembling output module, reads the ODUk data by the FIFO buffer; By data assemblings output module the ODUk data in the FIFO buffer are re-assemblied again, and the ODUk data after will re-assemblying write the TFI-5 bus, so can be directly with the ODUk data map on the TFI-5 bus; Light of the present invention transmits the mapping device of data cell, can also earlier the ODUk data map be arrived C-4-Xc by the co-ordination of FIFO buffer and data assembling output module; Again with the C-4-Xc data map on the TFI-5 bus, so can be indirectly with the ODUk data map on the TFI-5 bus.

Description of drawings

Fig. 1 is a C-4-17c data block schematic diagram;

Fig. 2 is the time slot allocation schematic diagram of C-4-17c data block on the TFI-5 bus;

Fig. 3 transmits the mapping device structural representation of data cell for light of the present invention;

Fig. 4 implements one mapping device structural representation for light of the present invention transmits data cell;

Fig. 5 is the data structure schematic diagram of FIFO buffer of the present invention;

Fig. 6 implements two mapping device structural representation for light of the present invention transmits data cell;

Fig. 7 transmits data cell mapping method schematic flow sheet for light of the present invention.

Embodiment

The technical solution of the present invention is further elaborated below in conjunction with the drawings and specific embodiments.

Light of the present invention transmits the mapping device of data cell can be with data from ODUk, map directly to the TFI-5 bus as ODU1, ODU2; Also can be earlier with data from ODUk be mapped to virtual container C-4-Xc, as C-4-17c, C_4_68c, be mapped to the TFI-5 bus from C-4-Xc again.

Wherein, the message transmission rate of ODU1 is 2.498775126Gbps, and the message transmission rate of ODU2 is 10.037273924Gbps, and the message transmission rate of TFI-5 is 2.48832Gbps, and then 5 TFI-5 buses can be held 4 road ODU1 or 1 road ODU2.When with data when ODUk is mapped to virtual container C-4-Xc, according to the regulation of OIF-TFI-5-01.0 agreement, can be with the data map of ODU1 to C-4-17c, with the data map of ODU2 to C-4-68c.

With the example that is mapped as of ODU1 data, the data structure of C-4-17c and TFI-5 is described below.OIF-TFI-5-01.0 agreement regulation, 884 bytes are arranged in the C-4-17c data block, be divided into 17 fritters, 52 bytes of every fritter, first byte of each fritter is for adjusting byte, comprise and adjust byte R, J and negative justification opportunity byte S, and back 51 bytes are data byte, promptly are used for filling the valid data of ODU1.Figure 1 shows that C-4-17c data block schematic diagram, comprise 17 fritters, totally 11 R bytes and 5 J bytes, R and the filling of J byte in the C-4-17c data block are according to the settled principle of OIF-TFI-5-01.0 agreement regulation; D is the valid data of 51 bytes of every fritter; First byte that it is pointed out that last fritter can be filled the S byte, also can fill the valid data of ODU1, promptly this byte is a data byte; Wherein, can judge whether first byte of last fritter is the S byte according to 5 J bytes, concrete, last bit of J byte is for adjusting chance bit C, the C of 5 J bytes forms CCCCC, if CCCCC=00000, then first byte of last fritter is a data byte; If CCCCC=11111, then first byte of last fritter is filled the S byte.The value that it is pointed out that CCCCC is followed the majority vote principle, promptly when the value majority of 5 C is 1, judges CCCCC=11111, when the value majority of 5 C is 0, judges CCCCC=00000.

Behind the data map C-4-17c with ODU1, again the data map among the C-4-17c is arrived the TFI-5 bus.Figure 2 shows that the time slot allocation schematic diagram of C-4-17c data block on the TFI-5 bus, comprise 5 TFI-5 buses, be used for holding 4 road ODU1, every road ODU1 takies the row of TFI-5 in turn, as the 161st row, 165 row, 169 row, 173 row etc. is the 1 road ODU1, and wherein numeral has filled the order of valid data byte among the C-4-17c corresponding; Twill fill take one classify as the 2 road ODU1, point-like fill take one classify as the 3 road ODU1, grid fill take one classify the 4 road ODU1 as.Every TFI-5 bus has 4320 time slots, and each time slot can be filled a byte, and wherein preceding 160 time slots are filled overhead byte, are used for filling the data of C-4-17c from 4320 time slots of the 161st time slot to the.It is to be noted, the data of the C-4-17c data block of 1 road ODU1 correspondence are write among the row TFI-5 successively according to byte order, and go out 3 time slots every 17 time slot free time, these 3 idle time slots are used for filling fixedly byte of padding, and the time slot of filling as grey among Fig. 2 is idle time slot.

It is to be noted, directly the TFI-5 data structure that the data map of ODUk is obtained on the TFI-5 bus is with above-mentioned identical with the TFI-5 data structure that data map obtains on the TFI-5 bus by C-4-17c, with the example that is mapped as of ODU1 data, the data structure of the TFI-5 that two kinds of mapping modes obtain all as shown in Figure 2.

In order to realize the mapping of above-mentioned ODUk data, the mapping device of light transmission data cell of the present invention comprises as shown in Figure 3: first in first out (FIFO, First Input First Output) buffer 10 and data assembling output module 20, wherein,

FIFO buffer 10 is used to read the ODUk data;

Data assembling output module 20 be used for the data of FIFO buffer 10 are re-assemblied, and the ODUk data after will re-assemblying writes the TFI-5 bus.

Below in conjunction with specific embodiment device of the present invention is described, be illustrated in figure 4 as the mapping device that light of the present invention transmits data cell enforcement one, comprise: FIFO buffer 10, data assembling output module 20, address setting module 30, address monitoring module 40, counter 50, data source module 60 and control module 70, wherein

1, FIFO buffer 10 is used for reading the data of ODUk.In the application of reality, a plurality of FIFO buffers of needs use read the data among the ODUk simultaneously, and concrete FIFO buffer quantity depends on the data input bit wide of system requirements.This data input bit wide is meant the bit number of the ODUk data that FIFO buffer 10 once can read, data input bit wide≤(data fifo bit wide * FIFO number), and wherein the data fifo bit wide is 2 ⁿ, n is a positive integer.The data input bit wide that supposing the system requires is 16bit, and the data fifo bit wide is 2 ³=8bit, the number that then needs the FIFO buffer is 2.

According to the embodiment of Fig. 3 as can be seen, after FIFO buffer 10 reads data among the ODUk, data need be exported to data assembling output module 20, therefore, the present invention reads the ODUk data with FIFO buffer 10 and is called and writes data, data are exported to data assemblings output module 20 be called sense data.Accept above-mentioned FIFO buffer number and be 2 example, when FIFO buffer 10 writes the ODUk data, need start 2 FIFO buffers simultaneously; When writing data, the ODUk data are write 1 row of FIFO buffer by the fifo address order, be illustrated in figure 5 as the data structure of FIFO buffer of the present invention, the data block of a FIFO buffer is divided into n FIFO fritter, FIFO buffer 10 total n row then, and the size of each FIFO fritter is the data fifo bit wide, as 8bit; Can a home address be set, be fifo address for each FIFO fritter by address setting module 30, this address has also been indicated the write sequence of ODUk data simultaneously, as the fifo address of the 1st FIFO fritter of FIFO buffer 1 among Fig. 5 be 1, the address of the 1st FIFO fritter of FIFO buffer 2 is 2, the fifo address of the 2nd FIFO fritter of FIFO buffer 1 is 3, the address of the 2nd FIFO fritter of FIFO buffer 2 is 4, by that analogy.When the data of system requirements input bit wide was 16bit, FIFO buffer 1 and FIFO buffer 2 write the ODUk data of 8bit simultaneously, and according to fifo address, it is 1 FIFO fritter that FIFO buffer 1 writes fifo address with the data of the 1st 8bit of ODUk; It is 2 FIFO fritter that FIFO buffer 2 writes fifo address with the data of the 2nd 8bit of ODUk, and by that analogy, FIFO buffer 10 writes the ODUk data according to fifo address; Wherein FIFO buffer 1 and FIFO buffer 2 can write data simultaneously, also can write data according to the order of ODUk data, write the 1st 8bit data of ODUk as FIFO buffer 1 after, FIFO buffer 2 writes the 2nd 8bit data of ODUk again.

Simultaneously, can also for each the FIFO fritter in the FIFO buffer 10 a FIFO write address be set by address setting module 30, preferably, when initial condition, when also not writing data, the FIFO write address that each FIFO fritter is set all is 0, for the first time when current FIFO fritter writes data, its FIFO write address is added 1, then current FIFO write address is 1; When current FIFO fritter writes data, add 1 again on the basis of current FIFO write address for the second time, then current FIFO write address is 2, by that analogy; This shows, two adjacent FIFO write addresses can equate, perhaps previous FIFO write address is bigger by 1 than a back FIFO write address, as shown in Figure 5, fifo address is that two FIFO fritters of 1 and 2 are adjacent FIFO fritter, and when FIFO buffer 1 and FIFO buffer 2 write data simultaneously, the FIFO write address of above-mentioned two FIFO fritters equated, and after writing data, both FIFO write addresses add 1 simultaneously; After FIFO buffer 1 write data, FIFO buffer 2 just began to write data, and this moment, fifo address was that the FIFO write address of 1 FIFO fritter is that the FIFO write address of 2 FIFO fritter is big by 1 than fifo address.

In order to prevent that FIFO buffer 10 from the write address mistake taking place, be about to data write error FIFO fritter by mistake when writing data, preferably, device shown in Figure 4 can also comprise an address monitoring module 40, fifo address and FIFO write address according to FIFO fritter in the FIFO buffer 10 of above-mentioned setting are monitored the state that FIFO buffer 10 writes data, when FIFO write address mistake takes place when, notice FIFO buffer 10 resets immediately, promptly get back to the state of FIFO write address before making a mistake, FIFO buffer 10 continues to write data.

2, the data in 20 pairs of FIFO buffers 10 of data assembling output module re-assembly, and the data after will re-assemblying write the TFI-5 bus.

Owing to contain ODUk data, fixedly byte of padding and adjustment byte in the data structure of TFI-5 bus, therefore data assembling output module 20 need to select current can from which data source sense data, described data source is ODUk data in the FIFO buffer 10, fixing byte of padding and adjust byte, preferably, device of the present invention can also comprise a counter 50, when carrying out the selection of data source, can be according to the data structure sum counter 50 of TFI-5 bus by calculating the data that current needs write to the TFI-5 time slot.By embodiment illustrated in figures 1 and 2 as can be known, for concrete ODUk type, as ODU1, the data structure of TFI-5 bus is fixed, and repeats no more herein, therefore, just can calculate the data that current TFI-5 time slot need write by counter 50.

According to the calculating of counter 50, need be when the TFI-5 time slot to be filled the ODUk data if current, data are assembled output module 20 from FIFO buffer 10 sense datas, and these data are write the current time slot of TFI-5.Concrete, can read the address according to the fifo address of FIFO fritter in the FIFO buffer 10 and FIFO and come sense data.Wherein, can for being provided with FIFO, the FIFO fritter in the FIFO buffer 10 read the address by address setting module 30, preferably, it is 0 that the FIFO that all FIFO fritters can be set reads the address initial value, when for the first time from current FIFO fritter reading of data, its FIFO is read the address add 1, then to read address change be 1 to FIFO; During for the second time from current FIFO fritter reading of data, its FIFO is read the address add 1 again, then to read address change be 2 to FIFO, by that analogy.It is x that the FIFO that supposes some FIFO fritters reads the address, and according to fifo address, the FIFO that confirms the previous FIFO fritter that it is adjacent reads the address when being x+1, then reads sense data the FIFO fritter that the address is x from FIFO.When data assemblings output module 20 according to FIFO buffer 10 in the fifo address of FIFO fritter and FIFO read after the address reads required data, FIFO buffer 10 is deleted these data from the FIFO fritter of correspondence.The FIFO that while address monitoring module 40 can also be monitored the FIFO fritter reads the address, when FIFO reads the address when making a mistake, as data assemblings output module 20 double from a FIFO fritter sense data or not according to fifo address sense data from the FIFO fritter, then monitoring module 40 notice FIFO buffers 10 in address reset immediately, and the output module 20 of data assembling is simultaneously read FIFO again and read the data that make a mistake in the address.

It is to be noted, because the message transmission rate of TFI-5 is different with the message transmission rate of ODUk, so the data that data assembling output module 20 once can be read from FIFO buffer 10 are different with the data bit width possibility that FIFO buffer 10 once can write, the FIFO buffer 10 data output bit wide that supposing the system is set is 40bit, the data fifo bit wide is 8bit, then data assemblings output module 20 can be simultaneously from 5 FIFO buffers 10 sense data in the continuous FIFO fritter of fifo address.

According to the calculating of counter 50, need be when the TFI-5 time slot to be filled fixedly byte of padding if current, data are assembled output module 20 and are stopped to read the ODUk data or stop to read the adjustment byte, but read fixedly byte of padding, and write the current time slot of TFI-5.

Calculating according to counter 50, if it is current need be when the TFI-5 time slot fill to be adjusted byte, the time as R, J or S byte, data assembling output module 20 stops to read the ODUk data or stops to read fixedly byte of padding, but reads R, J or S byte, and writes the current time slot of TFI-5.Being chosen as of concrete R, J or S byte: R, J byte have fixing position in the TFI-5 time slot, and the S byte can be judged according to last bit C of J byte, about the judgement of S byte, repeats no more among the embodiment as shown in Figure 1 herein.

At said fixing byte of padding and adjustment byte, device of the present invention can also comprise a data source module 60, is used to data assembling output module 20 that fixedly byte of padding and adjustment byte are provided.

Based on the co-ordination between above-mentioned FIFO buffer 10, data assembling output module 20, address setting module 30, address monitoring module 40, counter 50 and the data source module 60 just can be directly with the ODUk data map on the TFI-5 bus.

3, for guarantee FIFO buffer 10 and data the assembling output module 20 normally and efficiently work, device of the present invention can also comprise a control module 70, is used for controlling FIFO buffer 10 from the ODUk reading of data; The data that also are used for 20 pairs of FIFO buffers 10 of control data assembling output module re-assembly.As, control module 70 can be according to the sky of FIFO buffer 10 full state and fifo address produce FIFO reading and writing enable signal.Because the data of FIFO buffer 10 input bit wide is different with data output bit wide, so data input and output imbalance of FIFO buffer 10, when the data of FIFO buffer 10 data block store expire soon, control module 70 produces FIFO reading and writing enable signal, and the data of reading, slow down of data writes in the quickening FIFO buffer 10; Fast when empty when FIFO buffer 10, control module 70 produces FIFO reading and writing enable signals, the data that slow down read, accelerate writing of data, make FIFO buffer 10 maintain the state of a balance, kept the stability of FIFO buffer 10.

Simultaneously, FIFO reading and writing enable signal also needs to read the address according to the fifo address of FIFO fritter in the FIFO buffer 10, FIFO write address and FIFO and produces, as, can determine the current fifo address that can write the FIFO fritter of data according to fifo address and FIFO write address; Read the fifo address that current FIFO fritter that can sense data can be determined in the address according to fifo address and FIFO.

In addition, control module 70 can also be according to the data structure sum counter 50 of TFI-5 bus, control data assembling output module 20 is selected data source, and control data assembling output module 20 writes the TFI-5 bus with the data source of selecting, as, according to the data source that current needs are selected, control module 70 control datas assembling output module 20 corresponding data source sense data from data source module 60, and write the corresponding time slot of TFI-5 bus.

Figure 6 shows that light of the present invention transmits the mapping device structure of data cell embodiment two, device based on this embodiment, can earlier data be mapped to C-4-Xc from ODUk, be mapped to the TFI-5 bus from C-4-Xc again, this device comprises two parts ODUk_TO_C-4-Xc, be about to data from ODUk be mapped to the C-4-Xc part device and C-4-Xc_TO_TFI-5, be about to data are mapped to the TFI-5 bus portion from C-4-Xc device.As can be seen from Figure 6, ODUk_TO_C-4-Xc is identical with the apparatus structure of C-4-Xc_TO_TFI-5 part, and the structure with device shown in Figure 4 is identical respectively, and wherein the co-ordination principle of each module repeats no more with embodiment shown in Figure 4 herein.Fig. 6 and embodiment shown in Figure 4 different have following some:

1, in the device of ODUk_TO_C-4-Xc part, the ODUk data that data assembling output module 20 will be read from FIFO buffer 10 write the C-4-Xc according to the data structure of C-4-Xc; Simultaneously in the device of C-4-Xc_TO_TFI-5 part, the ODUk data that FIFO buffer 10 need write read from C-4-Xc, i.e. ODUk_TO_C-4-Xc partial data assembling output module 20 offers the ODUk data FIFO buffer 10 of C-4-Xc_TO_TFI-5 part by C-4-Xc;

2, in the device of ODUk_TO_C-4-Xc part, the data source that FIFO buffer 10 and data source module 60 provide for data assembling output module 20 is respectively the ODUk data and adjusts byte; In the device of C-4-Xc_TO_TFI-5 part, the data source that data source module 60 provides for data assemblings output module 20 only is fixing byte of padding, and FIFO buffer 10 is the C-4-Xc data, is ODUk data and adjustment byte for the data that data assembling output module 20 provides;

3, in the device of ODUk_TO_C-4-Xc part, counter 50 need calculate the current ODUk data that need write according to the data structure of C-4-Xc and adjust byte in C-4-Xc; In the device of C-4-Xc_TO_TFI-5 part, counter 50 need calculate current C-4-Xc data that need write to the TFI-5 bus and fixing byte of padding according to the data structure of TFI-5;

4, the FIFO buffer 10 of ODUk_TO_C-4-Xc part may be different with the number or the data fifo bit wide of the FIFO buffer 10 of C-4-Xc_TO_TFI-5 part.Data input bit wide as FIFO buffer 10 in the device of default ODUk_TO_C-4-Xc part is 16bit, the data fifo bit wide is 8bit, then FIFO buffer number is 2, and FIFO buffer 10 is 16bit to the bit wide of data assembling output module 20 outputs, i.e. data assembling output module 20 is 16 bits to the output bit wide of the FIFO buffer 10 of C-4-Xc_TO_TFI-5 part; If the data output bit wide of the FIFO buffer 10 of default C-4-Xc_TO_TFI-5 part is 40 bits, then the FIFO buffer 10 of this part needs to adopt 3 FIFO buffers that the data fifo bit wide is 16bit.

In order to realize above-mentioned mapping device, the present invention also provides a kind of mapping method, as shown in Figure 7, comprising: a kind of light transmits the mapping method of data cell, and this method comprises:

Step 701, the FIFO buffer reads the ODUk data.

The FIFO buffer need read the ODUk data according to the data input bit wide of systemic presupposition, and these ODUk data are offered data assembling output module.

Step 702, data assembling output module re-assemblies the ODUk data in the FIFO buffer, and the ODUk data after will re-assemblying write the TFI-5 bus.

Data assemblings output module to the ODUk data in the FIFO buffer re-assembly into: the counter of systemic presupposition is according to the data structure of TFI-5 bus, calculate data that current needs write the TFI-5 bus, as the ODUk data, adjust byte or fixing byte of padding, data are assembled the output module reading corresponding data then, and write the TFI-5 bus.

In addition, the mapping method that light of the present invention transmits data cell can also arrive C-4-Xc with the ODUk data map earlier, be mapped to the TFI-5 bus from C-4-Xc again, be specially: based on the embodiment of Fig. 7, data assembling output module re-assemblies the ODUk data in the FIFO buffer, and the ODUk data after will re-assemblying write C-4-Xc earlier; Then, the FIFO buffer reads the C-4-Xc data; Data assembling output module re-assemblies the C-4-Xc data in the FIFO buffer, and writes the TFI-5 bus, finishes the mapping of ODUk data to the TFI-5 bus thus.

The above is preferred embodiment of the present invention only, is not to be used to limit protection scope of the present invention.

Claims (10)

1. a light transmits the mapping device of data cell, it is characterized in that this device comprises: fifo fifo buffer and data assembling output module, wherein,

Described FIFO buffer is used to read light data cell ODUk data;

Described data assembling output module be used for the ODUk data of described FIFO buffer are re-assemblied, and the described ODUk data after will re-assemblying writes core bus interface standard TFI-5 bus.

2. transmit the mapping device of data cell according to the described light of claim 1, it is characterized in that this device further comprises control module, be used to control described FIFO buffer and read described ODUk data; Also be used to control described data assembling output module to the re-assemblying of described ODUk data, and control the data of described data assembling output module after and write described TFI-5 bus described re-assemblying.

3. transmit the mapping device of data cell according to the described light of claim 1, it is characterized in that, this device further comprises: the address setting module, be used for as required described FIFO buffer being divided into a plurality of FIFO fritters, and read the address for described FIFO fritter is provided with fifo address, FIFO write address and FIFO.

4. transmit the mapping device of data cell according to the described light of claim 3, it is characterized in that, described FIFO buffer also is used for according to described fifo address and described FIFO write address the described ODUk data that read being write described FIFO fritter;

This device further comprises: the address monitoring module is used for monitoring the state that described FIFO buffer writes described ODUk data described FIFO fritter according to described fifo address and described FIFO write address; And when described state makes a mistake, notify described FIFO buffer to reset immediately.

5. transmit the mapping device of data cell according to the described light of claim 3, it is characterized in that this device further comprises data source module sum counter, wherein,

Described data source module is used to described data assembling output module to provide to adjust byte and fixing byte of padding;

Described counter is used for calculating the data that current needs write described TFI-5 bus according to the data structure of described TFI-5 bus;

Correspondingly, described data assembling output module, also be used for writing the data of TFI-5 bus, from described FIFO fritter, read described ODUk data or from described data source module, read described adjustment byte or described fixedly byte of padding, and re-assembly according to described current needs.

6. according to the mapping device of claim 3 or 4 or 5 described light transmission data cells, it is characterized in that described data assembling output module also is used for reading the address according to described fifo address and described FIFO and reads described ODUk data from described FIFO fritter;

Described address monitoring module also is used for reading the address according to described fifo address and described FIFO and monitors described data assembling output module and read the state of described ODUk data from described FIFO fritter; And when described state makes a mistake, notify described FIFO buffer to reset immediately.

7. transmit the mapping device of data cell according to the described light of claim 1, it is characterized in that, described data assembling output module also be used for the ODUk data of described FIFO buffer are re-assemblied, and the described ODUk data after will re-assemblying writes virtual container C-4-Xc;

Correspondingly, described FIFO buffer also is used to read described C-4-Xc data.

8. transmit the mapping device of data cell according to the described light of claim 7, it is characterized in that,

Described data assembling output module also be used for the described C-4-Xc data of described FIFO buffer are re-assemblied, and the described C-4-Xc data after will re-assemblying writes described TFI-5 bus.

9. a light transmits the mapping method of data cell, it is characterized in that this method comprises:

The FIFO buffer reads the ODUk data;

Data assembling output module re-assemblies the ODUk data in the described FIFO buffer, and the described ODUk data after will re-assemblying write the TFI-5 bus.

10. transmit the mapping method of data cell according to the described light of claim 9, it is characterized in that this method further comprises:

Described data assembling output module re-assemblies the ODUk data in the described FIFO buffer, and the described ODUk data after will re-assemblying write C-4-Xc;

Described FIFO buffer reads described C-4-Xc data;

Described data assembling output module re-assemblies described C-4-Xc data, and writes described TFI-5 bus.

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