CN101931833A - Device and method for realizing demapping of optical channel data unit - Google Patents

Abstract

The invention discloses a device and method for realizing demapping of an optical channel data unit. The device comprises a control module and a storage module, wherein the storage module comprises a plurality of first-in first-out storages (FIFO storages); the control module is used for controlling the storage module to write bytes, which are judged as valid data, into the FIFO storages when data from the TFI-5 bus comes, and controlling the FIFO storages to read the stored valid data according to the data size fed back by the storage module; the FIFO storages are used for writing and caching the written valid data or reading the stored valid data; and the storage module is used for feeding the data size stored in the FIFO storages to the control module. The invention simplifies the mapping steps and enables the circuit structure to be more simple and reliable.

Description

The realization Optical Channel Data Unit-k is separated the device and method of mapping

Technical field

The present invention relates to communication technical field, relate in particular to a kind of Optical Channel Data Unit-k of realizing and separate the device and method of mapping.

Background technology

TFI-5 is a kind of core bus interface standard of being worked out by OIF (Optical Internetworking Forum, optical-fiber network forum), is used for connecting the framer and TDM (Time Division Multiplex, time division multiplexing) the intersection equipment of miscellaneous service.The transmission data of optical-fiber network will be shone upon when intersecting on the TFI-5 bus, and intersection equipment intersects to the TFI-5 bus data, separates the transmission data that map out optical-fiber network from the TFI-5 bus again after having intersected.

As shown in Figure 1, Fig. 1 is the schematic diagram of TFI-5 frame structure, and the frame structure of TFI-5 is the STM-16 structure, and speed is 2.48832Gbps.The speed of a kind of Optical Channel Data Unit-k ODU1 is 2.498775126Gbps, and the speed of another kind of Optical Channel Data Unit-k ODU2 is 10.037273924Gbps.Need hold 4 road ODU1 or 1 road ODU2 down with 5 road TFI-5 buses.Separate mapping and be signal (TFI-5 separates and is mapped to OUD1) or signal (TFI-5 separates and is mapped to ODU2) from the signal transition of 5 road 2.48832Gbps speed to 1 road 10.037273924Gbps speed from the signal transition of 5 road 2.48832Gbps speed to 4 road 2.498775126Gbps speed.

According to the regulation of OIF-TFI-5-01.0 agreement, the ODU1 data encapsulation is in the C_4_17c data block, and a C_4_17c data block has 884 bytes, and 884 block of bytes are divided into 17 fritters again, every fritter 52 bytes.First byte is for adjusting byte in 52 bytes, and 51 bytes are data byte thereafter.As shown in Figure 2, Fig. 2 is the schematic diagram of C_4_17c data block, and wherein D is the ODU1 data, and R and J are for adjusting byte, and S is the negative justification opportunity byte.The J byte also plays the effect that chance is judged of adjusting, and last bit of J byte is for adjusting chance bit C.CCCCC is formed in the C position of 5 J bytes, if CCCCC=00000 shows that the S byte is a data byte; If CCCCC=11111 shows that the S byte is for adjusting byte.The majority vote principle is followed in the judgement of S byte in the reality, if comprise 0 more than 3 or 3 in the CCCCC sequence, judges that then the S byte is an information byte; If comprise 1 more than 3 or 3 in the CCCCC sequence, judge that then the S byte is for adjusting byte.And then the C_4_17c data block is mapped on the TFI-5 bus.

As shown in Figure 3, Fig. 3 is the time slot allocation schematic diagram of C_4_17c data block on the TFI-5 bus, and C_4_17c takies 17 time slots on the TFI-5 bus, but one road ODU1 takies 20 time slots, remaining 3 time slot free time, fills fixedly byte of padding of C_4_3c.

According to the regulation of OIF-TFI-5-01.0 agreement, the ODU2 data encapsulation is in the C_4_68c data block, and a C_4_68c data block has 884 bytes, and 884 block of bytes are divided into 13 fritters again, every fritter 68 bytes.First byte is for adjusting byte in 68 bytes, and 67 bytes are data byte thereafter.As shown in Figure 4, Fig. 4 is the schematic diagram of C_4_68c data block, and wherein D is the ODU2 data, and R and J are for adjusting byte, and S is the negative justification opportunity byte.Last bit of J byte is for adjusting chance bit C, and CCCCC is formed in the C position of 5 J bytes, and therefore, the J byte also plays adjusts the effect that chance is judged to the S byte, if comprise 0 more than 3 or 3 in the CCCCC sequence, then the S byte is an information byte; If comprise 1 more than 3 or 3 in the CCCCC sequence, then the S byte is for adjusting byte.And then the C_4_68c data block is mapped on the TFI-5 bus.

As shown in Figure 5, Fig. 5 is the time slot allocation schematic diagram of C_4_68c data block on the TFI-5 bus, and C_4_68c takies 68 time slots on the TFI-5 bus, but one road ODU2 takies 80 time slots, remaining 12 time slot free time, fills fixedly byte of padding of C_4_12c.

In a word, according to the suggestion of OIF-TFI-5 agreement, ODUk (k=1 or 2) signal encapsulation earlier advances in C_4_Xc (X=17 or the 68) data block, C_4_Xc is mapped on the TFI-5 bus again.Therefore, separate to map out on the ODUk data principle from the TFI-5 bus and also be divided into for two steps, when the data on the TFI-5 bus arrive, at first separate from the TFI-5 bus and map out the C_4_Xc data block, deblocking takes on the ODUk data from the C_4_Xc data block again.If carry out the words of circuit design according to these two steps, per step is separated map operation all needs to use FIFO (First In First Out, first-in first-out) memory comes data cached and needs corresponding input and output control, and circuit structure is very complicated relatively, the waste chip area.

Summary of the invention

In view of above-mentioned analysis, the present invention aims to provide a kind of Optical Channel Data Unit-k of realizing and separates the device and method of mapping, in order to solve exist in the prior art separate the map operation complicated problems.

Purpose of the present invention mainly is achieved through the following technical solutions:

The invention provides a kind of data transfer unit that realizes and separate the device of mapping, comprising: control module, and the memory module that to comprise a plurality of FIFO memories be pushup storage, wherein,

Described control module, when being used for the data byte arrival on the TFI-5 bus, control the byte that described memory module will be judged to be valid data and write in the described FIFO memory, and control described FIFO memory according to described memory module feedback data amount and read wherein stored valid data;

Described FIFO memory is used for buffer memory and writes valid data wherein or read wherein stored valid data;

Described memory module is used for described FIFO memory data quantity stored is fed back to described control module.

Further, described control module specifically comprises: FIFO writes control unit and FIFO reads control unit, wherein,

Described FIFO writes control unit, when being used for the data byte arrival on the TFI-5 bus, judge that current byte is valid data or invalid data, if valid data, send write data and select signal and corresponding write control signal, controlling described memory module is written to current byte in the described FIFO memory, if invalid data then abandons;

Described FIFO reads control unit, is used for judging according to described memory module feedback data amount, sends read data and select signal and read control signal when determining to read valid data, controls described FIFO memory and reads wherein stored valid data.

Further, described FIFO writes control unit and specifically is used for, when the data byte on the TFI-5 bus arrives, judge the type of current byte, if valid data, then send write data and select signal and corresponding write control signal, control described memory module current byte is written in the described FIFO memory, if adjust in the byte the R byte or fixedly byte of padding then abandon; If the J byte in the adjustment byte then preserves the value of C position get off; If negative justification opportunity byte, then further judge that according to the predetermined decision principle this negative justification opportunity byte is valid data byte or adjustment byte, if valid data byte, then send write data and select signal and corresponding write control signal, control described memory module current byte is written in the described FIFO memory, then abandon if adjust byte.

Further, described memory module also is used for, and when described FIFO memory generation read/write, the read-write absolute address` of described FIFO memory is fed back to described control module in real time.

Described control module also comprises: the fifo address monitoring unit, be used for read-write state that read-write absolute address` according to each FIFO memory of described fifo module feedback monitors each described FIFO memory whether in correct address state scope, and when address state makes a mistake, send reset signal.

Further, described device also comprises: the FIFO write data is selected module, be used to receive described FIFO and write the write data selection signal that control unit is sent, and select signal to choose the valid data that write described FIFO memory from the TFI-5 bus according to write data.

Further, described device also comprises: the data selector of output is used to receive described FIFO and reads the read data selection signal that control unit is sent, and exports according to the data that described read data selects signal to select described FIFO memory to read.

The present invention also provides a kind of data transfer unit that realizes to separate the method for mapping, utilizes a kind of mapping device of separating, and described method comprises:

Steps A: when the data byte on the TFI-5 bus arrived, control module was controlled the current byte that described memory module will be judged to be valid data and is write in the described FIFO memory;

Step B: after described FIFO memory write and buffer memory writes wherein valid data, described memory module fed back to described control module with the data volume of described FIFO memory stores;

Step C: described control module is controlled described FIFO memory according to described memory module feedback data amount and is read the data of storing in the described FIFO memory.

Further, described steps A specifically comprises:

When the TFI-5 data byte arrives, FIFO writes the type that control unit is judged current byte, if valid data, then judge and current byte to be written in the described memory module, and send write data and select signal and corresponding write control signal, if adjust in the byte the R byte or fixedly byte of padding then abandon; If the J byte in the adjustment byte then preserves the value of C position get off; If negative justification opportunity byte, then further judge that according to the predetermined decision principle this negative justification opportunity byte is valid data byte or adjustment byte, if valid data byte, then judge this byte is written to described FIFO, and send write data selection signal and corresponding write control signal, then abandon if adjust byte.

Further, described step B specifically comprises:

The FIFO write data is selected module to write the write data that control unit sends according to described FIFO to select signal to choose the valid data that write described memory module from the TFI-5 bus;

The valid data that described memory module selects module to choose described FIFO write data according to described write control signal are written in each FIFO memory, and the data volume of described each FIFO memory stores is fed back to described control module.

Further, described step C specifically comprises:

Described FIFO reads control unit and controls described memory module output stored valid data according to described memory module feedback data amount, and is judging that sending read data when needing to export valid data selects signal and read control signal;

Described memory module is read the valid data of specifying in the FIFO memory according to the FIFO read data control signal that receives;

The data that described data selector selects signal to select described FIFO memory to read according to the read data that receives are exported.

Further, described method also comprises:

When described FIFO memory carried out read/write, described fifo module fed back the read-write absolute address` of each FIFO to the fifo address monitoring unit;

The read-write state that described fifo address monitoring unit monitors each FIFO according to the read-write absolute address` of described each FIFO and sends reset signal whether in correct address state scope when the address state mistake.

Beneficial effect of the present invention is as follows:

The present invention simplifies the understanding mapping steps, has realized directly separating from the TFI-5 bus mapping out the ODUk data.

Other features and advantages of the present invention will be set forth in the following description, and becoming apparent from specification of part perhaps understood by implementing the present invention.Purpose of the present invention and other advantages can realize and obtain by specifically noted structure in the specification of being write, claims and accompanying drawing.

Description of drawings

Fig. 1 is the schematic diagram of TFI-5 frame structure;

Fig. 2 is the schematic diagram of C_4_17c data block;

Fig. 3 is the time slot allocation schematic diagram of C_4_17c data block on the TFI-5 bus;

Fig. 4 is the schematic diagram of C_4_68c data block;

Fig. 5 is the time slot allocation schematic diagram of C_4_68c data block on the TFI-5 bus;

Fig. 6 is the described structural representation of separating mapping device of the embodiment of the invention;

Fig. 7 is the schematic flow sheet of the described de-mapping method of the embodiment of the invention.

Embodiment

The present invention simplifies the understanding mapping steps, and two steps of separating mapping are combined realization, realizes directly separating from the TFI-5 bus mapping out the ODUk data.It is as follows to separate the mapping techniques scheme:

It is disconnected when the TFI-5 data arrive that to declare current byte be ODUk information byte or fixedly byte of padding or adjustment byte, if current TFI-5 data are for fixedly byte of padding or adjustment byte then abandon, if current byte is that the ODUk information byte then obtains to get off to be written in the FIFO memory, come buffer memory ODUk data with the FIFO memory.Thereby just realized removing fixedly byte of padding and this two steps operation of adjustment byte in the process that data write, directly separated and mapped out the ODUk data, from the FIFO memory, read the ODUk data then equably and export from the TFI-5 bus.

Specifically describe preferential embodiment of the present invention below in conjunction with accompanying drawing, wherein, accompanying drawing constitutes the application's part, and is used from explaination principle of the present invention with embodiments of the invention one.For clear and simplification purpose, when it may make theme of the present invention smudgy, with specifying in detail of known function and structure in the omission device described herein.

6 pairs of described mapping devices of separating of the embodiment of the invention are elaborated at first in conjunction with the accompanying drawings.

As shown in Figure 6, Fig. 6 is the described structural representation of separating mapping device of the embodiment of the invention, specifically can comprise: control module, FIFO write data are selected module, are comprised the memory module of a plurality of FIFO memories, and the data selector of output; Wherein, described control module specifically comprises again: FIFO writes control unit, FIFO reads control unit and fifo address monitoring unit; Below each module and unit are elaborated respectively.

(1) control module, mainly be responsible for when the TFI-5 data arrive, control the byte that described memory module will be judged to be valid data and write in the described FIFO memory, and control described FIFO memory according to described memory module feedback data amount and read wherein stored valid data; Described control module specifically can comprise: FIFO writes control unit, FIFO reads control unit and fifo address monitoring unit.

1) FIFO writes control unit, main realizes that obtaining data from the TFI-5 bus is written to control procedure the FIFO memory.Be exactly specifically, when the TFI-5 data byte arrives, FIFO writes control unit and judges that the type of current byte is that (invalid data comprises: fixing byte of padding for ODUk valid data (D byte) or invalid data, adjust byte (R byte and J byte)), if valid data, then sending the FIFO write data selects signal to select module to the FIFO write data, and send corresponding FIFO write control signal respectively to each FIFO memory in the memory module, select module and memory module that these valid data are written in the FIFO memory by control FIFO write data; If R byte in the adjustment byte or fixing byte of padding then abandon these bytes, promptly do not control these bytes are written in the memory module; If the J byte in the adjustment byte then preserves the value of C position get off, so that follow-up the S byte is carried out majority vote; If negative justification opportunity byte, then judge that with the majority vote principle this negative justification opportunity byte is that information byte (embodiment of the invention is also thought valid data) is still adjusted byte according to CCCCC, if valid data, adopt in the same way control and write in the FIFO memory, then abandon if adjust byte.Described majority vote principle is if comprise 0 more than 3 or 3 in the CCCCC sequence, to judge that then the S byte is an information byte; If comprise 1 more than 3 or 3 in the CCCCC sequence, judge that then the S byte is for adjusting byte.

Here need to prove, because TFI-5 is capable 4320 bytes are arranged, preceding 160 bytes are overhead bytes, the 161st byte is a data byte to 4320 bytes, contain in the data byte ODUk valid data, fixedly byte of padding, adjust byte and negative justification opportunity byte, at first to start a counter according to the TFI-5 wardrobe signal row_fp of input so FIFO writes control unit, count TFI-5 data byte arrival behind 160 overhead bytes, begin to separate mapping again.C_4_17C and C_4_68C are to be the minimum period unit with 884 data blocks (size is the data block of 884 bytes), one 884 data block takies 208 row on the TFI-5 bus, fixedly the position of byte of padding, adjustment byte and ODUk data byte is determined in these 208 row.Therefore start the counter of one-period, go out according to the value sign of this counter which byte is to adjust byte on the present clock period TFI-5 bus, which is the ODUk data byte.Separate and shone upon after the delegation value of counter and determine, such as the cycle count that adopts 208, separate and shone upon after the delegation value of counter and should get back to 0, if be not 0, it is wrong then can to judge the TFI-5 bus data, should put 0 to the value of this counter, still can continue correctly to separate mapping at next line.

2) FIFO reads control unit, main being responsible for carried out data output according to the FIFO memory that described memory module feedback data amount is controlled in the described memory module, if the data of having stored predetermined quantity in the FIFO memory, reach half-full such as the FIFO memory, then FIFO reads control unit and begins to produce FIFO read control signal and ODUk read data and select signal.

3) fifo address monitoring unit is mainly used in the read-write state that monitors each FIFO memory.Be exactly that when FIFO memory generation read/write operation, memory module will be fed back the read-write absolute address` of each FIFO memory in real time to the fifo address monitoring unit specifically.Because each FIFO memory is write in order and is read in order, adjacent two FIFO memory reads or write addresses or equate, previous FIFO memory read or write the address than a back FIFO memory to read or write the address big by 1, (address of n FIFO all equates to have n FIFO memory that n address state just arranged, or k (k value from 2 to n-1) equal the address of the 1st to k FIFO to the address of n FIFO big by 1, be total to the n kind), therefore the fifo address monitoring unit can monitor in view of the above that the read-write state of each FIFO memory is whether in this n correct state range, if address state mistake, then send reset signal, so that the whole mapping device of separating is resetted, wait for that the arrival of next line signal restarts to separate mapping again.Adopt the monitoring of FIFO read/write address, added a heavy security mechanism, make to separate to shine upon certainly and can not make mistakes.

(2) the FIFO write data is selected module, and the main described FIFO of reception that is responsible for writes the FIFO write data selection signal that control unit is sent, and selects signal to choose the valid data that write described memory module from the TFI-5 bus according to this FIFO write data.Be exactly specifically, the FIFO write data is selected module to receive FIFO and is write the FIFO write data selection signal that control unit sends over, if this FIFO write data selects signal effective, then from 5 bytes of TFI-5 bus, choose the data that write of each FIFO memory.Because the memory module piece comprises n FIFO memory, therefore the FIFO write data selects the just corresponding n individual 5 that comprises of module to select 1 data selector, select respectively corresponding FIFO memory of data selector of 1 for one 5, so the FIFO write data among Fig. 6 selects signal should include the signal of n group 3bit, each 5 selects 1 data selector to choose data from 5 bytes of TFI-5 bus according to the value of this 3bit data bit, such as, when being 000, this 3bit value selects the 0th data byte, be to select the 1st data byte at 001 o'clock, ..., be to select the 4th data byte at 100 o'clock, then do not select during for other value.

(3) memory module is mainly used to data cachedly, generally includes the individual FIFO memory of n (n 〉=5), and the bit wide of FIFO memory is a byte wide.Be exactly that when the FIFO write control signal was effective, memory module was written in the corresponding FIFO memory according to writing the valid data byte that write control signal that control unit sends selects module to choose to the FIFO write data specifically; Each FIFO memory is to write data byte in order, for example, write sequence when n FIFO memory arranged is: the 1st valid data byte writes the 1st FIFO memory (FIFO#0), the 2nd valid data byte writes the 2nd FIFO memory (FIFO#1), ..., n valid data byte writes n FIFO memory (FIFO#n-1), and n+1 ODUk data byte writes the 1st FIFO memory, ..., other is by that analogy.

And, memory module is also wanted regular or real-time data volume with each FIFO memory stores how much to feed back to FIFO and is read control unit, FIFO reads control unit and whether produces the FIFO read control signal according to this data volume decision, so that control module control FIFO memory is read the wherein ODUk data of storage according to the FIFO read control signal.

Here, it should be noted that according to the output bit wide decision of system requirements to read what FIFO memories at every turn.TFI-5 separates mapping ODU1, if system requirements is exported 8 bit wides, then reads a FIFO memory at every turn, if system requirements is exported 16 bit wides, then reads 2 FIFO memories at every turn.TFI-5 separates mapping ODU2, if system requirements is exported 32 bit wides, then reads 4 FIFO memories at every turn, if system requirements is exported 64 bit wides, then reads 8 FIFO memories at every turn.Other output bit wide by that analogy.Evenly export the ODUk data according to certain ratio, but the ODUk data from the TFI-5 bus have the speed adjustment, FIFO reads control unit and monitors the data number of storing in the FIFO memory, when expiring soon, accelerates by the FIFO memory output, the output of slowing down when the FIFO memory is fast empty is overflowed to prevent the FIFO memory.

In addition, memory module also will feed back to the fifo address monitoring unit with the read-write absolute address` of each FIFO memory, so that the fifo address monitoring unit monitors whether the read-write state of each FIFO memory is correct, details are referring to top description to the fifo address monitoring unit.

(4) data selector of output, when the FIFO of memory module memory is read the ODUk data according to the FIFO read control signal, data selector is read the ODUk read data that control unit gives according to FIFO and is selected signal to select those as the data that FIFO memories of data output are read, and exports the ODUk data in these FIFO memories.Owing to include n FIFO memory in the memory module, so reading to control, ODU select signal with regard to corresponding n the bit data bit that include, each bit data bit is represented the selected state of the data that the FIFO memory corresponding with it read, such as, value on this bit data bit is that 1 expression is selected, if be that 0 expression is not selected.

Utilize the described mapping device of separating of the embodiment of the invention to separate the method for mapping and be elaborated below in conjunction with 7 pairs in accompanying drawing.

As shown in Figure 7, Fig. 7 is the schematic flow sheet of the described method of the embodiment of the invention.

Step 701: when the TFI-5 data byte arrives, FIFO writes the type that control unit is judged current byte, if valid data, then send the FIFO write data and select signal and corresponding FIFO write control signal, the byte that the control store module will be judged to be valid data is written in the FIFO memory, if adjust in the byte the R byte or fixedly byte of padding then abandon; If the J byte in the adjustment byte, then the value of C position is preserved so that follow-up the S byte is carried out the multidata judgement; If negative justification opportunity byte, also need further to judge that according to CCCCC majority vote principle this negative justification opportunity byte is information byte or adjustment byte, if valid data byte, then send the FIFO write data and select signal and corresponding FIFO write control signal, the byte that the control store module will be judged to be valid data is written in the FIFO memory, then abandons if adjust byte.

Step 702:FIFO write data is selected module to write the FIFO write data that control unit sends over according to FIFO to select signal to choose the valid data that write in the FIFO memory from the TFI-5 bus.

Step 703: when the FIFO write control signal is effective, the ODUk data that memory module selects the FIFO write data module to choose according to the write data control signal are written in the corresponding FIFO memory, and the data volume that memory module is also fed back in each FIFO memory is read control unit to FIFO.

Step 704:FIFO reads control unit and judges according to the next data volume of memory module feedback, if stored abundant data in the FIFO memory, reach half-full such as memory space, then FIFO reads control unit and begins to produce the FIFO read control signal, control FIFO memory output ODUk data.

Need get 5 data from the TFI-5 bus at most when separating mapping, so memory module comprises 5 FIFO memories, i.e. n 〉=5 at least.When FIFO memory number greater than 5 the time, what FIFO memories to depend on the output bit wide of system requirements, FIFO memory number n=output bit wide/FIFO bit wide with.For example TFI-5 separates mapping ODU1, and with the FIFO memory of 8 bit wides, exporting 8 or 16 bit data can be with 5 FIFO memory.And for example TFI-5 separates mapping ODU2, with the FIFO memory of 8 bit wides, and then need be with 8 FIFO memories if require to export 64 bit wides.

Step 705: memory module is read the ODUk data according to the FIFO read control signal.What FIFO memories output bit wide decision according to system requirements reads at every turn, and for example TFI-5 separates mapping ODU1, if system requirements is exported 8 bit wides, then reads a FIFO memory at every turn, if system requirements is exported 16 bit wides, then reads 2 FIFO memories at every turn.TFI-5 separates mapping ODU2, if system requirements is exported 32 bit wides, then reads 4 FIFO memories at every turn, if system requirements is exported 64 bit wides, then reads 8 FIFO memories at every turn.Other output bit wide by that analogy.FIFO reads control unit control store module and evenly exports the ODUk data according to certain ratio, but the ODUk data from the TFI-5 bus have the speed adjustment, FIFO reads control unit and monitors the data number of storing in the FIFO memory, when expiring soon, accelerates by the FIFO memory output, the output of slowing down when the FIFO memory is fast empty is overflowed to prevent FIFO.

Step 706: the data selector of output is read the ODU read data that control unit sends over according to FIFO and is selected signal to select corresponding FIFO memory to carry out data output.

Step 707: when FIFO memory generation read/write, memory module also will be fed back the read-write absolute address` of each FIFO memory in real time to the fifo address monitoring unit, the fifo address monitoring unit monitors that the read-write state of each FIFO memory is whether in n correct state range, if address state mistake, then send reset signal, the whole mapping device of separating that resets, waiting for that the next line signal arrives restarts to separate mapping again.Because as long as FIFO memory generation read/write will execution in step 707, so step 707 and be not limited to the execution sequence of above-mentioned steps.

In sum, the embodiment of the invention provides a kind of Optical Channel Data Unit-k of realizing to separate the device and method of mapping, simplify and understand mapping steps, two steps of separating mapping are combined realization, realize directly separating mapping out the ODUk data, make circuit structure more simple and reliable from the TFI-5 bus.And the embodiment of the invention adopts the monitoring of FIFO read/write address, has added a heavy security mechanism, makes to separate to shine upon certainly and can not make mistakes.

The above; only for the preferable embodiment of the present invention, but protection scope of the present invention is not limited thereto, and anyly is familiar with those skilled in the art in the technical scope that the present invention discloses; the variation that can expect easily or replacement all should be encompassed within protection scope of the present invention.Therefore, protection scope of the present invention should be as the criterion with the protection range of claims.

Claims (12)

1. realize that Optical Channel Data Unit-k separates the device of mapping for one kind, it is characterized in that, comprising: control module, and the memory module that to comprise a plurality of FIFO memories be pushup storage, wherein,

Described control module, when being used for the data byte arrival on the TFI-5 bus, control the byte that described memory module will be judged to be valid data and write in the described FIFO memory, and control described FIFO memory according to described memory module feedback data amount and read wherein stored valid data;

Described FIFO memory is used for buffer memory and writes valid data wherein or read wherein stored valid data;

Described memory module is used for described FIFO memory data quantity stored is fed back to described control module.

2. device according to claim 1 is characterized in that, described control module specifically comprises: FIFO writes control unit and FIFO reads control unit, wherein,

Described FIFO writes control unit, when being used for the data byte arrival on the TFI-5 bus, judge that current byte is valid data or invalid data, if valid data, send write data and select signal and corresponding write control signal, controlling described memory module is written to current byte in the described FIFO memory, if invalid data then abandons;

Described FIFO reads control unit, is used for judging according to described memory module feedback data amount, sends read data and select signal and read control signal when determining to read valid data, controls described FIFO memory and reads wherein stored valid data.

3. device according to claim 2, it is characterized in that, described FIFO writes control unit and specifically is used for, when the data byte on the TFI-5 bus arrives, judge the type of current byte, if valid data then send write data and select signal and corresponding write control signal, control described memory module current byte be written in the described FIFO memory, if adjust in the byte the R byte or fixedly byte of padding then abandon; If the J byte in the adjustment byte then preserves the value of C position get off; If negative justification opportunity byte, then further judge that according to the predetermined decision principle this negative justification opportunity byte is valid data byte or adjustment byte, if valid data byte, then send write data and select signal and corresponding write control signal, control described memory module current byte is written in the described FIFO memory, then abandon if adjust byte.

4. according to any described device in the claim 1 to 3, it is characterized in that described memory module also is used for, when described FIFO memory generation read/write, the read-write absolute address` of described FIFO memory is fed back to described control module in real time.

5. device according to claim 4, it is characterized in that, described control module also comprises: the fifo address monitoring unit, be used for read-write state that read-write absolute address` according to each FIFO memory of described fifo module feedback monitors each described FIFO memory whether in correct address state scope, and when address state makes a mistake, send reset signal.

6. according to claim 2 or 3 described devices, it is characterized in that, described device also comprises: the FIFO write data is selected module, be used to receive described FIFO and write the write data selection signal that control unit is sent, and select signal to choose the valid data that write described FIFO memory from the TFI-5 bus according to write data.

7. according to claim 2 or 3 described devices, it is characterized in that, described device also comprises: the data selector of output, be used to receive described FIFO and read the read data selection signal that control unit is sent, and export according to the data that described read data selects signal to select described FIFO memory to read.

8. realize that Optical Channel Data Unit-k separates the method for mapping for one kind, it is characterized in that utilize a kind of mapping device of separating, described method comprises:

Steps A: when the data byte on the TFI-5 bus arrived, control module was controlled the current byte that described memory module will be judged to be valid data and is write in the described FIFO memory;

Step B: after described FIFO memory write and buffer memory writes wherein valid data, described memory module fed back to described control module with the data volume of described FIFO memory stores;

Step C: described control module is controlled described FIFO memory according to described memory module feedback data amount and is read the data of storing in the described FIFO memory.

9. method according to claim 8 is characterized in that, described steps A specifically comprises:

When the TFI-5 data byte arrives, FIFO writes the type that control unit is judged current byte, if valid data, then judge and current byte to be written in the described memory module, and send write data and select signal and corresponding write control signal, if adjust in the byte the R byte or fixedly byte of padding then abandon; If the J byte in the adjustment byte then preserves the value of C position get off; If negative justification opportunity byte, then further judge that according to the predetermined decision principle this negative justification opportunity byte is valid data byte or adjustment byte, if valid data byte, then judge this byte is written in the described FIFO memory, and send write data selection signal and corresponding write control signal, then abandon if adjust byte.

10. method according to claim 8 is characterized in that, described step B specifically comprises:

The FIFO write data is selected module to write the write data that control unit sends according to described FIFO to select signal to choose the valid data that write described memory module from the TFI-5 bus;

The valid data that described memory module selects module to choose described FIFO write data according to described write control signal are written in each FIFO memory, and the data volume of described each FIFO memory stores is fed back to described control module.

11. method according to claim 8 is characterized in that, described step C specifically comprises:

Described FIFO reads control unit and controls described memory module output stored valid data according to described memory module feedback data amount, and is judging that sending read data when needing to export valid data selects signal and read control signal;

Described memory module is read the valid data of specifying in the FIFO memory according to the FIFO read data control signal that receives;

The data that described data selector selects signal to select described FIFO memory to read according to the read data that receives are exported.

12. any described method in 11 according to Claim 8 is characterized in that described method also comprises:

When described FIFO memory carried out read/write, described fifo module fed back the read-write absolute address` of each FIFO to the fifo address monitoring unit;

The read-write state that described fifo address monitoring unit monitors each FIFO according to the read-write absolute address` of described each FIFO and sends reset signal whether in correct address state scope when the address state mistake.

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