CN101930983A - Integrated circuit structure - Google Patents

Integrated circuit structure Download PDF

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Publication number
CN101930983A
CN101930983A CN2010102013525A CN201010201352A CN101930983A CN 101930983 A CN101930983 A CN 101930983A CN 2010102013525 A CN2010102013525 A CN 2010102013525A CN 201010201352 A CN201010201352 A CN 201010201352A CN 101930983 A CN101930983 A CN 101930983A
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Prior art keywords
emitter
bandgap grading
base bandgap
well region
base
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Inventor
陈家忠
陈硕懋
郭晋玮
刘莎莉
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Priority claimed from US12/715,071 external-priority patent/US8115280B2/en
Application filed by Taiwan Semiconductor Manufacturing Co TSMC Ltd filed Critical Taiwan Semiconductor Manufacturing Co TSMC Ltd
Priority to CN201510622440.5A priority Critical patent/CN105355594B/en
Publication of CN101930983A publication Critical patent/CN101930983A/en
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8222—Bipolar technology
    • H01L21/8224—Bipolar technology comprising a combination of vertical and lateral transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0207—Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/082—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including bipolar components only
    • H01L27/0821—Combination of lateral and vertical transistors only
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1203—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H01L29/0692—Surface layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/73—Bipolar junction transistors
    • H01L29/735—Lateral transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • General Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Bipolar Transistors (AREA)

Abstract

An integrated circuit structure is provided and includes a well region of a first conductivity type, an emitter of a second conductivity type opposite the first conductivity type over the well region, a collector of the second conductivity type over the well region and substantially encircling the emitter, and a base contact of the first conductivity type over the well region. The base contact is horizontally spaced apart from the emitter by the collector. At least one conductive strip horizontally spaces the emitter, the collector, and the base contact apart from each other. A dielectric layer is directly under, and contact with the at least one conductive strip. The invention has high RF frequency and high current gain, and results in reduction of flicker noise and process cost.

Description

Integrated circuit structure
Technical field
The present invention relates to a kind of semiconductor device, particularly use the structure and the manufacture method thereof of the horizontal vertical bipolar junction transistors (LVBJT) of CMOS transistor (CMOS) silicon-on-insulator (SOI) technology formation.
Background technology
Bipolar junction transistor (hereinafter to be referred as BJT) is the key component of analog integrated circuit.BJT can be divided into NPN BJT (hereinafter to be referred as NBJT) and PNP BJT types such as (hereinafter to be referred as PBJT).For the symbol of NPN BJT, it comprises collection utmost point C, base stage B and emitter-base bandgap grading E shown in Figure 1A.Utilize known CMOS transistor (hereinafter to be referred as CMOS) technology can form two kinds of BJT commonly used.Figure 1B and Fig. 1 C show a vertical BJT (vertical-BJT), and wherein Figure 1B shows vertical view, and Fig. 1 C shows profile.Above-mentioned vertical BJT is a NPN BJT who comprises doped region, and it is emitter-base bandgap grading E, base stage contact B and collection utmost point C.In order to increase emitter injection efficiency, emitter-base bandgap grading E by base stage contact B and collection utmost point C around.Emitter-base bandgap grading E contacts B and is formed among the P type trap PW with base stage, and collection utmost point C is formed among the N type trap NW, and wherein above-mentioned P type trap PW and N type trap NW further are formed among the dark N type trap DNW.Because the base region comprises that P type trap contacts B with base stage, emitter-base bandgap grading/base junction and the collection utmost point/base junction are formed between the vertically disposed element, so the BJT that forms can be considered a vertical BJT.
Fig. 1 D and Fig. 1 E show laterally BJT (lateral-BJT) of one (NPN).Fig. 1 D shows vertical view, and Fig. 1 E shows profile.Because P type trap PW is the part of base region, the part of P type trap PW is between emitter-base bandgap grading E and collection utmost point C, and emitter-base bandgap grading/base junction and the collection utmost point/base junction are formed between the element of horizontally set, so the BJT that forms can be considered a horizontal BJT (LBJT).
The improving gain ability of known vertical BJT and horizontal BJT is limited by following condition.With Fig. 1 E is example, except the BJT that attempt forms, also has parasitic transistor NBJT, and the collection utmost point, base stage and the emitter-base bandgap grading of above-mentioned parasitic transistor NBJT formed by emitter-base bandgap grading (zone) E, N type trap NW and dark N type trap DNW respectively.Because a pith of emitter-base bandgap grading/base junction of parasitic transistor NBJT is positioned at interface 2, above-mentioned interface 2 is positioned at the bottom of emitter-base bandgap grading E, and in order to reduce the influence of parasitic transistor NBJT, interface 2 preferably has little area.On the other hand, in order to improve the emitter injection efficiency of LBJT, the route optimization between emitter-base bandgap grading E and collection utmost point C that indicates as arrow 4 has big interfacial area (in the plane perpendicular to the accompanying drawing display plane).The length L (Fig. 1 D) of emitter-base bandgap grading E and collection utmost point C needs very large value.The very large length L of emitter-base bandgap grading E and little area are the demand of mutual contradiction, mean and improve the cost that LBJT can bring very large parasitic BJT.If LBJT utilizes the technology identical with forming cmos element to form, the predicament of known vertical BJT is the base width instability, and the aforementioned base width equals the degree of depth of the P type trap PW shown in Fig. 1 C substantially.
Summary of the invention
In view of this, embodiments of the invention provide a kind of integrated circuit structure, to solve the problem of known technology.
One embodiment of the invention provides a kind of integrated circuit structure, and the said integrated circuit structure comprises a well region, and it has one first conduction type.One emitter-base bandgap grading, it has one second conduction type in contrast to above-mentioned first conduction type, and above-mentioned emitter-base bandgap grading is positioned at above-mentioned well region top.The one collection utmost point, it has above-mentioned second conduction type, and the above-mentioned collection utmost point is positioned at above-mentioned well region top, and substantially around above-mentioned emitter-base bandgap grading.The contact of one base stage, it has above-mentioned first conduction type, and the aforementioned base contact is positioned at above-mentioned well region top.Aforementioned base contact with above-mentioned emitter-base bandgap grading and above-mentioned collection extremely level separate.At least one conduction bar, contacting each other with above-mentioned emitter-base bandgap grading, the above-mentioned collection utmost point with aforementioned base, level separates.One dielectric layer, be positioned at least one above-mentioned conduction bar under, and contact with at least one above-mentioned conduction bar.
Another embodiment of the present invention provides a kind of integrated circuit structure, comprising: the semiconductor substrate; Bury in this semiconductor substrate in one buried oxide district; And a bipolar junction transistor, comprising: a well region, it has one first conduction type, and this well region contacts with this buried oxide district; At least one emitter-base bandgap grading, it has one second conduction type in contrast to this first conduction type; At least one collection utmost point, it has this second conduction type; The contact of at least one base stage, it has this first conduction type, and wherein at least one described emitter-base bandgap grading, at least one described collection utmost point contact each other with at least one described base stage that level separates, and described emitter-base bandgap grading, the described collection utmost point and described base stage are arranged in this well region; And a plurality of conduction bars, be positioned at this well region top, and contact each other with at least one described base stage at least one described emitter-base bandgap grading, at least one described collection utmost point that level separates, wherein the described emitter-base bandgap grading of any one of this bipolar junction transistor separates by any one described base stage exposure level of at least one described collection utmost point and this bipolar junction transistor.
Further embodiment of this invention provides a kind of integrated circuit structure, comprising: the semiconductor substrate; Bury in this semiconductor substrate one mesozone in one buried oxide district; And a bipolar junction transistor, comprising: a well region, it has one first conduction type, and this well region contacts with this buried oxide district; One emitter-base bandgap grading, it has one second conduction type in contrast to this first conduction type, and this emitter-base bandgap grading contacts with this well region; A plurality of base stage contacts, it has this first conduction type, and wherein a plurality of described base stage contacts contact with this well region; A plurality of polysilicon strip things contact adjacent with each this emitter-base bandgap grading with a plurality of described base stages; And at least one collection utmost point, it has this second conduction type, and the described collection utmost point contacts with this well region, and a wherein described at least collection utmost point separates this emitter-base bandgap grading and each described base stage exposure level.
Other embodiment disclose as follows.
Except firing frequency frequency and high current gain, the isolation between LBJT and the substrate (for example p type substrate) also can cause the reduction of flicker noise (flicker noise).In addition, the technology of the embodiment of the invention can be fully and CMOS SOI process compatible, therefore can reduce the technology cost.
Description of drawings
Figure 1A shows the component symbol of a bipolar junction transistors.
Figure 1B and Fig. 1 C show the vertical view and the profile of the known vertical bipolar junction transistors of utilizing known CMOS transistor technology formation respectively.
Fig. 1 D and Fig. 1 E show the vertical view and the profile of the known lateral bipolar junction transistors of utilizing known CMOS transistor technology formation respectively.
Fig. 2 A to Fig. 2 D shows the vertical view of the bipolar junction transistor structure cell of the embodiment of the invention.
Fig. 3 to Fig. 4 shows the profile of the bipolar junction transistor structure cell of the embodiment of the invention.
Fig. 5 shows the testing element of the bipolar junction transistor structure cell be used to test the embodiment of the invention.
Wherein, description of reference numerals is as follows:
C～collection the utmost point;
B～base stage contact;
E～emitter-base bandgap grading;
PW～P type trap;
NW～N type trap;
DNW～dark N type trap;
L, LE～length;
WE～width;
WSE～width;
2～interface;
200～substrate;
20,201,202,203～conduction bar;
22～buried oxide;
24～dielectric layer;
PS～power supply;
GR～guard ring;
WR～trap ring;
T1, T2, T3, T4～end points.
Embodiment
Below describe and be accompanied by the example of description of drawings in detail with each embodiment, as reference frame of the present invention.And in the accompanying drawings, the shape of embodiment or thickness can enlarge, and to simplify or convenient the sign.Moreover, the part of each element will be to describe explanation respectively in the accompanying drawing, it should be noted that, not shown or describe element, be the form known to the those of ordinary skill in the affiliated technical field, in addition, only for disclosing the ad hoc fashion that the present invention uses, it is not in order to limit the present invention to certain embodiments.
The embodiment of the invention provides the horizontal-vertical bipolar junction transistors (LVBJTs) of a novelty, and it has the current gain of improvement.During specification is described different embodiment can be discussed.In accompanying drawing or specification description, similar or identical part is all used identical figure number.
Fig. 2 A shows the vertical view of NPN bipolar junction transistor (hereinafter to be referred as the NPN BJT) structure cell of one embodiment of the invention, and above-mentioned NPN bipolar junction transistor (NPN BJT) structure cell comprises collection utmost point C, base stage contact B and is positioned at the middle emitter-base bandgap grading E (also can be considered the summit) of NPN BJT structure cell.Fig. 2 B shows the NPN BJT structure cell of another embodiment of the present invention, and it comprises the emitter-base bandgap grading E pattern of more correcting one's mistakes.Emitter-base bandgap grading E is positioned at the summit of collection utmost point C.In order to improve the performance of BJT, emitter-base bandgap grading E area is preferably little, and the requirement that can reach little emitter-base bandgap grading E area by length L E and the width W E of reduction emitter-base bandgap grading E.Collection utmost point C can be adjacent to each side of each emitter-base bandgap grading E and emitter-base bandgap grading E.In one embodiment, not having one of them collection utmost point C under base stage contact B and emitter-base bandgap grading E situation between the two, there is not base stage contact B each side adjacent to emitter-base bandgap grading E.All collection utmost point C are connected to each other and as a single collection utmost point, and all base stages contact B is connected to each other and as a single base stage contact.Therefore, the NPN BJT structure cell shown in Fig. 2 A is as a single BJT.
The total length parametric representation of supposing emitter-base bandgap grading E is length L PE (figure does not show), and the ratio of the total length L PE of emitter-base bandgap grading E and area A E (figure does not show) can be expressed as parameter-area ratio (parameter-to-arearatio).In Fig. 2 A, the equal in length of 12 segment boundaries of length L PE and emitter-base bandgap grading E.Can find that parameter-area ratio is of value to the performance of final BJT.In addition, when small size was of value to influencing of the undesired parasitic BJT of reduction, high LPE value is of value to improved emitter injection efficiency.Because high parameter-area ratio, because all sides of emitter-base bandgap grading E is adjacent to collecting utmost point C, the path between emitter-base bandgap grading E and the collection utmost point C broadens relatively, therefore improves the performance of final BJT.Shown in Fig. 2 A, in order to increase parameter-area ratio, can adopt criss-cross emitter-base bandgap grading E, it has high parameter-area ratio, yet also can use other shapes with high parameter-area ratio as emitter-base bandgap grading E.For instance, emitter-base bandgap grading E can comprise a plurality of interconnected narrow bars.The width of each narrow bar (for example width W SE among Fig. 2 A) can near or equal the minimum widith that integrated circuit technology allows, perhaps, in other words, approach critical size.In other embodiments, the shape of emitter-base bandgap grading E can be polygonal, for example triangle, rectangle (shown in Fig. 2 B) or hexagon.
Emitter-base bandgap grading E to collection utmost point C, emitter-base bandgap grading E to base stage contact B contact with base stage B to all knots of collection utmost point C be by form conduction bar 20 (it can be formed by polysilicon, and therefore can be considered afterwards polysilicon strip thing) each other level separate (when looking) from vertical view.In other embodiments, can form conduction bar 20 by other electric conducting materials of for example metal.Please refer to Fig. 2 A and Fig. 2 B, form conduction bar 20 (comprising conduction bar 20_1,20_2 and 20_3) with each emitter-base bandgap grading E, collection utmost point C are contacted with base stage B each other level separate.In addition, the horizontal range between emitter-base bandgap grading E and the base stage contact B can be greater than the width (for example LG does not show) of conduction bar 20.In other words, each base stage contact B can be spaced laterally apart by at least one conduction bar 20 (can be two or more) and at least one collection utmost point C and emitter-base bandgap grading E.
Fig. 3 is the profile of the BJT shown in Fig. 2 B, and it is along the profile of tangent line 3-3 among Fig. 2 B.From above-mentioned profile as can be known, emitter-base bandgap grading E, the collection utmost point C contacts B and are formed among the P type trap PW and with P type trap PW and contact with base stage, emitter-base bandgap grading E, collect utmost point C and contact B with base stage and also be arranged in a buried oxide (BOX) 22.Buried oxide (BOX) 22 can further be positioned on the substrate 200 that the semi-conducting material by for example silicon forms.Aforesaid substrate 200 can be the p type, yet aforesaid substrate 200 also can be the n type.In specification, though the base region comprises base stage contact B and its P type well region down, base stage contacts B and can be equal to and be considered as base stage B.
In addition, conduction bar 20 can be positioned on the dielectric layer 24, and emitter-base bandgap grading E, collection utmost point C are contacted B with base stage and be spaced laterally apart each other.Therefore, emitter-base bandgap grading E, conduction bar 20_1 (it is as a grid) and around collection utmost point C can form as shown in Figure 3 a metal oxide semiconductor transistor (MOS) element.Can conductive doped bar 20, and can on conduction bar 20, apply a bias voltage, to reduce the electric leakage of final BJT.In one embodiment, power supply (bias generator) PS is connected to conduction bar 20_1 to apply bias voltage.Above-mentioned bias voltage can be back bias voltage, for example be about-0.25V, yet power ps also can apply different bias voltages.
In other embodiments, resistance protection oxidation bar (RPO strips) be can form and conduction bar 20 and buried oxide (BOX) 22 replaced forming.Though resistance protection oxidation bar can not be used for applying bias voltage, can be used to isolate follow-uply contact the silicide that B goes up formation with base stage in emitter-base bandgap grading E, collection utmost point C, contact with each other avoiding.
As shown in Figure 3, above-mentioned BJT can also comprise guard ring GR, and above-mentioned guard ring GR can be formed by the separator with shallow grooves (STI) around P type trap.In addition, for N type BJT, can form a n type trap ring WR (also with reference to figure 2), said n type trap ring is the ring around guard ring GR.In one embodiment, when BJT in use, can not apply any being biased on the trap ring WR.
Can utilize CMOS transistor (hereinafter to be referred as CMOS) technology to form the BJT of the embodiment of the invention, comprise and N+ district, P+ district, P type trap PW district and N type well region (for example trap ring WR), and with for example form simultaneously for the cmos element of logic element.Therefore, can utilize the ion injection mode to form above-mentioned N+ district, P+ district, P type trap PW district and N type well region.In addition, can utilize in a depth desired of substrate 200 and inject oxygen, in an oxygen-free environment, carry out annealing process again, so that the silicon of oxygen that injects and vicinity forms the mode of silica, to form buried oxide (BOX) 22.In other embodiments, can use silicon-on-insulator (SOI) substrate.The technology of BJT can be compatible fully with CMOS technology.
Fig. 4 shows the profile of PNP lateral bipolar junction transistors (hereinafter to be referred as PNP LBJT), except emitter-base bandgap grading E, collection utmost point C contact the conduction type of B and inverted configuration shown in Figure 3 with base stage, and outside the conduction type of well region and the inverted configuration shown in Figure 3, other are similar to structure shown in Figure 3.The vertical view of above-mentioned PNP LBJT is also identical with Fig. 2 A to Fig. 2 D in fact.In addition, form buried oxide (BOX) 22 so that PNP LBJT and the substrate under it 200 are isolated, aforesaid substrate 200 can be p type or n type.In order to reduce electric leakage, power supply (bias generator) PS can apply a positive bias to conduction bar 20_1.
Fig. 2 C to Fig. 2 D is various embodiments of the invention.What note is that LBJT can comprise a plurality of emitter-base bandgap gradings that are isolated from each other by conduction bar 20 and collection utmost point C.For instance, in Fig. 2 C, form two interconnected emitter-base bandgap grading E, with as a single emitter-base bandgap grading.Can increase more emitter-base bandgap grading E, and can be arranged as and for example be the one-period property pattern of an array.Except Fig. 2 D had only a conduction bar 203, Fig. 2 D was similar to Fig. 2 A.In addition, in these embodiments, all edges of emitter-base bandgap grading E conducted electricity bar 20 around, and all edges of emitter-base bandgap grading E are adjacent to collection utmost point C.Do not collecting utmost point C under the situation between base stage contact B and the emitter-base bandgap grading E, not having base stage to contact B can be adjacent to the edge of any emitter-base bandgap grading E.Scrutablely be, though for the purpose of layout is convenient, above-mentioned emitter-base bandgap grading E, collection utmost point C contact the shape that B has rule with base stage, but above-mentioned emitter-base bandgap grading E, collection utmost point C contact B and can have irregular shape with base stage, and above-mentioned irregular not isometric side, the arc-shaped side edges etc. of comprising.
Fig. 5 shows a test structure, and wherein the embodiment of the BJT of test demonstration is LBJT (extremely shown in Figure 4 as Fig. 2 A).LBJT need test four end points, comprises end points T1, T2, T3 and T4, and above-mentioned end points T1, T2, T3 and T4 are connected to trap ring WR respectively, base stage contacts B, conduction bar 20_2 and emitter-base bandgap grading E (Fig. 5 does not show, please refer to Fig. 2 A to Fig. 4).Measure base stage contact B and N type trap ring WR (Fig. 3) radio-frequency responsive with the LBJT that obtains testing, base stage contact B and N type trap ring WR are respectively as RF the 1st port and RF the 2nd port (figure shows).Experimental result shows respectively reduces to 1 at the frequency Ft (cut-off frequency) and the Fmax (maximum concussion frequency) of H21 gain and unidirectional power gain, and its value is for high.In addition, the LBJT structure cell of the embodiment of the invention has high current gain.Its reason may be buried oxide (BOX) 22 isolated substrates and its down due to the well region, and the parasitic BJT that above-mentioned buried oxide (BOX) 22 can cause substrate to produce disappears.
It should be noted that, though use LVBJT in the foregoing embodiments as embodiment, but adopt the CMOS SOI technology of example buried oxide (BOX) 22 as shown in Figure 3 and Figure 4 also can be used in other elements, the passive component of the active element of radio frequency (RF) element, for example RFMOS, for example inductance, variable capacitance (varactor), filter, antenna or similar elements for example, with the loss of reduction substrate, and can reduce the endophyte RLC resistance-inductance-capacitance (RLC) that radio frequency (RF) is used.
Scrutable is that except firing frequency frequency and high current gain, the isolation between LBJT and the substrate (for example p type substrate) also can cause the reduction of flicker noise (flicker noise).In addition, the technology of the embodiment of the invention can be fully and CMOS SOI process compatible, therefore can reduce the technology cost.
Though the present invention with embodiment openly as above; right its is not in order to limit the present invention; any those of ordinary skills; without departing from the spirit and scope of the present invention; when can doing a little change and retouching, so protection scope of the present invention is as the criterion when looking the protection range that claim defined of enclosing.

Claims (12)

1. integrated circuit structure comprises:
One well region, it has one first conduction type;
One emitter-base bandgap grading, it has one second conduction type in contrast to this first conduction type, and this emitter-base bandgap grading is positioned at this well region top;
The one collection utmost point, it has this second conduction type, and this collection utmost point is positioned at this well region top, and substantially around this emitter-base bandgap grading;
One base stage contact, it has this first conduction type, and this base stage contact is positioned at this well region top, and wherein this base stage contact collects this emitter-base bandgap grading and this extremely that level separates;
At least one conduction bar, contacting each other with this base stage this emitter-base bandgap grading, this collection utmost point, level separates; And
One dielectric layer, be positioned at least one described conduction bar under, and contact with at least one described conduction bar.
2. integrated circuit structure as claimed in claim 1 also comprises:
One buried oxide district, be positioned at this well region under; And
The semiconductor substrate, be positioned at this buried oxide district under.
3. integrated circuit structure as claimed in claim 1, also comprise a plurality of extra base stage contacts, it has this first conduction type, wherein each described extra base stage contact separates with this emitter-base bandgap grading level by at least one described collection utmost point and at least one described conduction bar, and wherein a plurality of described base stage contacts and is electrically connected to each other and in fact separates each other.
4. integrated circuit structure as claimed in claim 1, also comprise at least one extra emitter-base bandgap grading, it has this second conduction type, this extra emitter-base bandgap grading is positioned at this well region top, wherein each at least one described extra emitter-base bandgap grading collects extremely by at least two described conduction bars and this emitter-base bandgap grading and this that level separates, and wherein at least one described extra emitter-base bandgap grading is electrically connected to this emitter-base bandgap grading.
5. integrated circuit structure as claimed in claim 1 also comprises an extra well region, and it forms the annulation around this well region, and this extra well region has this second conduction type.
6. integrated circuit structure comprises:
The semiconductor substrate;
Bury in this semiconductor substrate in one buried oxide district; And
One bipolar junction transistors comprises:
One well region, it has one first conduction type, and this well region contacts with this buried oxide district;
At least one emitter-base bandgap grading, it has one second conduction type in contrast to this first conduction type;
At least one collection utmost point, it has this second conduction type;
The contact of at least one base stage, it has this first conduction type, and wherein at least one described emitter-base bandgap grading, at least one described collection utmost point contact each other with at least one described base stage that level separates, and described emitter-base bandgap grading, the described collection utmost point and described base stage are arranged in this well region; And
A plurality of conduction bars, be positioned at this well region top, and contact each other with at least one described base stage at least one described emitter-base bandgap grading, at least one described collection utmost point that level separates, wherein the described emitter-base bandgap grading of any one of this bipolar junction transistor separates by any one described base stage exposure level of at least one described collection utmost point and this bipolar junction transistor.
7. integrated circuit structure as claimed in claim 6, wherein in a vertical view, each described emitter-base bandgap grading by an annulation fully flatly around, and this annulation is formed by a plurality of described conduction bars.
8. integrated circuit structure as claimed in claim 7, wherein this first conduction type is the p type, and wherein this integrated circuit structure also comprises a bias generator, and electric property coupling arrives a plurality of described conduction bars, and this bias generator wherein is installed so that a back bias voltage to be provided.
9. integrated circuit structure as claimed in claim 7, wherein this first conduction type is the n type, and wherein this integrated circuit structure also comprises a bias generator, and electric property coupling arrives a plurality of described conduction bars, and this bias generator wherein is installed so that a positive bias to be provided.
10. integrated circuit structure comprises:
The semiconductor substrate;
Bury in this semiconductor substrate one mesozone in one buried oxide district; And
One bipolar junction transistors comprises:
One well region, it has one first conduction type, and this well region contacts with this buried oxide district;
One emitter-base bandgap grading, it has one second conduction type in contrast to this first conduction type, and this emitter-base bandgap grading contacts with this well region;
A plurality of base stage contacts, it has this first conduction type, and wherein a plurality of described base stage contacts contact with this well region;
A plurality of polysilicon strip things contact adjacent with each this emitter-base bandgap grading with a plurality of described base stages; And
At least one collection utmost point, it has this second conduction type, and the described collection utmost point contacts with this well region, and wherein at least one described collection utmost point separates this emitter-base bandgap grading and each described base stage exposure level.
11. integrated circuit structure as claimed in claim 10, wherein this emitter-base bandgap grading is positioned on the summit of at least one described collection utmost point.
12. integrated circuit structure as claimed in claim 10, also comprise at least one extra emitter-base bandgap grading, it contacts with this well region, wherein said extra emitter-base bandgap grading is electrically connected to this emitter-base bandgap grading, and in fact wherein said extra emitter-base bandgap grading separates by at least one described polysilicon strip thing and at least one described collection utmost point and this emitter-base bandgap grading.
CN2010102013525A 2009-06-17 2010-06-09 Integrated circuit structure Pending CN101930983A (en)

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