CN101930948B - Method for producing nitride read-only memory - Google Patents

Abstract

The invention discloses a method for producing a nitride read-only memory, which comprises the following steps of: providing a substrate with an isolating structure, wherein the isolating structure is used for isolating adjacent memory unit regions; depositing a dielectric layer on the substrate; forming a well region in a region under the surface of the substrate corresponding to the memory unit regions by ion implantation and forming a bit line in the well region; depositing a polysilicon layer on the dielectric layer and forming a grid electrode array in a region on the surface of the substrate corresponding to the memory unit regions by etching the polysilicon layer and the dielectric layer; forming side walls on the side edges of all grid electrodes of the grid electrode array and mutually connecting the side walls of adjacent grid electrodes; and carrying out ion implantation with an inclined angle on the well region part near the isolating structure. By self-alignment penetration preventing implantation, the manufacture method can save the film masking process, reduce the cost, solve the problem of misalignment with a front-layer mask film caused by film masking and prevent an asymmetrical implantation phenomenon.

Description

The manufacturing approach of nitride ROM

Technical field

The present invention relates to field of semiconductor manufacture, particularly a kind of manufacturing approach of nitride ROM.

Background technology

Along with the continuous development of semiconductor technology, the precision of production process of semiconductor device is also improving constantly.The precision of semiconductor integrated circuit has reached the deep-submicron size now, and this makes the integrated level of semiconductor device and the complexity of manufacturing process also increase greatly in the past.

Shown in Figure 1 is the part planar structure sketch map of a kind of silicon nitride ROM (NROM nitride read only memory).As shown in the figure, this NROM comprises a plurality of memory cell areas (cell area) 100.In each memory cell areas 100, constitute memory cell array by mutually orthogonal word line WL (Word Line) 110 and bit line BL (BitLine) 120.Isolate through fleet plough groove isolation structure (STI) 130 between the adjacent memory unit regions 100.Usually, bit line BL 120 is embedded among the Semiconductor substrate through ion implantation technology; 110 of word line WL are the grid arrays that forms through grid technology; STI 130 forms through processing steps such as fluting, filling, grindings, and the filler that is wherein adopted is an insulating material, can be oxide, for example silica.

Please combine the E referring to Fig. 2 A to Fig. 2, it is depicted as the cross section structure sketch map of making each step of method of silicon nitride ROM in the prior art, may further comprise the steps:

At first, shown in Fig. 2 A, Semiconductor substrate 10 is provided, it comprises memory cell areas 100 and the fleet plough groove isolation structure 130 that is used to isolate consecutive storage unit district 100, and on Semiconductor substrate 10, forms ONO (silica-silicon-nitride and silicon oxide) layer 140.

Then, shown in Fig. 2 B, 100 carry out the ion injection in the storage element district; The general boron ion that injects forms well region 160, then in Semiconductor substrate 10, forms a plurality of impurity diffusion zones through the ion injection; And impurity diffusion zone carried out the speedup oxidation, thereby form multiple bit lines BL 120; Certainly carrying out utilizing mask definition ion implanted region before ion injects, the speedup oxidation can utilize the heat treatment of uniform temperature and time to realize, these all are technology well-known to those skilled in the art, repeat no more at this.Accomplished the making of bit line BL120, just can further carry out the making that grid structure is word line WL 110, concrete forming process is following:

Like Fig. 2 C; On ONO (silica-silicon-nitride and silicon oxide) layer 140, pass through silica, silicon nitride etch; Remove the ONO layer on STI 130 surfaces, and the ONO layer 140 in reserved storage location district 100 is as the gate dielectric layer of memory cell areas 100, and on ONO layer 140, forms polysilicon layer; Utilize mask to carry out etching again, on memory cell areas 100, form grid array 110.

Because raising along with craft precision; The NROM integrated level constantly promotes; Live width is constantly dwindled, and makes that the amounts of dopant ions in the well region 160 also decreases, especially in silicon nitride ROM; The boron ion that mixes in the well region 160 adjacent with STI 130 is dissolved in the filler of STI 130 easily---in the oxide; And oxide absorbs, and the concentration that this will reduce doped with boron ion in the well region 160 of memory cell areas 100 makes memory cell (transistor) in the memory cell areas 100 that break-through (punchthrough) problem of source electrode and drain electrode takes place easily.

In order to prevent transistor generation source electrode and break-through (punchthrough) problem of drain electrode in the memory cell areas 100; Like Fig. 2 D; Form mask 170 as the barrier layer on memory cell areas 100 surfaces in the prior art, cover on the grid array 110 of memory cell areas 100, expose the marginal portion that memory cell areas 100 is close in fleet plough groove isolation structure STI 130; And it is carried out anti-penetration inject (APTimplantation; Anti-Punch Through implantation), to partly injecting the boron ion, to increase the concentration of boron ion with STI 130 adjacent well regions.

Then, shown in Fig. 2 E, remove mask 170, memory cell areas 100 is carried out chemical vapour deposition (CVD) and etching formation grid curb wall 190, be used to isolate the adjacent transistors grid.

By on can know; During the dopant ion boron ion of prior art in complement, need to increase one deck mask and define the zone that ion injects, because the manufacturing expense of mask operation complex process and mask is very high; Can bring with the anterior layer misalignment simultaneously and asymmetric problem occur injecting; Therefore, this has just improved manufacturing cost and time greatly, reduces production efficiency.

Summary of the invention

The present invention is intended to solve in the prior art, and when memory cell transistor was prevented the break-through performance at additional dopant ion injection enhancing nitride ROM edge, it was asymmetric to occur the ion injection easily, and operating procedure is complicated, and is with high costs, technical problems such as inefficiency.

In view of this, the present invention provides a kind of manufacturing approach of nitride ROM, comprising:

Provide one be formed with isolation structure substrate, said isolation structure is used for isolating adjacent memory unit regions;

Dielectric layer on said substrate;

Be infused in the zone formation well region of substrate surface below through ion, and in said well region, form bit line corresponding to memory cell areas;

Deposit spathic silicon layer on said dielectric layer is through etch polysilicon layer and dielectric layer, at the zone formation grid array of substrate surface corresponding to memory cell areas;

On the sidewall of each grid of said grid array, form side wall, the side wall of neighboring gates interconnects;

With the angle of inclination well region adjacent to said isolation structure partly being carried out ion injects.

Further, said isolation structure is a fleet plough groove isolation structure.

Further, the injection ion of said well region is the boron ion.

Further, said dielectric layer comprises folded successively silicon oxide layer, silicon nitride layer and the silicon oxide layer of establishing.

Further, said side wall is the three range upon range of side walls that add structure, comprises folded successively silicon oxide layer, silicon nitride layer and the silicon oxide layer of establishing.

Further, said partly to carry out direction that ion injects and vertical direction angle be 20 degree spends to 30 to the well region adjacent to said isolation structure, and the injection energy is 20keV to 25keV.

Further, the width of said grid is 50 to 100nm.

Further, the width of said side wall is 80 to 150nm.

The manufacturing approach of nitride ROM provided by the invention; Adjust to after side wall forms through the dopant ion implantation step that will strengthen anti-break-through,, can block the dopant ion of injection because the mid portion of storage area is all filled up by side wall medium (silicon oxide/silicon nitride/silicon oxide); And do not need to do in addition one mask layer; Can reduce the use of one deck mask thus, reduce expense and time greatly, can avoid the mask problems of missing aim simultaneously.In addition, for energy and the angle that dopant ion injects, only need on the basis of original injection condition, to adjust slightly to get final product, it is workable, and it is convenient to implement.Therefore, manufacturing approach provided by the invention can strengthen and inject stability when playing the anti-break-through effect of transistor, simplifies technological process, practices thrift manufacturing cost, enhances productivity.

Description of drawings

Shown in Figure 1 is a kind of part planar structure sketch map of silicon nitride ROM;

Fig. 2 A to Fig. 2 E is depicted as the cross section structure sketch map of making each step of method of silicon nitride ROM in the prior art;

The manufacturing approach flow chart of the silicon nitride ROM that provides for one embodiment of the invention shown in Figure 3;

Fig. 4 A to Fig. 4 E is depicted as the cross section structure sketch map that one embodiment of the invention is made each step of method of silicon nitride ROM.

Embodiment

For making the object of the invention, characteristic more obviously understandable, provide preferred embodiment and combine accompanying drawing, the present invention is described further.

See also Fig. 3, it is depicted as the manufacturing approach flow chart of the silicon nitride ROM that one embodiment of the invention provides.

This manufacturing approach may further comprise the steps:

S310: provide one be formed with isolation structure Semiconductor substrate, said isolation structure is used for isolating adjacent memory unit regions;

S320: dielectric layer on said substrate;

S330: be infused in the zone formation well region of said substrate surface below through ion, and in said well region, form bit line corresponding to memory cell areas;

S340: deposit spathic silicon layer on said dielectric layer, through etch polysilicon layer and dielectric layer, at the zone formation grid array of substrate surface corresponding to memory cell areas;

S350: on the sidewall of each grid of said grid array, form side wall, and the side wall of neighboring gates interconnects;

S360: with the angle of inclination well region adjacent to said isolation structure is partly carried out ion and inject.

In order more clearly to explain the present invention, please combine Fig. 4 A to Fig. 4 E.

At first; Shown in Fig. 4 A; Semiconductor substrate 20 is provided, and it comprises memory cell areas 200 and the fleet plough groove isolation structure STI 230 that is used to isolate consecutive storage unit district 200, then on Semiconductor substrate 20, forms dielectric layer; In present embodiment, said dielectric layer is ONO (silica-silicon-nitride and silicon oxide) layer 240.

Then; Shown in Fig. 4 B, 200 carry out the ion injection in the storage element district, generally inject the boron ion; Form well region 260; Then in the well region 260 of Semiconductor substrate 20, inject a plurality of impurity diffusion zones of formation, and impurity diffusion zone is carried out the speedup oxidation, thereby form multiple bit lines BL 220 through ion; Certainly carrying out utilizing mask definition ion implanted region before ion injects, the speedup oxidation can utilize the heat treatment of uniform temperature and time to realize, these all are technology well-known to those skilled in the art, repeat no more at this.Accomplished the making of bit line BL 220, just can further carry out the making that grid structure is word line WL 210, concrete forming process is following:

Like Fig. 4 C; On ONO (silica-silicon-nitride and silicon oxide) layer 240, pass through silica, silicon nitride etch; Remove the ONO layer of STI 230 tops; And the ONO layer 240 in reserved storage location district 200 is the gate dielectric layer of memory cell areas 200, and on ONO layer 240, forms polysilicon layer, and on memory cell areas 200, forms grid array 210 through etching.

In the present embodiment, the width of the grid of grid array 210 is 50 to 100nm.

Then, shown in Fig. 4 D, memory cell areas 200 is carried out chemical vapour deposition (CVD) and etching formation grid curb wall 290, be used to isolate the adjacent transistors grid.In the present embodiment, said side wall 290 is the three range upon range of side walls that add structure, comprises successively folded silicon oxide layer, silicon nitride layer and the silicon oxide layer of establishing, and side wall 290 width are 80 to 150nm.

Then; Like Fig. 4 E, in order to prevent transistor generation source electrode and break-through (punch through) phenomenon of drain electrode in the storage unit district 200, with side wall 290 as the barrier layer; Be used to cover the grid array 210 on the memory cell areas 200; And partly carry out anti-penetration with the angle that tilts to the well region adjacent to fleet plough groove isolation structure STI 230 and inject (APT implantation, Anti-Punch Through implantation), well region 260 is injected the boron ion.

In the present embodiment; For the accuracy that guarantees to inject; Direction that said dopant ion tilts to inject and vertical direction angle 20 degree are to 30 degree, and the injection energy is 20keV to 25keV, injects from the both direction symmetry respectively; Can reach accurate requirement and quantitative requirement simultaneously, and no longer need mask to define the zone that ion injects.

In sum; The manufacturing approach that the embodiment of the invention provides is adjusted to after the side wall formation through the dopant ion implantation step that will strengthen anti-break-through, because the mid portion of memory cell areas is all filled up by side wall medium (silicon oxide/silicon nitride/silicon oxide), can block the dopant ion of injection; And do not need to do in addition one mask layer; Can reduce the use of one deck mask, reduce expense and time greatly, can avoid the mask problems of missing aim simultaneously.In addition, new injection condition only need change energy and the angle that dopant ion injects, and can remedy the concentration of dopant ion in the trap.Therefore, manufacturing approach provided by the invention has increased and has injected stability under the prerequisite that strengthens the anti-break-through performance of transistor, has simplified technological process, has practiced thrift manufacturing cost, has improved production efficiency.

Though the present invention discloses as above with preferred embodiment; Right its is not in order to limit the present invention; Has common knowledge the knowledgeable in the technical field under any; Do not breaking away from the spirit and scope of the present invention, when can doing a little change and retouching, so protection scope of the present invention is as the criterion when looking claims person of defining.

Claims (7)

1. the manufacturing approach of a nitride ROM comprises:

Provide one be formed with isolation structure substrate, said isolation structure is used for isolating adjacent memory unit regions;

Dielectric layer on said substrate;

Be infused in the zone formation well region of substrate surface below through ion, and in said well region, form bit line corresponding to memory cell areas;

Deposit spathic silicon layer on said dielectric layer is through etch polysilicon layer and dielectric layer, at the zone formation grid array of substrate surface corresponding to memory cell areas;

On the sidewall of each grid of said grid array, form side wall, the side wall of neighboring gates interconnects;

With the angle of inclination well region adjacent to said isolation structure is partly carried out ion and inject, said partly to carry out direction that ion injects and vertical direction angle be 20 degree spends to 30 to the well region adjacent to said isolation structure, and the injection energy is 20keV to 25keV.

2. manufacturing approach according to claim 1 is characterized in that, said isolation structure is a fleet plough groove isolation structure.

3. manufacturing approach according to claim 1 is characterized in that, the injection ion of said well region is the boron ion.

4. manufacturing approach according to claim 1 is characterized in that, said dielectric layer comprises folded successively silicon oxide layer, silicon nitride layer and the silicon oxide layer of establishing.

5. manufacturing approach according to claim 1 is characterized in that, said side wall is the three range upon range of side walls that add structure, comprises folded successively silicon oxide layer, silicon nitride layer and the silicon oxide layer of establishing.

6. manufacturing approach according to claim 1 is characterized in that, the width of said grid is 50 to 100nm.

7. manufacturing approach according to claim 1 is characterized in that, the width of said side wall is 80 to 150nm.

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