CN101930712A - Shift unit, shift device and liquid crystal display - Google Patents
Shift unit, shift device and liquid crystal display Download PDFInfo
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- CN101930712A CN101930712A CN2009100535373A CN200910053537A CN101930712A CN 101930712 A CN101930712 A CN 101930712A CN 2009100535373 A CN2009100535373 A CN 2009100535373A CN 200910053537 A CN200910053537 A CN 200910053537A CN 101930712 A CN101930712 A CN 101930712A
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Abstract
The invention relates to a shift unit, a shift device and a liquid crystal display. The shift unit comprises a first control unit, a second control unit, a gate driving signal generating unit and a capacitance control signal generating unit, wherein the first control unit is used for receiving a clock signal and an input control signal and generating an intermediate control signal; the second control unit is used for receiving the intermediate control signal generated by the first control unit and generating an output control signal; the gate driving signal generating unit is used for receiving the clock signal and the output control signal generated by the second control unit and generating a gate driving signal; and the capacitance control signal generating unit is used for receiving a capacitance control input signal and the intermediate control signal generated by the first control unit and generating a capacitance control signal. A circuit structure is simplified to contribute to territory layout and circuit driving.
Description
Technical field
The present invention relates to field of liquid crystal display, particularly the LCD of shift unit, shift unit and this shift unit of application.
Background technology
In LCD (LCD), perhaps at structure other flat-panel monitors similarly such as e-book, Organic Light Emitting Diode flexible display etc., gate metal line is a lateral arrangement as the row drive wire in the liquid crystal pixel array layout.Link to each other with drive integrated circult (IC) pin of chip but the wiring of the periphery outside display interior pixel viewing area zone, the gate metal line of these lateral arrangement need to arrange in a certain direction concurrently, obtain display drive signals.Common LCD all has the pixel of hundreds of row even thousands of row, therefore also just there is the very considerable gate metal line of quantity in periphery wiring zone, under amorphous silicon device manufacturing condition now, every gate metal line width with and and adjacent grid line between necessary be 10 μ m apart from sum, therefore these parallel grid lines of arranging will occupy very large area in the periphery zone of connecting up, but have a strong impact on the miniaturization and the integration of display device thus.
Amorphous silicon gate could drives (ASG, Amorphous Silicon Gate) technology has solved the problems referred to above, it utilizes at the other circuit structure that produces the grid drive signal of making separately of each row pixel, broken away from dependence, also just saved at the connect up parallel grid line of arranging of regional One's name is legion of periphery to drive IC.The circuit structure of the independent generation grid drive signal that each row pixel is other is called the ASG unit, common ASG unit has the structure of a shift register, the ASG driving circuit of an integral body is the repetition of ASG unit at all row, or the interlacing of parity rows ASG unit repeats.The on-off element (for example thin film transistor (TFT) TFT) of the pixel cell in grid drive signal and the liquid crystal pixel array is connected, and controls the conducting and the disconnection of described on-off element.
Each pixel cell in the liquid crystal pixel array comprise pixel electrode, storage electrode and public electrode and be filled in pixel electrode and public electrode between liquid crystal molecule.When the on-off element conducting of pixel cell, the pixel voltage that carries data-signal is applied on the corresponding pixel electrode, voltage on pixel voltage on the pixel electrode and the public electrode corresponding with it forms voltage difference, the liquid crystal molecule that is held on is therebetween deflected, different liquid crystal deflecting element degree has two different tropism's optical path differences, by with backlight, the cooperation of devices such as polaroid can produce different light intensity, by line by line or the on-off element of the pixel cell in the described liquid crystal pixel array of interlacing gating, can be so that different pixel cells sees through different light intensity.Line by line or behind the staggered scanning gating, the light intensity that whole liquid crystal pixel array sees through is a two field picture.
After the on-off element of pixel cell disconnects, form series relationship between the pixel capacitance that memory capacitance that storage electrode, public electrode constitute and pixel electrode, public electrode constitute, if this moment is the current potential on the change memory capacitance, then the voltage of pixel capacitance two interpolars also has the change value of a correspondence, this is called capacitive coupling (CC, Coupled Capacity) mechanism, the voltage change value of pixel capacitance two interpolars is: Δ V
P2=C
St* Δ V
Cst/ (C
St+ C
Lc+ C
Gd)
Wherein, Δ V
CstBe the voltage variety of memory capacitance, C
StBe memory capacitance, C
LcBe pixel capacitance, C
GdGate leakage capacitance for on-off element.Utilize the capacitive coupling principle can realize reducing the purpose of power consumption and noise, therefore, capacitance control signal Vcst is designed to the voltage of the memory capacitance of control break pixel cell, and the Vcst driving circuit that produces capacitance control signal Vcst is the repetition of a Vcst unit in each row pixel.
Can reduce system complexity in conjunction with ASG technology and CC technology, improve operation stability, and promote overall performance.Fig. 1 has shown the combinational circuit of a kind of ASG unit and Vcst unit, shown combinational circuit can be used as a shift unit of the horizontal drive circuit of LCD, usually the horizontal drive circuit of LCD comprises n level shift unit, and wherein, n is the line number of liquid crystal pixel array.As shown in the figure, the ASG unit comprises buffer cell 12 and grid drive signal generation unit 14, and capacitance control signal generation unit 16, VGH are that high-voltage power supply, VGL are LVPS.
Grid drive signal generation unit 14, comprise 4 thin film transistor (TFT) Gate_1, Gate_2, Gate_3 and Gate_4, receive positive output control signal QN, negative output control signal QNb that anti-phase each other positive clock signal CK, negative clock signal CKb and buffering unit 11 produce, produce grid drive signal GateN.Grid drive signal GateN is used to drive the on-off element of the pixel cell of liquid crystal pixel array corresponding row.
Capacitance control signal generation unit 16, comprise 7 thin film transistor (TFT) Vcst_1, Vcst_2, Vcst_3, Vcst_4, Vcst_5, Vcst_6, Vcst_7, receive the first electric capacity control input signals VcstN-3, the second electric capacity control input signals VcstN-2, the first input grid drive signal GateN+1 and the second input grid drive signal GateN-1, produce capacitance control signal VcstN.The first electric capacity control input signals VcstN-3 is the capacitance control signal that the shift unit of first three grade produces, the second electric capacity control input signals VcstN-2 is the capacitance control signal that the shift unit of preceding two-stage produces, the first input grid drive signal GateN+1 is the grid drive signal of back one-level, and the second input grid drive signal GateN-1 is the grid drive signal of previous stage.Capacitance control signal VcstN is used for the voltage of memory capacitance of the pixel cell of control break liquid crystal pixel array corresponding row.
The redundant degree height of combinational circuit shown in Figure 1, input is many, and common LCD all has the pixel of hundreds of row even thousands of row, thereby all brings difficulty for the drives of whole liquid crystal display circuit and layout composing.
Summary of the invention
The present invention solves the driving circuit redundance height of prior art LCD, the problem of layout difficulty.
For addressing the above problem, the embodiment of the invention provides a kind of shift unit, comprising:
First control module, receive clock signal and input control signal produce intermediate control signal;
Second control module receives the intermediate control signal that described first control module produces, and produces the output control signal;
The grid drive signal generation unit receives the output control signal that described clock signal and described second control module produce, and produces the grid drive signal;
The capacitance control signal generation unit receives the intermediate control signal that electric capacity control input signals and described first control module produce, and produces capacitance control signal.
Optionally, described clock signal comprises anti-phase each other positive clock signal and negative clock signal, described input control signal comprises anti-phase each other positive input control signal and negative input control signal, described intermediate control signal comprises anti-phase each other middle control signal and negative intermediate control signal, described first control module comprises: grid is imported first and second transistors of positive clock signal, the described first and second transistorized source electrodes are imported positive input control signal and negative input control signal respectively, and middle control signal and negative intermediate control signal are exported in drain electrode respectively.
Optionally, described output control signal comprises anti-phase each other positive output control signal and negative output control signal, described second control module comprises: the 3rd, the 4th, the the 5th and the 6th transistor, the the described the 3rd and the 6th transistor gate input middle control signal, the negative intermediate control signal of the described the 4th and the 5th transistorized grid input, the the described the 3rd and the 5th transistorized source electrode is imported first voltage, the the described the 4th and the 6th transistorized source electrode is imported second voltage, described third and fourth transistor drain output positive output control signal, the described the 5th, the 6th transistor drain output negative output control signal.
Optionally, described grid drive signal generation unit comprises: seven, the 8th, the 9th and the tenth transistor, the the described the 7th and the 8th transistorized grid is imported positive output control signal and negative output control signal respectively, the described the 9th transistorized grid and the tenth transistorized source electrode are imported positive clock signal, the described the the 7th, the 8th and the 9th transistorized source electrode input negative clock signal, described the 8th transistor drain is connected with the tenth transistorized grid, described the 7th, the 9th and the tenth transistor drain output grid drive signal.
Optionally, described electric capacity control input signals comprises the first electric capacity control input signals and the second electric capacity control input signals, the described second electric capacity control input signals is than half pwm clock signal of the first electric capacity control input signals reverse phase shift, described capacitance control signal generation unit comprises: grid is imported the 11 and the tenth two-transistor of middle control signal and negative intermediate control signal respectively, the described the 11 and the source electrode of the tenth two-transistor import the first electric capacity control input signals and the second electric capacity control input signals respectively, the drain electrode output capacitance control signal of the described the 11 and the tenth two-transistor.
For addressing the above problem, the embodiment of the invention also provides a kind of shift unit, comprise the shift unit that the n level is above-mentioned, wherein, the input control signal that first control module of the 1st grade of shift unit receives comprises outside input control signal, and the input control signal that first control module of other shift units at different levels except that the 1st grade receives comprises the output control signal that first control module of preceding 1 grade of shift unit produces;
The electric capacity control input signals that the capacitance control signal generation unit of the 1st grade of shift unit receives comprises outside first electric capacity control input signals and the outside second electric capacity control input signals, the electric capacity control input signals that the capacitance control signal generation unit of the 2nd grade of shift unit receives comprises outside second electric capacity control input signals and outside the 3rd electric capacity control input signals, the electric capacity control input signals that the capacitance control signal generation unit of 3rd level shift unit receives comprises the capacitance control signal that the capacitance control signal generation unit of outside the 3rd electric capacity control input signals and the 1st grade of shift unit produces, and removes the 1st, 2, the electric capacity control input signals that the capacitance control signal generation unit of other shift units at different levels beyond 3 grades receives comprises the capacitance control signal that the capacitance control signal generation unit of capacitance control signal that the capacitance control signal generation unit of preceding 2 grades of shift units produces and preceding 3 grades of shift units produces.
For addressing the above problem, the embodiment of the invention also provides a kind of LCD, comprises liquid crystal pixel array, horizontal drive circuit and column drive circuit, and described horizontal drive circuit comprises above-mentioned shift unit.
Compared with prior art, above-mentioned shift unit, shift unit and LCD have the following advantages: omitted unnecessary circuit component and input signal cable, circuit structure is simplified; Correspondingly, more flexibility has just been arranged on laying out pattern, can significantly reduce the area that takies, realized narrow frame and miniaturization, and reduced and bad probability occurs.
Description of drawings
Fig. 1 is a kind of example circuit diagram of the shift unit of prior art LCD;
Fig. 2 is the timing diagram of each signal in the 1st grade of shift unit;
Fig. 3 is the timing diagram of each signal in the N level shift unit;
Fig. 4 is a kind of embodiment circuit diagram of shift unit of the present invention;
Fig. 5 is a kind of embodiment circuit diagram of shift unit of the present invention;
Fig. 6 is the timing diagram of each external signal of shift unit shown in Figure 5.
Embodiment
The shift unit of the embodiment of the invention has omitted element and the input signal cable that produces identical intermediate control signal, promptly in conjunction with the accompanying drawings and embodiments the specific embodiment of the present invention is described in detail below.
The horizontal drive circuit of LCD comprises the shift unit that the n level is shown in Figure 1, and wherein, positive clock signal CK, the negative clock signal CKb of odd level shift unit is identical with the negative clock signal CKb of even level shift unit, positive clock signal CK respectively; Positive output control signal QN, the negative output control signal QNb of (N-1) level shift unit output is respectively as the positive input control signal QN-1 of N level shift unit, negative input control signal QN-1b input; The grid drive signal GateN of (N-1), (N+1) level shift unit output imports as the first input grid drive signal GateN+1, the second input grid drive signal GateN-1 of N level shift unit respectively; The capacitance control signal VcstN of (N-2), (N-3) level shift unit output imports as the first electric capacity control input signals VcstN-3, second electric capacity control input control signal VcstN-2 of N level shift unit respectively.
Please in conjunction with reference to figure 1, Fig. 2 and Fig. 3, Fig. 2 has provided the positive clock signal CK of the 1st grade of shift unit, negative clock signal CKb, positive input control signal QN-1, negative input control signal QN-1b, the first electric capacity control input signals VcstN-3, the second electric capacity control input signals VcstN-2, the first input grid drive signal GateN+1, the second input grid drive signal GateN-1, middle control signal 301, negative intermediate control signal 302, first node signal 303, Section Point signal 304, positive output control signal QN, negative output control signal QNb, the timing diagram of grid drive signal GateN and capacitance control signal VcstN.Fig. 3 has provided the N level (timing diagram of above-mentioned each signal of shift unit of 1＜N≤n).
Thin film transistor (TFT) Buffer_1, Buffer_2 produce anti-phase each other middle control signal 301 and negative intermediate control signal 302 according to anti-phase each other positive clock signal CK and negative clock signal CKb, anti-phase each other positive input control signal QN-1 and negative input control signal QN-1b; Thin film transistor (TFT) Buffer_3, Buffer_4, Buffer_5, Buffer_6 constitute a register, and it produces anti-phase each other positive output control signal QN and negative output control signal QNb by middle control signal 301 and 302 controls of negative intermediate control signal.
Thin film transistor (TFT) Vcst_3, Vcst_4, Vcst_5, Vcst_6, Vcst_7 constitute another register, produce anti-phase each other first node signal 303 and Section Point signal 304 according to the first input grid drive signal GateN+1 and the second input grid drive signal GateN-1; The first electric capacity control input signals VcstN-3 of output selectively of first node signal 303 and Section Point signal 304 control TFT Vcst_1, Vcst_2 or the second electric capacity control input signals VcstN-2.
From Fig. 2 and sequential relationship shown in Figure 3, middle control signal 301 is identical with first node signal 303, and negative intermediate control signal 302 is identical with Section Point signal 304.
Based on the sequential relationship of Fig. 2 and each signal shown in Figure 3, the circuit of shift unit shown in Figure 1 can be simplified.Please refer to Fig. 4, the shift unit of the embodiment of the invention comprises: first control module 22, second control module 23, grid drive signal generation unit 24 and capacitance control signal generation unit 26.
Grid drive signal generation unit 24, the output control signal that receive clock signal and described second control module 23 produce produces grid drive signal GateN.
Capacitance control signal generation unit 26 receives the intermediate control signal that electric capacity control input signals and described first control module 22 produce, and produces capacitance control signal Vcst.In the present embodiment, the electric capacity control input signals comprises the first electric capacity control input signals VcstN-3 and the second electric capacity control input signals VcstN-2.
Grid drive signal generation unit 24 comprises the 7th transistor Gate_1, the 8th transistor Gate_2, the 9th transistor Gate_3 and the tenth transistor Gate_4, positive output control signal QN imports the grid of the 7th transistor Gate_1, and negative output control signal QNb imports the grid of the 8th transistor Gate_2; Positive clock signal CK imports the grid of the 9th transistor Gate_3 and the source electrode of the tenth transistor Gate_4, and negative clock signal CKb imports the source electrode of the 7th transistor Gate_1, the 8th transistor Gate_2 and the 9th transistor Gate_3; The drain electrode of the 8th transistor Gate_2 is connected with the grid of the tenth transistor Gate_4; The drain electrode of the 7th transistor Gate_1, the 9th transistor Gate_3 and the tenth transistor Gate_4 is connected, output grid drive signal GateN.Positive clock signal CK and negative clock signal CKb are a pair of anti-phase each other signal, the 7th transistor Gate_1, the 8th transistor Gate_2, the 9th transistor Gate_3 and the tenth transistor Gate_4 are N type thin film transistor (TFT), the high level pulsewidth of grid drive signal GateN is identical with the high level pulsewidth of negative clock signal CKb, and the following jumping of grid drive signal GateN is along identical along sequential with the following jumping of positive output control signal QN.
Capacitance control signal generation unit 26 comprises the 11 transistor Vcst_1 and the tenth two-transistor Vcst_2, the grid of middle control signal 301 inputs the 11 transistor Vcst_1, the grid of negative intermediate control signal 302 inputs the tenth two-transistor Vcst_2; The first electric capacity control input signals VcstN-3 imports the source electrode of the 11 transistor Vcst_1, and the second electric capacity control input signals VcstN-2 imports the source electrode of the tenth two-transistor Vcst_2; The drain electrode of the 11 transistor Vcst_1, the tenth two-transistor Vcst_2 connects, output capacitance control signal VcstN.The 11 transistor Vcst_1, the tenth two-transistor Vcst_2 are N type thin film transistor (TFT), and capacitance control signal VcstN optionally exports the first electric capacity control input signals VcstN-3 and the second electric capacity control input signals VcstN-2.The hopping edge phase difference of half clock signal of the hopping edge of the second electric capacity control input signals VcstN-2 and the first electric capacity control input signals VcstN-3, and be anti-phase saltus step, the hopping edge of the hopping edge of capacitance control signal VcstN and the second electric capacity control input signals VcstN-2 differs a clock signal.
Compare with circuit shown in Figure 1, shift unit shown in Figure 4 has omitted thin film transistor (TFT) Vcst_3, Vcst_4, Vcst_5, Vcst_6, Vcst_7 and the first input grid drive signal GateN+1, the second input grid drive signal GateN-1 that produces first node signal 303, Section Point signal 304.
In addition, the transistor of shift unit shown in Figure 4 all is a N type thin film transistor (TFT), and it also can change P type thin film transistor (TFT) into, only need correspondingly change the grid phase of input signals and get final product.
Please refer to Fig. 5, the shift unit of the embodiment of the invention comprises n level shift unit, and wherein, shift unit as shown in Figure 4.
In conjunction with Fig. 4 and Fig. 5, a pair of reciprocal outside positive clock signal CK and outside negative clock signal CKb by the parity rows sequence alternate input to the clock signal input terminal of shift unit, be the outside positive clock signal CK of positive clock signal CK input end input of odd level shift unit, the negative clock signal CKb input end of odd level shift unit is imported outside negative clock signal CKb; The positive clock signal CK input end of even level shift unit is imported outside negative clock signal CKb, the outside positive clock signal CK of the negative clock signal CKb input end input of even level shift unit.
The input control signal that first control module 22 of the 1st grade of shift unit receives comprises outside input control signal, and the input control signal that first control module 22 of other shift units at different levels except that the 1st grade receives comprises the output control signal that first control module 22 of preceding 1 grade of shift unit produces.
Specifically, the input end of the positive input control signal QN-1 of N level shift unit is connected with the output terminal of the positive output control signal QN of (N-1) level (previous stage) shift unit, the input end of the negative input control signal QN-1b of N level shift unit is connected with the output terminal of the negative output control signal QNb of (N-1) level (previous stage) shift unit, wherein, 1＜N≤n.For example, the input end of the positive input control signal QN-1 of 3rd level shift unit is connected with the output terminal of the positive output control signal QN of the 2nd grade of shift unit, and the input end of the negative input control signal QN-1b of 3rd level shift unit is connected with the output terminal of the negative output control signal QNb of the 2nd grade of shift unit.In addition, outside input control signal comprises outside positive input control signal and outside negative input control signal, the input end of the positive input control signal QN-1 of the 1st grade of shift unit is imported outside positive input control signal STV, the outside negative input control signal STVb of the input end input of the negative input control signal QN-1b of the 1st grade of shift unit.Outside positive input control signal STV and outside negative input control signal STVb are a pair of anti-phase each other signals, and its sequential is promptly respectively shown in the positive input control signal QN-1 and negative input control signal QN-1b of Fig. 2.
1st, the electric capacity control input signals that receives of the capacitance control signal generation unit 26 of 2,3 grades of shift units comprises the external capacitive control input signals, and the electric capacity control input signals that the capacitance control signal generation unit 26 of other shift units at different levels except that the 1st, 2,3 grade receives comprises the capacitance control signal of capacitance control signal generation unit 26 generations of the capacitance control signal of capacitance control signal generation unit 26 generations of preceding 2 grades of shift units and preceding 3 grades of shift units.
Specifically, the input end of the first electric capacity control input signals VcstN-3 of N level shift unit is connected with the output terminal of the capacitance control signal VcstN of (N-3) level (first three level) shift unit, the input end of the second electric capacity control input signals VcstN-2 of N level shift unit is connected with the output terminal of the capacitance control signal VcstN of (N-2) level (preceding two-stage) shift unit, wherein, 3＜N≤n.For example, the input end of the first electric capacity control input signals VcstN-3 of the 5th grade of shift unit is connected with the output terminal of the capacitance control signal VcstN of the 2nd grade of shift unit, and the input end of the second electric capacity control input signals VcstN-2 of the 5th grade of shift unit is connected with the output terminal of the capacitance control signal VcstN of 3rd level shift unit.In addition, the external capacitive control input signals comprises the outside first electric capacity control input signals, the outside second electric capacity control input signals and outside the 3rd electric capacity control input signals, the input end of the first electric capacity control input signals VcstN-3 of the 1st grade of shift unit is imported the outside first electric capacity control input signals Vcst-3, and the input end of the second electric capacity control input signals VcstN-2 is imported the outside second electric capacity control input signals Vcst-2; The input end of the first electric capacity control input signals VcstN-3 of the 2nd grade of shift unit is imported the outside second electric capacity control input signals Vcst-2, outside the 3rd electric capacity control input signals Vcst-1 of input end input of the second electric capacity control input signals VcstN-2; Outside the 3rd electric capacity control input signals Vcst-1 of input end input of the first electric capacity control input signals VcstN-3 of 3rd level shift unit, the input end of the second electric capacity control input signals VcstN-2 is connected with the output terminal of the capacitance control signal VcstN of the 1st grade of shift unit.
The sequential relationship of outside positive clock signal CK, outside negative clock signal CKb and the outside first electric capacity control input signals Vcst-3, the outside second electric capacity control input signals Vcst-2, outside the 3rd electric capacity control input signals Vcst-1, outside positive input control signal STV, outside negative input control signal STVb as shown in Figure 6.Need to prove, the high level pulsewidth of outside positive input control signal STV shown in Figure 6 equals outside positive pwm clock signal half, in other embodiments, the high level pulsewidth of outside positive input control signal STV can be greater than half outside positive pwm clock signal and less than a positive pwm clock signal in outside, and the edge is jumped in upward jumping along being ahead of going up of corresponding outside just clock signal CK of outside positive input control signal STV.
Can see in conjunction with Fig. 2 to 5, the grid drive signal of shift units at different levels output is than the grid drive signal of the previous stage shift unit output pwm clock signal that has been shifted half, and the grid drive signal is used to drive the on-off element of the pixel cell of liquid crystal pixel array corresponding row.The capacitance control signal of shift units at different levels output than the capacitance control signal reverse phase shift of previous stage shift unit output half pwm clock signal, capacitance control signal is used for the voltage of memory capacitance of the pixel cell of control break liquid crystal pixel array corresponding row.
The embodiment of the invention also provides a kind of LCD of using above-mentioned shift unit, and described LCD comprises liquid crystal pixel array, horizontal drive circuit and column drive circuit.Wherein, horizontal drive circuit comprises shift unit shown in Figure 5, and shift unit comprises the shift unit that the n level is shown in Figure 4, and n is the line number of liquid crystal pixel array.
Each pixel cell in the liquid crystal pixel array comprise on-off element, pixel electrode, storage electrode public electrode and be filled in pixel electrode and public electrode between liquid crystal molecule.Pixel electrode is connected with column drive circuit by on-off element, the on-off element of the pixel cell that the grid drive signal GateN of horizontal drive circuit output and liquid crystal pixel array N are capable is connected, control the disconnection and the conducting of described on-off element, when the on-off element conducting, the pixel voltage that carries data-signal that column drive circuit provides is applied on the corresponding pixel electrode.Capacitance control signal VcstN is used for the voltage of the memory capacitance of the capable pixel cell of control break liquid crystal pixel array N.
In sum, above-mentioned shift unit has omitted element and the input signal cable that produces identical intermediate control signal, and just second control module and capacitance control signal generation unit can shared intermediate control signals, therefore makes circuit structure be simplified; Correspondingly, the appropriate reconstruction circuit can make it be more conducive to layout and be easier to drive, and then can significantly reduce the area that chip of LCD takies to eliminate redundancy by simplifying also, realizes narrow frame and miniaturization, and can reduce the bad probability of appearance.
Though oneself discloses the present invention as above with preferred embodiment, the present invention is defined in this.Any those skilled in the art without departing from the spirit and scope of the present invention, all can do various changes and modification, so protection scope of the present invention should be as the criterion with claim institute restricted portion.
Claims (7)
1. a shift unit is characterized in that, comprising:
First control module, receive clock signal and input control signal produce intermediate control signal;
Second control module receives the intermediate control signal that described first control module produces, and produces the output control signal;
The grid drive signal generation unit receives the output control signal that described clock signal and described second control module produce, and produces the grid drive signal;
The capacitance control signal generation unit receives the intermediate control signal that electric capacity control input signals and described first control module produce, and produces capacitance control signal.
2. shift unit as claimed in claim 1, it is characterized in that, described clock signal comprises anti-phase each other positive clock signal and negative clock signal, described input control signal comprises anti-phase each other positive input control signal and negative input control signal, described intermediate control signal comprises anti-phase each other middle control signal and negative intermediate control signal, described first control module comprises: grid is imported first and second transistors of positive clock signal, the described first and second transistorized source electrodes are imported positive input control signal and negative input control signal respectively, and middle control signal and negative intermediate control signal are exported in drain electrode respectively.
3. shift unit as claimed in claim 2, it is characterized in that, described output control signal comprises anti-phase each other positive output control signal and negative output control signal, described second control module comprises: the 3rd, the 4th, the the 5th and the 6th transistor, the the described the 3rd and the 6th transistorized grid input middle control signal, the negative intermediate control signal of the described the 4th and the 5th transistorized grid input, the the described the 3rd and the 5th transistorized source electrode is imported first voltage, the the described the 4th and the 6th transistorized source electrode is imported second voltage, described third and fourth transistor drain output positive output control signal, the described the 5th and the 6th transistor drain output negative output control signal.
4. shift unit as claimed in claim 2, it is characterized in that, described grid drive signal generation unit comprises: the 7th, the 8th, the the 9th and the tenth transistor, the the described the 7th and the 8th transistorized grid is imported positive output control signal and negative output control signal respectively, the described the 9th transistorized grid and the tenth transistorized source electrode are imported positive clock signal, the described the 7th, the the 8th and the 9th transistorized source electrode input negative clock signal, described the 8th transistor drain is connected the described the 7th with the tenth transistorized grid, the the 9th and the tenth transistor drain output grid drive signal.
5. shift unit as claimed in claim 2, it is characterized in that, described electric capacity control input signals comprises the first electric capacity control input signals and the second electric capacity control input signals, the described second electric capacity control input signals is than half pwm clock signal of the first electric capacity control input signals reverse phase shift, described capacitance control signal generation unit comprises: grid is imported the 11 and the tenth two-transistor of middle control signal and negative intermediate control signal respectively, the described the 11 and the source electrode of the tenth two-transistor import the first electric capacity control input signals and the second electric capacity control input signals respectively, the drain electrode output capacitance control signal of the described the 11 and the tenth two-transistor.
6. a shift unit is characterized in that, comprises each described shift unit in the n level claim 1 to 5, wherein,
The input control signal that first control module of the 1st grade of shift unit receives comprises outside input control signal, and the input control signal that first control module of other shift units at different levels except that the 1st grade receives comprises the output control signal that first control module of preceding 1 grade of shift unit produces;
The electric capacity control input signals that the capacitance control signal generation unit of the 1st grade of shift unit receives comprises outside first electric capacity control input signals and the outside second electric capacity control input signals,
The electric capacity control input signals that the capacitance control signal generation unit of the 2nd grade of shift unit receives comprises outside second electric capacity control input signals and outside the 3rd electric capacity control input signals,
The electric capacity control input signals that the capacitance control signal generation unit of 3rd level shift unit receives comprises the capacitance control signal that the capacitance control signal generation unit of outside the 3rd electric capacity control input signals and the 1st grade of shift unit produces,
The electric capacity control input signals that the capacitance control signal generation unit of other shift units at different levels except that the 1st, 2,3 grade receives comprises the capacitance control signal that the capacitance control signal generation unit of capacitance control signal that the capacitance control signal generation unit of preceding 2 grades of shift units produces and preceding 3 grades of shift units produces.
7. a LCD comprises liquid crystal pixel array, horizontal drive circuit and column drive circuit.It is characterized in that described horizontal drive circuit comprises the described shift unit of claim 6.
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| CN200910053537A CN101930712B (en) | 2009-06-19 | 2009-06-19 | Shift unit, shift device and liquid crystal display |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2016106830A1 (en) * | 2014-12-31 | 2016-07-07 | 深圳市华星光电技术有限公司 | Goa circuit and liquid crystal display device |
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2009
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2016106830A1 (en) * | 2014-12-31 | 2016-07-07 | 深圳市华星光电技术有限公司 | Goa circuit and liquid crystal display device |
| GB2548760A (en) * | 2014-12-31 | 2017-09-27 | Shenzhen China Star Optoelect | GOA circuit and liquid crystal display device |
| GB2548760B (en) * | 2014-12-31 | 2021-01-20 | Shenzhen China Star Optoelect | GOA circuit and liquid crystal display device |
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| Publication number | Publication date |
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| CN101930712B (en) | 2012-10-17 |
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