CN101924900B

CN101924900B - A Synchronous Clock Distribution System Supporting HD/SD Simulcast

Info

Publication number: CN101924900B
Application number: CN201010210678.4A
Authority: CN
Inventors: 程鹏; 姚景国
Original assignee: Dalian Gigatec Electronics Co ltd
Current assignee: Dalian Jiecheng Technology Co Ltd
Priority date: 2010-06-26
Filing date: 2010-06-26
Publication date: 2014-07-02
Anticipated expiration: 2030-06-26
Also published as: CN101924900A

Abstract

A synchronous clock distribution system supporting high/standard definition simulcast, the front end of the system supports two paths of external synchronous signals and is designed with two synchronous clock extraction modules, and the two paths of external synchronous signals can be arbitrarily distributed to the synchronous clock extraction modules through a front end matrix; two synchronous clock extraction modules adopt high/standard definition compatible synchronous extraction chips; the rear end of the system adopts a matrix design, the synchronous clocks extracted by the two synchronous clock extraction modules are input into the matrix, each functional module slot in the broadcasting platform corresponds to one matrix to output, and the functional modules in each broadcasting platform select the required synchronous clocks (high definition/standard definition) according to requirements. The system can realize the mixed insertion of high/standard definition functional modules which need to be synchronized in the same broadcasting platform; the synchronous clock of the function module in each slot position is convenient to select; and the cost of the broadcasting system is reduced.

Description

A kind of synchronous clock distribution system of supporting high/standard definition simulcast

Technical field

The present invention relates to a kind of synchronous synchronous clock distribution system broadcasting of vision signal of supporting, relate in particular to the synchronous clock distribution system of simultaneously supporting high-definition video signal and SD vision signal.

Background technology

In Broadcast and TV system, be that high-definition video signal or SD vision signal all need to do synchronous broadcast, therefore can provide the broadcast platform of synchronised clock to be used widely in broadcast system.Can provide the broadcast platform of synchronised clock structurally will have multiple grooves position, support several functions module to work simultaneously, need to possess synchronous extraction and synchronous distribution function in function, the interconnection system of tradition broadcast platform as shown in Figure 1.Traditional broadcast platform is limited by its synchronous clock distribution system, only support SD signal to broadcast, only supporting high-definition signal to broadcast, even if support the compatible broadcast of high/standard definition, must be also the functional module of all processing high-definition signal or all processing SD signal in platform.

In Broadcast and TV system, the development speed of HD video is very fast, and industry generally believes that HD video will replace SD video completely after 10 years, and in these 10 years, can not delay the development of HD video, guarantees again the normal use of SD video user.Tradition is broadcasted the application of platform in high/standard definition simulcast system as shown in Figure 2, not only uses dumbly under this applied environment, but also can increase the cost of broadcast system.

Summary of the invention

The present invention is directed to the problems referred to above, design a kind of synchronous clock distribution system of supporting high/standard definition simulcast, be intended to solve tradition broadcast platform application dumb, increase the problem of broadcast system cost.

Technical scheme of the present invention is as follows: the front end support two-way external synchronization signal of system is also designed with two synchronised clock extraction modules, and two-way external synchronization signal can be distributed to arbitrarily synchronised clock extraction module through front end matrix.What two synchronised clock extraction modules adopted in design is the synchronous extracting chip of high/standard definition compatibility.Such Front-end Design has realized an interconnection system extracts the function of two kinds of different synchronised clocks (high definition/SD) simultaneously.What the rear end of system adopted is matrix form design, the input that the synchronised clock of two synchronised clock extraction module extractions is matrix, broadcast the corresponding Output matrix in each functional module groove position in platform, each functional module of broadcasting in platform can be selected needed synchronised clock (high definition/SD) according to demand like this.

First utilize analog selection switch 2 × 2 matrixes of Front-end Design at synchronous clock distribution system, realize the selection of the external reference signal input of synchronised clock extraction module by this matrix.Jiang Yi road REF signal is received respectively an input pin of two analog selection switches, another road REF signal is received respectively another input pin of two analog selection switches, the output of two analog selection switches provides reference signal to respectively two synchronised clock extraction modules, and arbitrary synchronised clock extraction module all can be selected needed External Reference REF signal by the input selection pin of analog selection switch.

Synchronised clock extraction module adopts the synchronous extracting chip of high/standard definition compatibility from External Reference signal, to extract the synchronous control signal such as HS (line synchronizing signal), VS (field sync signal) and OE (parity field signal), row, field sync signal that the synchronous extracting chip of high/standard definition compatibility is extracted are given genlock chip, and the high/standard definition synchronizing clock signals that genlock chip produces is selected the synchronised clock output identical with reference signal through differential signal selector switch again.

In the rear end of synchronous clock distribution system, the synchronous control signal (HS, VS, OE etc.) that the synchronous extracting chip of two-way high/standard definition compatibility is extracted is all given FPGA/CPLD, FPGA/CPLD is matrix circuit structure, each groove position of broadcasting on platform all can obtain one group of independently synchronous control signal from FPGA/CPLD, and every group of synchronous control signal all can be selected one in the synchronous control signal of the synchronous extracting chip extraction of two-way high/standard definition compatibility; For synchronised clock, each groove position is all furnished with a differential signal selector switch, and the output synchronised clock of two synchronised clock extraction modules is accessed respectively in its two-way input port.Make each groove position can independently select synchronizing clock signals by differential signal selector switch like this.

Utilize new synchronous clock distribution system, broadcast platform and complete high/standard definition simulcast design as shown in Figure 7.

Beneficial effect of the present invention: can realize and need synchronous high/standard definition functional module mixed insertion in same broadcast platform; Facilitate the synchronised clock of functional module in each groove position to choose; Reduce broadcast system cost.

Accompanying drawing explanation

Below in conjunction with the drawings and specific embodiments, the invention will be further described.

Fig. 1 is the interconnection system schematic diagram that tradition is broadcasted platform.

Fig. 2 is that tradition is broadcasted the application principle figure of platform in high/standard definition simulcast system.

Fig. 3 is synchronous clock distribution system front end schematic diagram of the present invention.

Fig. 4 is the synchronous extraction schematic diagram in synchronous clock distribution system of the present invention.

Fig. 5 is synchronous clock distribution system backend synchronization distribution principle figure a of the present invention.

Fig. 6 is synchronous clock distribution system backend synchronization distribution principle figure b of the present invention.

Fig. 7 is the application principle figure of the present invention in high/standard definition simulcast system.

Embodiment

First the present embodiment utilizes 4053 (bidirectional analog selector switches) 2 × 2 matrixes of Front-end Design at synchronous clock distribution system, realizes the selection of synchronised clock extraction module to input External Reference signal by this matrix.As shown in Figure 3, REF1 is received respectively to the S1 pin of 4053-1 and 4053-2, REF2 receives respectively the S2 pin of 4053-1 and 4053-2, and the output D of 4053-1 provides reference signal to synchronised clock extraction module A, and the output D of 4053-2 provides reference signal to synchronised clock extraction module B.So the arbitrary synchronised clock extraction module of design all can be selected needed External Reference REF signal by 4053 C pin.

As shown in Figure 4, the design of synchronised clock extraction module adopts two LMH1981 (and similar chip) from External Reference signal, to extract the synchronous control signal such as HS (line synchronizing signal), VS (field sync signal) and OE (parity field signal).LMH1981 input REF signal is supported the synchronizing signals such as SD analog video or high definition three level.Row, the field sync signal that two LMH1981 are extracted given two LMH1982 and is used for phase-locked generation high/standard definition synchronizing clock signals.The high/standard definition synchronizing clock signals that two-way LMH1982 produces is selected the synchronised clock output identical with reference signal through two paths of differential signals selector switch DS90CP22 again.

As shown in Figure 5,6, in the rear end of synchronous clock distribution system, the synchronous control signal (HS, VS, OE etc.) that two-way LMH1981 extracts is all given FPGA, FPGA is designed to matrix circuit structure, each groove position of broadcasting on platform all can obtain one group of independently synchronous control signal from FPGA, and every group of synchronous control signal all can be selected one in the synchronous control signal of two-way LMH1981 extraction.For synchronised clock, each groove position is all furnished with a DS90CP22, and the synchronised clock of two synchronised clock extraction module outputs is accessed respectively in its two-way input port, makes each groove position can independently select synchronizing clock signals like this by DS90CP22.

Utilize system of the present invention, broadcast design that platform completes high/standard definition simulcast as shown in Figure 7.

The present invention is not limited to above-described embodiment, and equivalent concepts or change in any technical scope disclosing in the present invention, all classify protection scope of the present invention as.

Claims

1. A synchronous clock distribution system supporting high/standard definition simulcast, characterized in that: the front end of the system supports two external synchronous signals and is designed with two synchronous clock extraction modules, and the two external synchronous signals can be distributed arbitrarily through the front-end matrix to the synchronous clock extraction module; the two synchronous clock extraction modules adopt high/standard definition compatible synchronous extraction chips; Each functional module slot in the platform corresponds to a matrix output, and each functional module in the broadcasting platform selects the required HD/SD synchronous clock according to the requirements;

Design a 2×2 matrix at the front end of the system by using two analog selection switches, the matrix realizes the selection of the input external reference signal by the synchronous clock extraction module, and connects one REF signal to one input pin of the two analog selection switches respectively , the other REF signal is respectively connected to the other input pin of the two analog selection switches, and the outputs of the two analog selection switches provide reference signals for the two synchronous clock extraction modules, and any synchronous clock extraction module can pass the analog selection switch The input selection pin selects the required external reference REF signal;

The synchronous clock extraction module adopts the high/standard definition compatible synchronous extraction chip to extract the synchronous control signal from the external reference signal, and sends the line and field synchronous signals extracted by the high/standard definition compatible synchronous extraction chip to the genlock chip, and the genlock chip The generated high/standard definition synchronous clock signal is selected by the differential signal selection switch to output the same synchronous clock as the reference signal;

At the back end of the system, the synchronous control signals extracted by two high-definition/standard-definition compatible synchronous extraction chips are all sent to FPGA/CPLD. FPGA/CPLD obtains a set of independent synchronous control signals, and each set of synchronous control signals can select one of the synchronous control signals extracted by two high-definition/standard-definition compatible synchronous extraction chips; for the synchronous clock, each slot is It is equipped with a differential signal selection switch, and its two input ports are respectively connected to the output synchronous clocks of the two synchronous clock extraction modules.