CN101917190B - Phase lock loop (PLL) circuit as well as phase synchronization method and motion analysis method thereof - Google Patents

Abstract

The invention relates to a phase lock loop (PLL) circuit. The PLL circuit comprises a phase comparator (2), a level shifter (3), a voltage-controlled oscillator (VCO) (4) and a frequency divider (5), wherein the phase comparator (2) compares the phases of a reference clock signal and a comparison clock signal to generate a phase comparison signal which has three values of high-voltage (referred as H) level, low-voltage (referred as L) level and reference level and outputs an H or L level signal in correspondence with the time width of detected phase difference, and outputs a reference level signal when no phase difference is detected; the level shifter (3) enables the waveform of the phase comparison signal from the phase comparator (2) to maintain rectangular; the VCO (4) inputs the H level signal to advance phase, and inputs the L level signal to postpone the phase; and the frequency divider (5) divides the frequency of an oscillation clock pulse output by the VCO as the comparison clock signal.

Description

Phase-locked loop (PLL) circuit and phase synchronization method and action-analysing method

Technical field

The present invention relates to occur PLL (the Phase Locked Loop: phase-locked loop) circuit and phase synchronization method thereof corresponding to the phase difference of reference clock signal and comparison clock signal.

Background technology

For example, in patent documentation (communique among the JP 2004-40227), existing PLL circuit is disclosed.

In existing PLL circuit, phase comparator with following characteristic is housed, that is: with regard to the output signal of excute phase after relatively, the time difference of the time width of the time width of the square-wave signal of its high-voltage level and the square-wave signal of low voltage level is proportional to phase difference, without phase difference the time, high-voltage level equates with the square-wave signal time width of low voltage level, omitted the loop filter that is considered to essential, in the PLL circuit, be provided with the work wave shaping circuit in the part of carrying loop filter, make from the signal waveform of phase-comparison circuit output to keep rectangle.

In addition, the design of voltage-controlled oscillator (VCO:Voltage Controlled Oscillator) is becoming odd function as precondition with frequency variation during as the function of voltage with this voltage-frequency change characteristic.

Patent documentation 1: JP 2004-40227 communique

Summary of the invention

The problem that invention will solve

Because existing PLL circuit has structure described above, need to have at the VCO that frequency variation is become the voltage-frequency characteristic of odd function during as the function of voltage.In the VCO of reality, such characteristic can only be met in the scope of part, can only use in this scope.

In addition, the wide VCO of above-mentioned characteristic range is high price, exists the problem that so-called circuit cost increases.

Also have, because the phase comparator of above-mentioned patent documentation 1 record is not universal component, essential otherwise designed exists the problem that so-called this partial design cost increases.

Have again, in existing PLL circuit, owing to use above-mentioned phase comparator, even also there is frequency variation in the stable state after Phase synchronization finishes from the output of VCO.

The object of the invention is to, obtain the little PLL circuit of frequency variation with the clock signal of low-cost and output.

In order to solve the means of problem

Phase-locked loop of the present invention (PLL) circuit is characterised in that and is provided with:

Phase comparator, the phase difference of input reference clock signal and comparison clock signal and benchmark clock signal and comparison clock signal, according to phase difference, generation and output have the square-wave signal of 3 voltage levels;

Level shifter, input be from the square-wave signal of phase comparator output, the voltage level of mobile square-wave signal, and output makes the square-wave signal behind this voltage level shifting;

Voltage-controlled oscillator (VCO), the square-wave signal that input is exported from level shifter, and export its frequency corresponding to the clock signal of the voltage level of this square-wave signal; And

Frequency divider, the signal behind the clock signal Fractional-N frequency (N is natural number) that will export from VCO is clock signal as a comparison, feeds back to above-mentioned phase comparator.

Above-mentioned phase comparator is characterised in that: carry out the phase bit comparison of reference clock signal and comparison clock signal in each of reference clock signal, generation has the square-wave signal of 3 values such as high-voltage level, low voltage level and reference level in cycle.

Above-mentioned phase comparator is characterised in that: in the situation of the phase difference that has phase place to lag behind in comparison clock signal to cause, the time width that makes the square-wave signal of high-voltage level is proportional to phase difference and generates the square-wave signal of high-voltage level, in comparison clock signal, have in the situation of the phase difference that phase place causes in advance, the time width that makes the square-wave signal of low voltage level is proportional to phase difference and generates the square-wave signal of low voltage level, in the situation without phase difference, the square-wave signal of the square-wave signal of output HIGH voltage level and low voltage level not, the signal of output reference level.

Above-mentioned level shifter is characterised in that: 3 magnitudes of voltage of the magnitude of voltage of the magnitude of voltage of the square-wave signal of the high-voltage level that will export from phase comparator and the square-wave signal of low voltage level and the magnitude of voltage of reference level are transformed into the magnitude of voltage of control VCO.

Above-mentioned level shifter is characterised in that, is provided with: a plurality of resistors that are connected in series; And change the connection of above-mentioned a plurality of resistance and generate the switch of the magnitude of voltage of control VCO according to above-mentioned 3 magnitudes of voltage.

Above-mentioned phase comparator is characterised in that: carry out the phase bit comparison of reference clock signal and comparison clock signal in each of reference clock signal, generation has the square-wave signal of 3 values such as high-voltage level, low voltage level and reference level in cycle.

Above-mentioned VCO is characterised in that: have arbitrarily voltage-frequency characteristic.

Above-mentioned PLL circuit is characterised in that: with the Mathematical Modeling of the response of ordered series of numbers performance PLL circuit as operation principle.

The phase synchronization method of phase-locked loop of the present invention (PLL) circuit is characterised in that:

Input reference clock signal and comparison clock signal, the phase difference of benchmark clock signal and comparison clock signal has the square-wave signal of 3 voltage levels according to phase difference generation and output;

Input above-mentioned square-wave signal, the voltage level of mobile square-wave signal, output makes the square-wave signal behind this voltage level shifting;

Input makes the square-wave signal behind the above-mentioned voltage level shifting, exports its frequency corresponding to the clock signal of the voltage level of this square-wave signal;

Signal behind the above-mentioned clock signal Fractional-N frequency (N is natural number) is fed back as above-mentioned comparison clock signal.

Be further characterized in that: in the cycle of each reference clock signal, carry out the phase bit comparison of reference clock signal and comparison clock signal, generation has the square-wave signal of 3 values such as high-voltage level, low voltage level and reference level.

The action-analysing method of phase-locked loop of the present invention (PLL) circuit is the action-analysing method of phase-locked loop (PLL) circuit that is provided with following parts, and these parts are:

Phase comparator, input reference clock signal and comparison clock signal, the phase place of benchmark clock signal and the phase place of comparison clock signal, generation and output have the square-wave signal corresponding to the predetermined voltage level of the time width of phase difference;

Voltage-controlled oscillator (VCO), the signal that input is exported from phase comparator, and export its frequency corresponding to the clock signal of the voltage level of this signal;

Frequency divider, will from the clock signal of the VCO output signal after by Fractional-N frequency (N is natural number) as a comparison clock signal feed back to above-mentioned phase comparator; It is characterized in that:

The phase difference of said reference clock signal and comparison clock signal is carried out motion analysis with following Mathematical Modeling.

θ _n＝(1-((G·T)/(2π·N))) ⁿ·θ

N: natural number

π: circumference ratio

G: corresponding to the constant of the voltage-frequency characteristic of VCO

T: the cycle of oscillation of reference clock signal

N: the divider ratio of frequency divider (natural number)

θ: the phase difference in the moment 0

θ _n: the phase difference of moment nT

Description of drawings

Fig. 1 is the block diagram of the PLL circuit of the explanation embodiment of the invention 1.

Fig. 2 is the block diagram of realization example of the level shifter of the expression embodiment of the invention 1.

Fig. 3 represents the voltage-frequency characteristic of VCO of the PLL circuit of the embodiment of the invention 1.

Fig. 4 is the concept map that expression is used for the elemental motion of the phase comparator of the embodiment of the invention 1 and level shifter.

Fig. 5 is the figure of Mathematical Modeling of the PLL circuit of the explanation embodiment of the invention 1.

Fig. 6 represents the phase control method of the PLL circuit of the embodiment of the invention 1.

Embodiment

Embodiment 1

Below, by PLL (the Phase Locked Loop) circuit 100 of figure explanation embodiments of the invention 1.So-called PLL circuit is also referred to as Phase synchronization loop etc., is to generate the circuit that does not have the output signal of phase deviation with input signal.

In Fig. 1, input terminal 1 is the terminal of input reference clock signal FR.

The phase place of 2 signals of 2 pairs of inputs of phase comparator compares, and compares its phase difference, the phase difference output detection signal.Phase comparator 2 output HIGH voltages (below be designated as H) level square-wave signal and low-voltage (below be designated as L) level square-wave signal.Phase comparator 2 is according to phase difference, and the square wave that the time width of the time width of H level square-wave signal or L level square-wave signal is proportional to phase difference is exported as phase difference detection signal PD.Without phase difference the time, phase comparator 2 output reference level voltages.

Level shifter 3 is work wave reshapers, makes the signal waveform from the phase difference detection signal PD of phase comparator 2 remain rectangle.

Voltage-controlled oscillator (VCO:Voltage Controlled Oscillator) the 4th has control terminal, can make frequency of oscillation according to the oscillator that is added in the DC voltage change of the direct current signal DC on the control terminal.Here, VCO4 is the oscillator that N times (N is natural number) occured in the oscillating clock signal CL of the frequency of reference clock signal.

Frequency divider 5 is that oscillating clock signal CL frequency division is become 1/N, and exports the Clock dividers of comparison clock signal FP to phase comparator 2.

Lead-out terminal 6 is terminals of output oscillating clock signal CL.

Fig. 2 is the figure of the realization example of expression level shifter 3.

In Fig. 2, SW1 and SW2 are basis opens and closes signal contact from the output level of the square-wave signal of phase comparator 2 analog switches.SW1 is phase detection signal PD only becomes ON when H level square-wave signal switch.SW2 is phase detection signal PD only becomes ON when L level square-wave signal switch.Time in addition, SW1 and SW2 are OFF.SW1 and SW2 can not become ON simultaneously.

R1, R2, R3, R4 are the resistance (or its resistance value) of setting the voltage level of the direct current signal DC that inputs to VCO4.R1, R2, R3, R4 are connected in series, applied voltage Vcc.

SW1 and SW2 basis form following open and-shut mode from the output level of the square-wave signal of phase comparator 2.The voltage level of direct current signal DC of VCO4 that inputs to this moment is as follows.

SW1 because R2 is bypassed, becomes in ON, the SW2 situation at OFF:

Voltage level=Vcc * ((R3+R4)/(R1+R3+R4))

Voltage level is high voltage.Below, this high voltage signal (or its magnitude of voltage) is represented with VH.

SW1 is at OFF, and SW2 because R3 is bypassed, becomes in the situation of ON:

Voltage level=Vcc * ((R4)/(R1+R2+R4))

Voltage level becomes low-voltage.Below, this low voltage signal (or its magnitude of voltage) is represented with VL.

When SW1 at OFF, SW2 is when OFF, because R1～R4 all is connected, becomes:

Voltage level=Vcc * ((R3+R4)/(R1+R2+R3+R4)),

Voltage level becomes V _HWith V _LBetween reference voltage.Below, this reference voltage signal (or its magnitude of voltage) is used V _nExpression (V _H＞V _n＞V _L).

Fig. 3 is the figure of the voltage-frequency characteristic of expression VCO4.

Among Fig. 3, transverse axis is the input voltage v that transports to the direct current signal DC of VCO4.Input voltage v gets the value from 0 volt to the Vcc volt.

The longitudinal axis is the output frequency f from the oscillating clock signal CL of VCO4.Here, with frequency f ₀Be made as the frequency of 1/N of the frequency f r of reference clock signal FR.Input voltage v is in the time of 0 volt, and output frequency f is frequency f ₀-df.But when input voltage v was the Vcc volt, output frequency f did not constitute f ₀+ df.But, if suitably select above-mentioned V _H, V _L, then become as follows.

V _nThat output frequency f becomes frequency f ₀Reference voltage.

V _LThat output frequency f becomes frequency f ₀The low-voltage of-Δ f.

VH is that output frequency f becomes frequency f ₀The high voltage of+Δ f.

Here, the relation of 3 voltage levels is V _H＞V _n＞V _LBut, be not limited to V _H-V _m=V _n-V _L

In Fig. 3, if output frequency f is apart from frequency f ₀Frequency variation become the function g (v) of input voltage v, then by the characteristic curve of Fig. 3 as can be known, become

g(V _H)＝-g(V _L)＝Δf、g(V _n)＝0

Namely be

Δ f=G (G is constant)

Level shifter 3 presets level, makes above V _H, V _n, V _LOccur.That is, level shifter is set level, make the output frequency of the VCO that exports corresponding to this H level follow the output frequency of the VCO that exports corresponding to the L level to equate opposite in sign with poor (Δ f) absolute value of the clock frequency of reference voltage with poor (the Δ f) of the clock frequency of reference voltage.

Moreover, if the frequency of oscillating clock signal CL is made as f ₀, the frequency of reference clock signal FR is made as fr, the frequency of comparison clock signal FP is made as fp, then the relation in the frequency of the oscillating clock signal CL of stable state is

f ₀＝N×fr，fr＝fp

Fig. 4 is the elemental motion concept map of expression phase comparator 2 and level shifter 3.

Transverse axis represents the time.The longitudinal axis represents: the signal waveform of the signal waveform of reference clock signal FR, comparison clock signal FP, from the output waveform of the phase difference detection signal PD of phase comparator 2, from the voltage of the direct current signal DC of level shifter 3, namely to the input voltage v of VCO4.

Fig. 4 represents the situation of the phase deviation θ of comparison clock signal FP and reference clock signal FR.In phase comparator 2, detect this phase difference θ.-θ represents that the phase place of comparison clock signal FP lags behind.+ θ represents that the phase place of comparison clock signal FP is leading.

Phase comparator 2 is when having phase place to lag behind, in order to make phase place in advance (for SW1 is placed ON), the square-wave signal from moment t1 to moment t2 output voltage V cc.The square-wave signal of level shifter 3 input voltage Vcc, and SW1 placed ON, voltage is altered to V _HAnd output direct current signal DC.Carry out such operation successively until the phase difference θ in n cycle (n is natural number) _n(n is natural number), at the moment in n cycle t3, phase place consistent (Fig. 4 is the situation of n=1).

When phase place is consistent, the signal of phase comparator 2 output voltage V cc/2.The signal of level shifter 3 input voltage Vcc/2 places OFF with SW1 and SW2, and voltage is altered to V _nAnd output direct current signal DC.Perhaps, keep the OFF of SW1 and SW2, output maintains V with voltage _nDirect current signal DC.

Phase comparator 2 postpones (for SW2 is placed ON) in order to make phase place, from the square-wave signal of moment t4 to t5 output voltage 0 (GND) when having phase place leading.The square-wave signal of level shifter 3 input voltages 0 places ON with SW2, and voltage is altered to V _LAnd output direct current signal DC.Carry out such operation successively until the phase difference θ n (n is natural number) in n (n is natural number) cycle, the moment in n cycle t6 phase place consistent (Fig. 4 is the situation that n equals 1).

Fig. 5 is illustrated in the phase comparator 2, the detection signal waveform when detecting comparison clock signal FP than reference clock signal FR phase deviation θ.

In Fig. 5, transverse axis represents the time.The longitudinal axis represents the voltage of direct current signal DC, namely to the voltage level of the input voltage v of VCO4.

T is the time (T=1/fr) in 1 cycle of reference clock signal FR.

V _nIt is the reference voltage that consists of benchmark.V _nThe V with Fig. 3 and Fig. 4 _nIdentical voltage.

V _LIt is the low-voltage that consists of L level part.V _LThe V of Fig. 3 and Fig. 4 _L, V _LIt is the signal that phase place is postponed.

V _HIt is the high voltage that consists of H level part.V _HThe V of Fig. 3 and Fig. 4 _H, V _HIt is the signal that phase place is shifted to an earlier date.

V _HForm convex, V _LForm the square-wave signal of spill.

In Fig. 5, V _HBe central authorities (half period calibration, the i.e. T/2) rising from 1 cycle, only during (θ/2 π) T, become high voltage, afterwards, be back to reference voltage.

V _LBecome low-voltage during (θ/2 π) T from the central authorities (T/2) in 1 cycle, afterwards, the central authorities (T/2) in 1 cycle are back to reference voltage.

In Fig. 4, V _HAnd V _LBe output in the place identical with the place of phase deviation, and as shown in Figure 5, because phase comparator 2 with T/2 centering and phase difference output detection signal PD, is exported V with the T/2 centering _HAnd V _L, can within 1 cycle T, carry out reliably the adjustment of phase place.

V _HAnd V _LTime width (θ/2 π) T during.That is, V _HAnd V _LTime width be proportional to phase difference θ.Thereby, only during (θ/2 π) T, consist of the frequency f of oscillating clock signal CL ₀+ Δ f, or f ₀The frequency of-Δ f, its result, the phase place of oscillating clock signal CL are leading with the amount that is proportional to θ, or lag behind with the amount that is proportional to θ.

Below, with regard to the phase synchronization method of PLL circuit 100, describe with the workflow diagram of Fig. 6.

Input step S1

At first, the clock signal FR that is inputted by the input terminal 1 of reference clock signal is input to phase comparator 2.In addition, from the oscillating clock signal CL of VCO4 with frequency divider 5 frequency divisions to 1/N, with its as a comparison clock signal FP input to phase comparator 2.

Phase place comparison step S2

Then, in phase comparator 2, carry out the phase bit comparison of reference clock signal FR with the comparison clock signal FP of input.Phase comparator 2 is phase differences relatively, and the square wave that the time width of the time width of H level square-wave signal or L level square-wave signal is proportional to phase difference is exported as phase difference detection signal PD.

When phase comparator 2 lags behind in the phase place that detects comparison clock signal FP, the H level square-wave signal that lies prostrate for the voltage vcc that phase place is exported in advance make SW1 place ON.The time width of H level square-wave signal is proportional to phase difference.During its time width (θ/2 π) T.

When phase place is consistent, the signal of phase comparator 2 output voltage V cc/2.

Phase comparator 2 detects the phase place of comparison clock signal FP when leading, exports the L level square-wave signal of the voltage 0 volt (GND) that makes SW2 place ON for phase place is postponed.The time width of L level square-wave signal is proportional to phase difference.During its time width (θ/2 π) T.

Here, suppose that the output of phase comparator 2 is as follows.

The H level is substantially equal to power source voltage Vcc, is than the abundant high current potential of Vcc/2, and the L level is substantially equal to earthing potential GND=0 volt, is the current potential fully lower than Vcc/2.

In addition, fiduciary level is substantially equal to Vcc/2, is fully lower than Vcc, than the abundant high current potential of GND.

These are set, and are attainable (for example, R1, R4＜R2, R3) by the value of selecting R1, R2, R3, R4.

Level moves step S3

Become the input of level shifter 3 from the phase difference detection signal PD of these phase comparator 2 outputs.

Here, level shifter 3 constitutes shown in illustration 2, the SW1 of Fig. 2 action and with the R2 short circuit when the current potential input of Vcc roughly, current potential input beyond this then is failure to actuate, in addition, the SW2 of Fig. 2 moves when roughly the current potential of GND is inputted and with the R3 short circuit, the current potential input beyond this then is failure to actuate.

In level shifter 3, eliminate overshoot or the undershoot of this phase detection signal PD, the H level translation is become

V _H＝Vcc×((R3+R4)/(R1+R3+R4))

The L level translation is become

V _L=(R4/ (R1+R4+R3)) is transformed into reference level again

Vn=((R3+R4)/(R1+R2+R3+R4)) inputs to VCO4 as the frequency control voltage of transporting to VCO4.

Vibration step S4

VCO4 is converted into the phase mass that will cut down at the interval in 1 cycle with the time width of H level square-wave signal, vibrates.In addition, the time width with L level square-wave signal is converted into and will in the additional phase mass in the interval in 1 cycle, vibrates.

That is, in 1 cycle T of the frequency control voltage that is input to VCO4, the phase mass that on the interval in this 1 cycle, will add or cut down, involved as the time width of the time width of H level square-wave signal or L level square-wave signal.VCO4 reads this time width, and according to vibrating according to the clock signal C L after this time width adjustment oscillation phase.

Above-mentioned action is shown in Fig. 4, when comparison clock signal FP lags behind than the phase place of reference clock signal FR, with the time width that is proportional to this phase difference from level shifter 3 output V _H, when comparison clock signal FP is more leading than the phase place of reference clock signal FR, export V with the time width that is proportional to this phase difference from level shifter 3 _LIn addition, do not exporting V _HAnd V _LThe time, the output of level shifter 3 is maintained at V _n

Moreover, when between comparison clock signal FP and reference clock signal FR, not having phase difference, that is, when establishing, Phase synchronization also exports V _n

Output step S5

From the oscillating clock signal CL of VCO4 output, a part is exported from lead-out terminal 7 to the outside as the output from the PLL circuit, and another part is input to frequency divider 5 as branch.

Frequency division step S6

Oscillating clock signal CL is by frequency divider 5N frequency division, and clock signal FP feeds back to phase comparator 2 again as a comparison.

The PLL circuit of present embodiment is after Phase synchronization is established, and phase comparator 2 is output as stable reference level voltage vcc/2, and the output of accepting its level shifter also becomes the reference level V of stable VCO4 _n, can predict that from the output frequency of VCO4, namely therefore the output frequency of PLL circuit becomes equable clock output.

In the present embodiment, record and narrate the action of PLL without transfer function, and process as the ordered series of numbers of the phase adjustment of 1 cycle portions of reference clock signal FR.For example, in phase comparator 2, when detecting comparison clock signal FP and only being θ than the phase place lag or lead of reference clock signal FR, its detection signal waveform becomes Fig. 5.

Here, with V _nThe position as datum line, when observing the H level part of this waveform and L level part, from the characteristic of the VCO4 of Fig. 3, as shown in Figure 5, the H level partly consists of the key element that makes phase place leading, the L level partly consists of the key element that makes the phase place hysteresis.

Namely, with respect to reference clock signal FR, when the phase place that detects the θ of comparison clock signal FP lags behind, can make the phase place of comparison clock signal FP be proportional in advance the amount of the phase difference θ of reference clock signal FR and comparison clock signal FP according to the leading key element of phase place shown in Figure 5.In addition, with respect to reference clock signal FR, when the phase place of the θ that detects comparison clock signal FP was leading, can make according to phase place hysteresis key element shown in Figure 5 the phase place hysteresis of comparison clock signal FP only was the amount that is proportional to the phase difference θ of reference clock signal FR and comparison clock signal FP.

As previously discussed, the PLL circuit of present embodiment is the circuit that phase comparator 2 is housed, the output signal that this phase comparator 2 carries out the phase bit comparison has the 3 values output of H level square-wave signal, L level square-wave signal and reference level, with time width output H level signal or the L level signal corresponding to detected phase difference, outputting standard level voltage during without phase difference.

In addition, the PLL circuit of present embodiment is the circuit that level shifter 3 is housed, and its effect is to make from the signal waveform of phase comparator 2 outputs to remain rectangle.

Above-mentioned level shifter 3 is that level is set output voltage (V _n, V _H, V _L) circuit, make corresponding to H level output V _HThe output frequency (f of VCO4 ₀+ Δ f) with the clock frequency (f of reference voltage V n ₀) poor (Δ f) and corresponding to the L level of above-mentioned level shifter 3 output V _LThe output frequency (f of VCO4 ₀-Δ f) and reference voltage V _nClock frequency (f ₀) poor (Δ f) become that absolute value equates but opposite in sign (| Δ f|=|-Δ f|).

In addition, the PLL circuit of present embodiment is that phase difference with 1 cycle portions of reference clock signal is as the circuit that carries out motion analysis and design with the ordered series of numbers of 1 unit of measurement.About this point, below explanation.

The Mathematical Modeling of these circuit operations of quantitative description below is described.

If will be made as θ at the reference clock signal FR of moment t=0 and the phase difference of comparison clock signal FP, then the phase difference ψ (t) in moment t＞0 o'clock is provided by following formula.

[formula 1]

$\mathrm{\ψ}\left(t\right)=\mathrm{\θ}-\frac{1}{N}\·{\∫}_0^{t}g\left(v\left(x\right)\right)\mathrm{dx}$

, will moment t=(n-1) T (n=1,2,3 ...) and reference clock signal FR and the phase difference of comparison clock signal FP (deduct from the phase place of reference clock signal FR the phase place of comparison clock signal FP after value) as θ _N-1, the voltage v (t) that inputs to VCO4 during (n-1) T＜t＜nT represents with step function U (t)

[formula 2]

$U\left(t\right)=\left\{\begin{array}{cc}1,& t>0\\ 0,& t<0\end{array}\right.$

[formula 3]

${\mathrm{\&tau;}}_n=(n-1)T+\frac{|{\mathrm{\&theta;}}_n-1|}{2\mathrm{\&pi;}}T$

In that event, then at the phase place hysteresis (θ of comparison clock signal FP than reference clock signal FR _N-1＞0) time, constitutes following formula.

[formula 4]

v(t)＝V _H·U[t-(n-1)T]-V _H·U(t-τ _n)

+V _n·U(t-τ _n)-V _n·U(t-nT)

This with

[formula 5]

$v\left(t\right)=\left\{\begin{array}{cc}{V}_H,& (n-1)T<t\&le;{\mathrm{\&tau;}}_n\\ V_{n,}& {\mathrm{\&tau;}}_n<t\&le;\mathrm{nT}\end{array}\right.$

With value.

If with following formula v (t) substitution g (v), the function with g is transformed into time t then obtains

[formula 6]

$g\left(t\right)=\left\{\begin{array}{cc}g\left(V_H\right)=\mathrm{\&Delta;f}=G,& (n-1)T<t\&le;{\mathrm{\&tau;}}_n\\ g\left(V_n\right)=0,& {\mathrm{\&tau;}}_n<t\&le;\mathrm{nT}\end{array}\right.$

Equally, at comparison clock signal FP than the leading (θ of reference clock signal FR phase place _N-1＜0) in the situation,

[formula 7]

v(t)＝V _L·U[t-(n-1)T]-V _L·U(t-τ _n)

+V _n·U(t-τ _n)-V·U(t-nT)

This with

[formula 8]

$v\left(t\right)=\left\{\begin{array}{cc}{V}_L,& (n-1)T<t\&le;{\mathrm{\&tau;}}_n\\ V_n,& {\mathrm{\&tau;}}_n<t\&le;\mathrm{nT}\end{array}\right.$

With value.

If in above-mentioned v (t) substitution g (v), the function with g is transformed into time t then obtains

[formula 9]

$g\left(t\right)=\left\{\begin{array}{cc}g\left(V_L\right)=-\mathrm{\&Delta;f}=-G,& (n-1)T<t\&le;{\mathrm{\&tau;}}_n\\ g\left(V_n\right)=0,& {\mathrm{\&tau;}}_n<t\&le;\mathrm{nT}\end{array}\right.$

Thereby in (n-1) T＜t≤nT, frequency variation g (t) is if gather (θ _N-1＞0) and (θ _N-1＜0) two kinds of situations show, and following formula is then arranged.

[formula 10]

$g\left(t\right)=\frac{{\mathrm{\&theta;}}_{n-1}}{\left|{\mathrm{\&theta;}}_{n-1}\right|}\&CenterDot;G\&CenterDot;\{U(t-(n-1)T)-U(t-{\mathrm{\&tau;}}_n)\}$

Phase difference θ n in the time of can calculating t=nT with this

[formula 11]

${\mathrm{\&theta;}}_n=\mathrm{\&psi;}\left(\mathrm{nT}\right)$

$=\mathrm{\&theta;}-\frac{{\mathrm{\&theta;}}_{n-1}}{\left|{\mathrm{\&theta;}}_{n-1}\right|}\&CenterDot;\frac{G}{N}.$

$\left[\underset{k=1}{\overset{n-1}{\mathrm{\&Sigma;}}}{\&Integral;}_{(k-1)\&CenterDot;T}^{k\&CenterDot;T}\right[U(t-(k-1)\&CenterDot;T)-U(t-{\mathrm{\&tau;}}_k)\left]\mathrm{dt}\right]$

$-\frac{{\mathrm{\&theta;}}_{n-1}}{\left|{\mathrm{\&theta;}}_{n-1}\right|}\&CenterDot;\frac{G}{N}.$

${\&Integral;}_{(n-1)\&CenterDot;T}^{n\&CenterDot;T}[U(t-(n-1)\&CenterDot;T)-U(t-{\mathrm{\&tau;}}_n)]\mathrm{dt}$

$={\mathrm{\&theta;}}_{n-1}-\frac{{\mathrm{\&theta;}}_{n-1}}{\left|{\mathrm{\&theta;}}_{n-1}\right|}\frac{G}{N}.$

${\&Integral;}_{(n-1)\&CenterDot;T}^{n\&CenterDot;T}[U(t-(n-1)\&CenterDot;T)-U(t-{\mathrm{\&tau;}}_n)]\mathrm{dt}$

If calculate the definite integral of this formula, then consist of

[formula 12]

${\mathrm{\&theta;}}_n=(1-\frac{G\&CenterDot;\mathrm{<figure-callout\; id="2"\; label="T"\; filenames="HSA00000262480700011.png,HSA00000262480700031.png"\; state="\{\{state\}\}">T</figure-callout>}}{2\mathrm{\&pi;}\&CenterDot;N})\&CenterDot;{\mathrm{\&theta;}}_{n-1}$

The recurrent formula of such Geometric Sequence.

Thereby following formula becomes the Mathematical Modeling of the phase difference variation of each cycle T of expression.

[formula 13]

${\mathrm{\&theta;}}_n={(1-\frac{G\&CenterDot;\mathrm{<figure-callout\; id="2"\; label="T"\; filenames="HSA00000262480700011.png,HSA00000262480700031.png"\; state="\{\{state\}\}">T</figure-callout>}}{2\mathrm{\&pi;}\&CenterDot;N})}^n\&CenterDot;\mathrm{\&theta;}$

, the condition of convergence of this ordered series of numbers is the barring condition of the PLL circuit of present embodiment, and

[formula 14]

$0<\frac{G\&CenterDot;T}{\mathrm{\&pi;}\&CenterDot;N}<4$

Must satisfy.

On the contrary, if satisfy above-mentioned condition, then mean no matter initial stage (constantly t=0) phase difference is that what value all must locking.

In addition, hence one can see that, and GT/N π=2 o'clock become phase difference 0 within 1 cycle.

That is, adopt the Mathematical Modeling of present embodiment, when the method for resolving the PLL circuit operation can be provided, can hold the response action for the step phase place input of the PLL circuit of present embodiment, moreover, also so that blocking time be designed to possibility.

As previously discussed, the PLL circuit of present embodiment is characterised in that, be provided with such phase comparator, it is in each cycle of this reference clock signal, carry out the phase bit comparison of reference clock signal and comparison clock signal, generation has high-voltage level, the square-wave signal of 3 values such as low voltage level and reference level, the time width of the time width of the square-wave signal of high-voltage level and the square-wave signal of low voltage level is proportional to phase difference, during without phase difference, the square-wave signal of the square-wave signal of output HIGH voltage level and low voltage level not, and output reference level.

In addition, the PLL circuit is characterised in that, be provided with its frequency of output corresponding to the VCO (voltage-controlled oscillator of the clock signal of the magnitude of voltage of inputting, hereinafter referred to as VCO), with the clock signal as a comparison of the signal behind the clock signal Fractional-N frequency (N is natural number) of above-mentioned VCO output, feed back to above-mentioned phase comparator.

Moreover, the PLL circuit is characterised in that and is provided with such level shifter, this level shifter corresponding to the magnitude of voltage of the magnitude of voltage of the high-voltage level square-wave signal of phase comparator output and low voltage level square-wave signal and reference level magnitude of voltage with level translation to suitable control magnitude of voltage, as the input to VCO.

Like this, the PLL circuit can arrange and have the arbitrarily VCO of voltage-frequency characteristic.

In addition, the PLL circuit will be expressed the Mathematical Modeling of PLL Circuit responce as operation principle with ordered series of numbers.

The possibility of utilizing on the industry

As previously discussed, PLL circuit according to present embodiment, the phase comparator of above-mentioned 3 values output is the type that is called as " phase frequency comparator ", become the comparator of being changed by extensive integrated circuit (IC), if use so general phase comparator, owing to there is no need the phase comparator of design specialized, the PLL circuit of this partial design cost that can be reduced.

And after Phase synchronization was established, input was stable reference level voltage as VCO, and is therefore little as the output frequency change of PLL circuit.

In addition, if the phase place condition of convergence be decided by

[formula 15]

|θ _n|＜ε

(ε is the maximum of allowing phase difference after Phase synchronization is established)

Then from being satisfied with the n of this formula, also can calculate immediately convergence rate is n * T, has kept the advantage of so-called existing PLL circuit.

Moreover in the condition of convergence formula of ordered series of numbers, its convergence range is 2 times of existing PLL circuit, therefore can obtain the PLL circuit that the circuit design degree of freedom enlarges.

Claims (1)

1. a phase-locked loop (PLL) circuit has:

Phase comparator, the phase place of input reference clock signal and comparison clock signal and benchmark clock signal and the phase place of comparison clock signal, generation and output have the square-wave signal corresponding to the predetermined voltage level of the time width of phase difference;

Level shifter, input is from the square-wave signal of described phase comparator output, to carrying out conversion and export square-wave signal from the magnitude of voltage of the square-wave signal of the magnitude of voltage of the square-wave signal of the high-voltage level of described phase comparator output and low voltage level and these three magnitudes of voltage of magnitude of voltage of reference level;

Voltage-controlled oscillator (VCO), input is exported its frequency corresponding to the clock signal of the voltage level of this signal from the signal of described level shifter output;

Frequency divider, will from the clock signal of this voltage-controlled oscillator output signal after by Fractional-N frequency as a comparison clock signal feed back to described phase comparator, N is natural number; It is characterized in that:

Described phase-locked loop circuit satisfies the phase difference of 1 cycle portions of the described reference clock signal condition of convergence as the following ordered series of numbers of 1 unit of measurement, and making the described reference clock signal that is input in the described phase comparator and the phase difference of described comparison clock signal is 0:

θ _n＝(1-((G·T)/(2π·N))) ⁿ·θ

N: natural number

π: circumference ratio

G: corresponding to the constant of the voltage-frequency characteristic of VCO

T: the cycle of oscillation of reference clock signal

N: the divider ratio of frequency divider is natural number

θ: the phase difference in the moment 0

θ _n: the phase difference of moment nT.

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