CN101908510A - Semiconductor device with heat-radiating and packaging structure and manufacturing method thereof - Google Patents
Semiconductor device with heat-radiating and packaging structure and manufacturing method thereof Download PDFInfo
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- CN101908510A CN101908510A CN2009103028633A CN200910302863A CN101908510A CN 101908510 A CN101908510 A CN 101908510A CN 2009103028633 A CN2009103028633 A CN 2009103028633A CN 200910302863 A CN200910302863 A CN 200910302863A CN 101908510 A CN101908510 A CN 101908510A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
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Abstract
The invention relates to a semiconductor device with a heat-radiating and packaging structure and a manufacturing method thereof, and the semiconductor device comprises a layer-adding packaging substrate which is started to manufacture on the basis of a copper core substrate. The layer-adding packaging substrate comprises a thick copper crystal placing bonding pad, a high-density layer-adding circuit and a plurality of electrical pin bonding pads. The thick copper crystal placing bonding pad and the electrical pin bonding pads are integrally formed by the copper core substrate, the layer-adding circuit is formed by the laminated substrate, the layer-adding circuit extends to the periphery by taking the position of the thick copper crystal placing bonding pad as a core so as to provide winding wires required when connecting electronic components, and a plurality of electroplating blind holes are in conduction and connection with the electrical pin bonding pads. Therefore, the semiconductor device can simultaneously have the functions of the thick copper crystal placing bonding pad and the high-density layer-adding circuit, and lead the overall device to improve the reliability and be difficult to separate; furthermore, the semiconductor device has good packaging and good heat radiation effect due to the thick copper crystal placing bonding pad, and the layer-adding circuit can provide the good wire winding capacity.
Description
Technical field:
The present invention relates to semiconductor device of a kind of tool heat-dissipation packaging structure and preparation method thereof, especially refer to a kind of comprise one with copper nuclear substrate be the basis begin to make increase layer package substrate, and have the semiconductor device that layer package substrate, semiconductor chip and a moulding material are formed the tool heat-dissipating gain that increases of complete line road surface and complete pin face by this, but the function of integration base encapsulation (LaminatePackage) and lead frame (Lead Frame Package) encapsulation.
Background technology:
Along with the continuous lifting of semiconductor technology, the chip that semiconductor device carried also tends to running speed and the function that the height integration is desired so that electronic product to be provided, and so this while chip operates the heat that is produced also relatively increases.Be to encapsulate with lead frame traditionally, though above-mentioned use lead frame can obtain better heat radiating effect, only it does not only have the wiring ability of fine-line in the past, more has between structure problems such as connection reliability is not good take place.
In the making of general semiconductor device, traditional heat dissipation path by chip, bind glue, substrate and be passed to the external world to the heat conduction soldered ball of substrate below, the road of not only dispelling the heat is very long, and radiating efficiency is also often not enough, for solving this radiating efficiency problem, the general fin (Heat Spreader) that the good metal material of normal attaching one thermal conductivity is made on the conventional semiconductor device structure, the heat that chip is produced must be passed to fin and dissipation.And the semiconductor device that adopts this kind radiator structure discloses in No. the 7038311st, U.S. Patent Publication communique.As shown in figure 18, the ball grid array (Ball Grid Array, the BGA) encapsulating structure that show the semiconductor device of this exposure.The encapsulating structure 7 of this exposure comprises that haply one is bonded in semiconductor chip 71 on a T shape fin 72 horizontal surfaces 721, by heat-conducting glue 78 and extends through circuit base plate 73, several weld pad 733 and the arrays of solder balls 74 at these circuit base plate 73 second surfaces 732 at these circuit base plate 73 first surfaces 731 of its opening by these T shape fin 72 vertical main bodys 722, and by this semiconductor chip 71 of an encapsulating material 76 pressings, a bonding wire 75 and this circuit base plate 73 first surfaces 731.Can make heat that this semiconductor chip 71 produces be passed to vertical main body 722 and dissipate to outside this encapsulating structure 7 by the horizontal surface 721 of this T shape fin 72.Yet, because the part that the fin 72 of this kind encapsulating structure 7 is connected with circuit base plate 73 only is the corner that these T shape fin 72 both sides T shapes are outstanding, in case vibrations are arranged slightly, promptly easily cause between structure unstable and separate, not only reduce integrally-built reliability, also under the not good situation of structural stability, cause electrical efficient unclear; In addition, because this encapsulating structure 7 is configured with the fin 72 of this T shape for taking radiating efficiency into account, only the assembling of 74 of itself and arrays of solder balls also causes higher cost of manufacture and long shortcomings such as Production Time relatively also because of the T shape structure of this fin 72 causes processing procedure too complicated.So it is required when reality is used that general prior art can't meet the user.
Summary of the invention:
Technical problem to be solved by this invention is: at above-mentioned the deficiencies in the prior art, semiconductor device of a kind of tool heat-dissipation packaging structure and preparation method thereof is provided, but integration base encapsulation and leaded package, and the thick copper of putting below, brilliant position optionally is provided and effectively solves the required of assembly radiating, and required coiling when can the high density build-up circuit providing electronic building brick to link to each other, and effectively improve the conventional substrate heat dissipation problem and can simplify the making flow process of traditional build-up circuit board.
In order to solve the problems of the technologies described above, the technical solution adopted in the present invention is: a kind of semiconductor device of tool heat-dissipation packaging structure, at least comprise that one increases layer package substrate, a semiconductor chip and a moulding material are formed, be characterized in: described increase layer package substrate have at least more than one copper bump and with this copper bump toward around the copper soleplate that extends, those copper bumps and this copper soleplate constitute the copper pedestal, copper bump surface on this copper pedestal is for putting brilliant connection pad zone, copper soleplate on this copper pedestal then comprises first second of reaching with respect to first, go up for first of this copper soleplate and be patterning build-up circuit zone, second of this copper soleplate upward is the hot joining pad, and this hot joining pad is with having several pin pads on one deck; This semiconductor chip contains several I/O connection pads, and this semiconductor chip is bonded in this and increases copper bump surface on the layer package substrate, and is electrically connected to those patterned circuit zones by those I/O connection pads; This moulding material is in order to encapsulate this semiconductor chip and this increases the upper surface of layer package substrate.
A kind of manufacture method of tool heat-dissipation packaging structure, be with a tool complete put brilliant side line road surface and complete pin face increase layer package substrate and semiconductor chip join, and imposing the semiconductor device that moulding material encapsulation constitutes the tool heat-dissipating gain, this manufacture method that increases layer package substrate comprises the following steps: at least
A, provide bronze medal nuclear substrate;
B, remove the thick copper of part of this copper nuclear substrate, and form copper pedestal with copper soleplate and several copper bumps;
C, be core, go up in first of this copper soleplate and form at least one dielectric layer and at least one metal level, and manifest the copper bump on this copper pedestal with the copper bump on this copper pedestal;
D, on this metal level and this dielectric layer, form several openings;
E, form a metal level in these several openings to electrically connect this double-sided substrate and this copper soleplate;
F, remove partly this metal level and form and put brilliant side patterned line layer, and remove the partly copper soleplate of this copper pedestal, and form electrically connection pad of pin zone;
G, form welding resisting layer and barrier layer respectively at this line layer surface and this pin zone; So far, finish the complete high-cooling property of putting brilliant side line road surface and pin face of a tool and increase layer package substrate.
So, have the function of integrating layer multilayer packaging substrate and lead frame, the thick copper of putting below, brilliant position not only optionally is provided and effectively solves the required of assembly radiating, and required coiling when can the high density build-up circuit providing electronic building brick continuous; Simultaneously, has the function that thick copper is put brilliant connection pad and high density build-up circuit, because thick copper is put brilliant connection pad and build-up circuit and is formed by the substrate pressing that copper is examined substrate and tool build-up circuit, the single unit system reliability is high and not easily separated, and then can put brilliant connection pad by thick copper the semiconductor device packages better heat radiating effect is provided, to solve the disappearance of conventional substrate, and can provide good coiling ability by build-up circuit, supplying the deficiency of conventional wires frame encapsulation, and can simplify the making flow process of traditional build-up circuit board.
Description of drawings:
Fig. 1 is the semiconductor device generalized section of a preferred embodiment of the present invention.
Fig. 2 is the making schematic flow sheet of a preferred embodiment of the present invention.
Fig. 3 is the first structural profile schematic diagram of a preferred embodiment of the present invention.
Fig. 4 is the second structural profile schematic diagram of a preferred embodiment of the present invention.
Fig. 5 is the 3rd structural profile schematic diagram of a preferred embodiment of the present invention.
Fig. 6 is the 4th structural profile schematic diagram of a preferred embodiment of the present invention.
Fig. 7 is the 5th structural profile schematic diagram of a preferred embodiment of the present invention.
Fig. 8 is the 6th structural profile schematic diagram of a preferred embodiment of the present invention.
Fig. 9 is the 7th structural profile schematic diagram of a preferred embodiment of the present invention.
Figure 10 is the 8th structural profile schematic diagram of a preferred embodiment of the present invention.
Figure 11 is the 9th structural profile schematic diagram of a preferred embodiment of the present invention.
Figure 12 is the tenth structural profile schematic diagram of a preferred embodiment of the present invention.
Figure 13 is the 11 structural profile schematic diagram of a preferred embodiment of the present invention.
Figure 14 is the 12 structural profile schematic diagram of a preferred embodiment of the present invention.
Figure 15 is the 13 structural profile schematic diagram of a preferred embodiment of the present invention.
Figure 16 is the 14 structural profile schematic diagram of a preferred embodiment of the present invention.
Figure 17 is the 15 structural profile schematic diagram of a preferred embodiment of the present invention.
Figure 18 is a known semiconductor packaging system generalized section.
Label declaration:
Semiconductor device 1 increases layer package substrate 10
Copper nuclear substrate 10a copper pedestal 10b
Build-up circuit substrate 10c copper bump 101
102 first 102a of copper soleplate
Second 102b hot joining pad 103
Moulding material 12 first and second resistance layers 20,21
First opening, 22 first dielectric layers 23
Increase laminar substrate 24 the first metal layers 241
Second dielectric layer, 242 first line layers 243
Second and third opening 25,26 second and third metal levels 27,28
Third and fourth resistance layer 29,30 fourth, fifth openings 31,32
Second and third line layer 33,34 first and second welding resisting layers 35,36
Six, minion mouth 37,38 first and second barrier layers 39,40
Step (A)～(G) 50～56 encapsulating structures 7
Semiconductor chip 71 T shape fin 72
Arrays of solder balls 74 bonding wires 75
Encapsulating material 76 heat-conducting glues 78
Embodiment:
Seeing also shown in Figure 1ly, is the semiconductor device generalized section of a preferred embodiment of the present invention.As shown in the figure: the present invention is semiconductor device of a kind of tool heat-dissipation packaging structure and preparation method thereof, and this semiconductor device 1 comprises that at least one increases layer package substrate 10, semiconductor chip 11 and a moulding material 12 and forms.
This increase layer package substrate 10 have at least more than one copper bump 101 and with this copper bump 101 be core toward around the copper soleplate 102 of extension, those copper bumps 101 and this copper soleplate 102 constitute a bronze medal pedestal 10b, wherein copper bump 101 surfaces on this copper pedestal 10b are to put brilliant connection pad zone, copper soleplate 102 on this copper pedestal 10b then comprises second 102b of one first 102a and with respect to first, it on first 102a of this copper soleplate 102 a patterning build-up circuit (Build up layer) zone, be a hot joining pad 103 on second 102b of this copper soleplate 102, and this hot joining pad 103 is with having several pin pads 104 on one deck.In wherein, second 102b area of this copper soleplate 102 is greater than the area of those copper bumps 101; This hot joining pad 103 can be in order to the radiator structure of ground connection or connection circuit plate; Be coated with a welding resisting layer 39,40 on those patterned circuit zones, hot joining pad 103 and those pin pads 104, and this patterned circuit zone is connected to electroplate buried blind via or through hole with this pin pads 104.
This semiconductor chip 11 contains several I/O (I/O) connection pad, and this semiconductor chip 11 is bonded in this and increases copper bump 101 surfaces on the layer package substrate 10, and is electrically connected to those patterned circuit zones by those I/O connection pads; And this moulding material 12 is in order to encapsulate this semiconductor chip 11 and this increases the upper surface of layer package substrate 10.The above constitutes the semiconductor device 1 of a brand-new and tool heat-dissipating gain.
Seeing also shown in Figure 2ly, is the making schematic flow sheet of a preferred embodiment of the present invention.As shown in the figure: manufacture method of the present invention be with a tool complete put brilliant side line road surface and complete pin face increase layer package substrate and semiconductor chip join, and impose the semiconductor device that moulding material encapsulation constitutes the tool heat-dissipating gain, wherein this manufacture method that increases layer package substrate comprises the following steps: at least
(A) provide copper nuclear substrate 50: bronze medal nuclear substrate is provided, and wherein, this copper nuclear substrate is one not contain the copper coin of dielectric layer material;
(B) form the copper pedestal 51 with copper soleplate and copper bump: remove the thick copper of part of this copper nuclear substrate, and form the copper pedestal with a copper soleplate and several copper bumps, wherein, this copper bump can be formed at the copper soleplate top by etching mode;
(C) form dielectric layer and metal level 52: with the copper bump on this copper pedestal is core, forms at least one dielectric layer and at least one metal level in first mode that goes up with direct pressing of this copper soleplate, and manifests the copper bump on this copper pedestal;
(D) form several openings 53: on this metal level and this dielectric layer, form several openings, wherein, after several openings can be opened copper window (Conformal Mask) earlier, the mode via radium-shine boring formed again, also or in direct radium-shine boring (LASER Direct) mode formed;
(E) electrically connect metal level and copper soleplate 54: with electroless-plating and plating mode form a metal level in those several openings to electrically connect this double-sided substrate and this copper soleplate;
(F) the electrical connection pad 55 of brilliant side patterned line layer and pin zone is put in formation: brilliant side patterned line layer is put in the metal level and the formation that remove part with etching mode, and removes the partly copper soleplate of this copper pedestal, and the regional electrically connection pad of formation pin; And
(G) form welding resisting layer and barrier layer and constitute high-cooling property and increase layer package substrate 56: respectively at this line layer surface and this pin zone formation one welding resisting layer and a barrier layer; So far, finish the complete high-cooling property of putting brilliant side line road surface and pin face of a tool and increase layer package substrate, wherein, this welding resisting layer is the liquid photoresistance of high sensing optical activity of doing with printing, rotary coating or spraying; This barrier layer can be in electronickelling gold, electroless nickel plating gold, electrosilvering or the electrotinning and selects one.
In wherein, above-mentioned this dielectric layer can be epoxy resins insulation film (Ajinomoto Build-up Film, ABE), benzocyclobutene (Benzocyclo-buthene, BCB), two Maleimide triazine resin (BismaleimideTriazine, BT), epoxy resin board (FR4, FR5), polyimides (Polyimide, PI), polytetrafluoroethylene (Poly (tetra-floroethylene), PTFE) or epoxy resin and glass fibre one of form.
As the present invention during in practical operation, in a preferred embodiment, as shown in Figure 1.See also Fig. 3～shown in Figure 17, as shown in the figure: at first provide one not contain the copper coin of dielectric layer material as copper nuclear substrate 10a, and respectively at first first resistance layer 20 that goes up the high photosensitive macromolecular material of fitting of this copper nuclear substrate 10a, and in second second resistance layer 21 that goes up the high photosensitive macromolecular material of fitting of this copper nuclear substrate 10a, and on this first resistance layer 20, form several first openings 22 with the exposure and the mode of developing, to appear its down first of this copper nuclear substrate 10a, this first second then covers fully with this second resistance layer 21 relatively.Then remove the thick copper of part that those first opening, 22 belows have appeared, and remove this first and second resistance layer, make this copper nuclear substrate 10a form copper pedestal 10b with several copper bumps 101 and a copper soleplate 102 to peel off mode with etching mode.In wherein, this first and second resistance layer is the dry film photoresist layer, and the copper pedestal 10b that forms in present embodiment, and the thickness of its copper bump 101 is 200 millimeters (mm), and the thickness of this copper soleplate 102 is 35 millimeters.
To have several copper bumps 101 on this copper pedestal 10b is core, go up with what the pressing mode formed that one first dielectric layer 23 and comprises the first metal layer 241, one second dielectric layer 242 and one first line layer 243 in 102 first 102a of this copper soleplate and to increase laminar substrate 24, and it is in advance by milling cutter several medium altitude grooves that are shaped that this first dielectric layer 23 and this increase laminar substrate 24, can manifest the copper bump 101 on this copper pedestal 10b, and put brilliant connection pad zone usefulness as definition, to increase the chip cooling effect.In wherein, this first line layer 243 that increases laminar substrate 24 is prefabricated by metallic copper institute.
On this first metal layer 241 and this second dielectric layer 242, form several second openings 25 respectively with radium-shine bore mode, and on 102 second 102b of copper soleplate of this copper pedestal 10b and this first dielectric layer 23, form several the 3rd openings 26, afterwards more respectively with electroless-plating and plating mode in those second openings 25, copper bump 101 surfaces that brilliant connection pad zone is put in this first metal layer 241 and conduct form one second metal levels 27, and second formation one the 3rd metal level 28 that in those the 3rd openings 26, reaches this copper pedestal 10b, afterwards respectively at the 3rd resistance layer 29 of the high photosensitive macromolecular material of fitting on this second metal level 27, and the 4th resistance layer 30 of the high photosensitive macromolecular material of on the 3rd metal level 28, fitting, and with exposure and visualization way respectively at forming several the 4th openings 31 on the 3rd resistance layer 29, to appear second metal level 27 under it, and on the 4th resistance layer 30, form several the 5th openings 32, and appear the 3rd metal level 28 on it.Remove second metal level 27 and this first metal layer 241 of those the 4th opening 31 belows afterwards respectively with etching mode, and remove the 3rd metal level 28 of those the 5th opening 32 tops and the copper soleplate 102 of this copper pedestal 10b, at last, remove this third and fourth resistance layer respectively, and form second and third line layer 33,34 respectively.So far, finish one and have the build-up circuit substrate 10c that thick copper is put brilliant connection pad zone.In wherein, this the first～three metal level 241,27,28 is all copper, and this second metal level 27 is as the electric connection usefulness of this first line layer 243 with this second line layer 33, and the 3rd metal level 28 is then used as this first line layer 243 and the electric connection of this tertiary circuit layer 34.
After finishing the making of this build-up circuit substrate 10c, then put the making in brilliant side patterned circuit zone and pin zone.First welding resisting layer of using respectively at these second line layer, 33 surface-coated one deck insulation protections 35; and second welding resisting layer of using in these tertiary circuit layer 34 surface-coated one deck insulation protections 36; and with exposure and visualization way respectively at forming several the 6th openings 37 on this first welding resisting layer 35; to appear the part of its following second line layer 33 as electric connection pad; and on this second welding resisting layer 36, form several minion mouths 38; tertiary circuit layer 34 is as the part of electric connection pad on it to appear, and second 102b by this copper soleplate 102 forms a hot joining pad 103 and several pin pads 104 by this.At last, respectively at formation one first barrier layer 39 on those the 6th openings 37, and on a little minion mouths 38, form one second barrier layer 40.What so far, constitute that integral body of the present invention has complete copper bump 101, copper soleplate 102, hot joining pad 103 and a pin pads 104 of putting brilliant side line road surface and complete pin face increases layer package substrate 10.In wherein, this first and second barrier layer 39,40 is a nickel-gold layer.
Then on putting the copper bump 101 in brilliant connection pad zone, this conduct coheres semiconductor chip 11, and this semiconductor chip 11 and this are increased layer package substrate 10 engage, I/O connection pad and this patterned circuit zone that increases on the layer package substrate 10 on this semiconductor chip 11 are electrically connected.At last, increase layer package substrate 10 upper surfaces with a moulding material 12 these semiconductor chips 11 of encapsulation and this again.So far, finish the semiconductor device 1 (as shown in Figure 1) of a tool heat-dissipating gain.
From the above, the semiconductor device of tool heat-dissipation packaging structure of the present invention, be comprise one with copper nuclear substrate be the basis begin to make increase layer package substrate.This increases layer package substrate (Buildup substrate) and comprises that thick copper puts brilliant connection pad, high density build-up circuit, hot joining pad and several electrical pin pads.In wherein, it is integrally formed by this copper nuclear substrate that this thick copper is put brilliant connection pad, hot joining pad and electrical pin pads, this build-up circuit is then formed by the substrate of pressing, and this build-up circuit be with this thick copper to put brilliant connection pad position be core to around coiling required when providing electronic building brick to link to each other is provided, and electroplate blind holes with several and be connected with the electrical pin pads conducting.Therefore, the characteristic that increases layer package substrate in this semiconductor device is, can have the function that thick copper is put brilliant connection pad and high density build-up circuit simultaneously, and can put brilliant connection pad and build-up circuit system at this thick copper and examine by copper under the substrate pressing of substrate and tool build-up circuit formed, single unit system is reached improve reliability and not easily separated, and then can put brilliant connection pad by thick copper the semiconductor device packages better heat radiating effect is provided, to solve the disappearance of conventional substrate, and can provide good coiling ability by build-up circuit, to supply the deficiency of conventional wires frame encapsulation.
In sum, semiconductor device of a kind of tool heat-dissipation packaging structure of the present invention and preparation method thereof, can effectively improve the various shortcoming of prior art, has the function of integrating layer multilayer packaging substrate and lead frame, the thick copper of putting below, brilliant position not only optionally is provided and effectively solves the required of assembly radiating, and required coiling when can the high density build-up circuit providing electronic building brick to link to each other, can effectively improve the conventional substrate heat dissipation problem by this and reach and simplify the purpose that traditional build-up circuit board is made flow process, and then it is more progressive that the present invention can be produced, more practical, the institute that more meets the user must, really meet the important document of application for a patent for invention, proposed patent application in accordance with the law.
Claims (17)
1. the semiconductor device of a tool heat-dissipation packaging structure, at least comprise that one increases layer package substrate, a semiconductor chip and a moulding material are formed, it is characterized in that: described increase layer package substrate have at least more than one copper bump and with this copper bump toward around the copper soleplate that extends, those copper bumps and this copper soleplate constitute the copper pedestal, copper bump surface on this copper pedestal is for putting brilliant connection pad zone, copper soleplate on this copper pedestal then comprises first second of reaching with respect to first, go up for first of this copper soleplate and be patterning build-up circuit zone, second of this copper soleplate upward is the hot joining pad, and this hot joining pad is with having several pin pads on one deck; This semiconductor chip contains several I/O connection pads, and this semiconductor chip is bonded in this and increases copper bump surface on the layer package substrate, and is electrically connected to those patterned circuit zones by those I/O connection pads; This moulding material is in order to encapsulate this semiconductor chip and this increases the upper surface of layer package substrate.
2. the semiconductor device of tool heat-dissipation packaging structure as claimed in claim 1 is characterized in that: described hot joining pad is in order to ground connection.
3. the semiconductor device of tool heat-dissipation packaging structure as claimed in claim 1 is characterized in that: but the radiator structure of described hot joining pad connection circuit plate.
4. the semiconductor device of tool heat-dissipation packaging structure as claimed in claim 1 is characterized in that: second area of described copper soleplate is greater than the area of those copper bumps.
5. the semiconductor device of tool heat-dissipation packaging structure as claimed in claim 1 is characterized in that: described patterned circuit zone is connected to electroplate buried blind via or through hole with this pin pads.
6. the semiconductor device of tool heat-dissipation packaging structure as claimed in claim 1 is characterized in that: be coated with welding resisting layer on described patterned circuit zone, hot joining pad and those pin pads.
7. the manufacture method of a tool heat-dissipation packaging structure, be with a tool complete put brilliant side line road surface and complete pin face increase layer package substrate and semiconductor chip join, and impose the semiconductor device that moulding material encapsulation constitutes the tool heat-dissipating gain, it is characterized in that: the described manufacture method that increases layer package substrate comprises the following steps: at least
A, provide bronze medal nuclear substrate;
B, remove the thick copper of part of this copper nuclear substrate, and form copper pedestal with copper soleplate and several copper bumps;
C, be core, go up in first of this copper soleplate and form at least one dielectric layer and at least one metal level, and manifest the copper bump on this copper pedestal with the copper bump on this copper pedestal;
D, on this metal level and this dielectric layer, form several openings;
E, form a metal level in these several openings to electrically connect this double-sided substrate and this copper soleplate;
F, remove partly this metal level and form and put brilliant side patterned line layer, and remove the partly copper soleplate of this copper pedestal, and form electrically connection pad of pin zone;
G, form welding resisting layer and barrier layer respectively at this line layer surface and this pin zone; So far, finish the complete high-cooling property of putting brilliant side line road surface and pin face of a tool and increase layer package substrate.
8. the manufacture method of tool heat-dissipation packaging structure as claimed in claim 7 is characterized in that: described copper nuclear substrate is not for containing the copper coin of dielectric layer material.
9. the manufacture method of tool heat-dissipation packaging structure as claimed in claim 7 is characterized in that: the copper bump of described step B is formed at the copper soleplate top by etching mode.
10. the manufacture method of tool heat-dissipation packaging structure as claimed in claim 7 is characterized in that: the part metal level that removes of described step F is formed by etching mode.
11. the manufacture method of tool heat-dissipation packaging structure as claimed in claim 7 is characterized in that: the dielectric layer of described step C and metal level are formed on first of the copper soleplate of this copper pedestal in direct pressing mode.
12. the manufacture method of tool heat-dissipation packaging structure as claimed in claim 7 is characterized in that: described dielectric layer one of is formed by epoxy resins insulation film, benzocyclobutene, two Maleimide triazine resin, epoxy resin board, polyimides, polytetrafluoroethylene or epoxy resin and glass fibre.
13. the manufacture method of tool heat-dissipation packaging structure as claimed in claim 7 is characterized in that: described several openings form via radium-shine bore mode with after opening the copper window earlier again.
14. the manufacture method of tool heat-dissipation packaging structure as claimed in claim 7 is characterized in that: described several openings directly form with radium-shine bore mode.
15. the manufacture method of tool heat-dissipation packaging structure as claimed in claim 7 is characterized in that: the metal level of described step e is formed by electroless-plating and plating mode.
16. the manufacture method of tool heat-dissipation packaging structure as claimed in claim 7 is characterized in that: described welding resisting layer is the liquid photoresistance of the high sensing optical activity of doing with printing, rotary coating or spraying.
17. the manufacture method of tool heat-dissipation packaging structure as claimed in claim 7 is characterized in that: described barrier layer is to select one in electronickelling gold, electroless nickel plating gold, electrosilvering or the electrotinning.
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| CN2009103028633A CN101908510B (en) | 2009-06-03 | 2009-06-03 | Semiconductor device with heat-radiating and packaging structure and manufacturing method thereof |
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| CN2009103028633A CN101908510B (en) | 2009-06-03 | 2009-06-03 | Semiconductor device with heat-radiating and packaging structure and manufacturing method thereof |
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| CN101908510B CN101908510B (en) | 2012-05-09 |
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| CN102629560A (en) * | 2011-02-08 | 2012-08-08 | 旭德科技股份有限公司 | Package carrier and method for manufacturing the same |
| CN104242051B (en) * | 2014-09-18 | 2017-05-10 | 武汉光迅科技股份有限公司 | External cavity tunable laser and cavity mode locking method thereof |
| CN107305871A (en) * | 2016-04-19 | 2017-10-31 | 富士通天株式会社 | Printed wiring board |
| CN111048500A (en) * | 2019-12-17 | 2020-04-21 | 中国电子科技集团公司第三十八研究所 | Integrally packaged radio frequency microsystem assembly |
| TWI753468B (en) * | 2020-06-24 | 2022-01-21 | 欣興電子股份有限公司 | Substrate structure with heat dissipation structure and manufacturing method thereof |
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| US6294731B1 (en) * | 1999-03-16 | 2001-09-25 | Performance Interconnect, Inc. | Apparatus for multichip packaging |
| CN1131553C (en) * | 1999-10-29 | 2003-12-17 | 华通电脑股份有限公司 | Plastic substrate with heat dissipation function for package and its making method |
| CN1331217C (en) * | 2003-11-10 | 2007-08-08 | 乾坤科技股份有限公司 | Wafer package structure and its base plate |
| CN101373760A (en) * | 2007-08-21 | 2009-02-25 | 钰桥半导体股份有限公司 | High heat dissipation memory module structure |
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2009
- 2009-06-03 CN CN2009103028633A patent/CN101908510B/en not_active Expired - Fee Related
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN102610586A (en) * | 2011-01-19 | 2012-07-25 | 旭德科技股份有限公司 | Package carrier |
| CN102629560A (en) * | 2011-02-08 | 2012-08-08 | 旭德科技股份有限公司 | Package carrier and method for manufacturing the same |
| CN102629560B (en) * | 2011-02-08 | 2014-07-23 | 旭德科技股份有限公司 | Package carrier and method for manufacturing the same |
| CN104242051B (en) * | 2014-09-18 | 2017-05-10 | 武汉光迅科技股份有限公司 | External cavity tunable laser and cavity mode locking method thereof |
| US10050406B2 (en) | 2014-09-18 | 2018-08-14 | Accelink Technologies Co., Ltd. | External cavity tunable laser and cavity mode locking method thereof |
| CN107305871A (en) * | 2016-04-19 | 2017-10-31 | 富士通天株式会社 | Printed wiring board |
| CN107305871B (en) * | 2016-04-19 | 2019-12-03 | 富士通天株式会社 | Printed wiring board |
| CN111048500A (en) * | 2019-12-17 | 2020-04-21 | 中国电子科技集团公司第三十八研究所 | Integrally packaged radio frequency microsystem assembly |
| CN111048500B (en) * | 2019-12-17 | 2021-07-09 | 中国电子科技集团公司第三十八研究所 | Integrally packaged radio frequency microsystem assembly |
| TWI753468B (en) * | 2020-06-24 | 2022-01-21 | 欣興電子股份有限公司 | Substrate structure with heat dissipation structure and manufacturing method thereof |
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| Publication number | Publication date |
|---|---|
| CN101908510B (en) | 2012-05-09 |
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