CN101901831A - SCR ESD protection structure with high maintaining voltage - Google Patents
SCR ESD protection structure with high maintaining voltage Download PDFInfo
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- CN101901831A CN101901831A CN 200910233693 CN200910233693A CN101901831A CN 101901831 A CN101901831 A CN 101901831A CN 200910233693 CN200910233693 CN 200910233693 CN 200910233693 A CN200910233693 A CN 200910233693A CN 101901831 A CN101901831 A CN 101901831A
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- type well
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- 239000000758 substrate Substances 0.000 claims abstract description 12
- 238000012423 maintenance Methods 0.000 claims description 7
- 230000001681 protective effect Effects 0.000 claims description 6
- 238000000034 method Methods 0.000 claims description 2
- 230000001105 regulatory effect Effects 0.000 claims 1
- 230000003071 parasitic effect Effects 0.000 description 12
- 238000005516 engineering process Methods 0.000 description 6
- 230000015556 catabolic process Effects 0.000 description 4
- 239000004065 semiconductor Substances 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 238000010276 construction Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 238000002347 injection Methods 0.000 description 2
- 239000007924 injection Substances 0.000 description 2
- 230000024241 parasitism Effects 0.000 description 2
- 239000000969 carrier Substances 0.000 description 1
- 239000012141 concentrate Substances 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 230000018109 developmental process Effects 0.000 description 1
- 230000008713 feedback mechanism Effects 0.000 description 1
- 230000001771 impaired effect Effects 0.000 description 1
- 230000002265 prevention Effects 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 230000008929 regeneration Effects 0.000 description 1
- 238000011069 regeneration method Methods 0.000 description 1
- 229910021332 silicide Inorganic materials 0.000 description 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
- H01L29/87—Thyristor diodes, e.g. Shockley diodes, break-over diodes
Abstract
The invention relates to an electrostatic discharge protection SCR structure with high maintaining voltage, which comprises a P-type substrate, wherein the P substrate is provided with an N-type well region and a P-type well region; the N-type well region and the P-type well region overlap to form another low-doped region; the N-type well is provided with a first N+ doped region and a first P+ doped region; the first N+ doped region and the first P+ doped region are led out through contact holes and are connected together so as to be used as the anode of the device; the P-type well is provided with a second N+ doped region and a second P+ doped region; and the second N+ doped region and the second P+ doped region are led out through contact holes and are connected together so as to be used as the cathode of the device. Thus, the SCR structure is composed of the P+ doped region in the N-type well, the N-type well region and the P-type well region, and the N+ doped region in the P-type well. The low doped region formed by the overlap of the N-type well and the P-type well is utilized to increase the resistance in the maintaining state, thereby increasing the maintaining voltage.
Description
Technical field
The present invention relates to use semiconductor controllable silicon (Semiconductor controlled rectifier; SCR) electrostatic protection of device (electrostatic discharge; ESD), in particular, be the SCR esd protection structure that has high maintenance voltage about a kind of.
Background technology
The continuous development of integrated morphology technology, the characteristic size of integrated morphology reduces gradually,, drain region light dope dark such as short grid length, thin gate oxide, shallow junction but causes internal structure to impact easier temporarily being damaged at electrostatic leakage ESD with advanced technologies such as silicide doping in raising integrated morphology performance and integrated level.According to statistics, annual semi-conductor industry because the economic loss that causes of ESD in multi-million dollar.Therefore, the ESD safeguard structure is set at each I/O port place and just becomes prevention ESD stress one of hurtful effective way of gate oxide.
The purpose of design of esd protection structure is exactly will avoid work structuring to become the discharge path of ESD and damaged, and guaranteeing the ESD that takes place all has suitable low-resistance bypass that the ESD electric current is introduced power line between any two chip pins.This low-resistance bypass is not only wanted to absorb the ESD electric current, also want can the clamper work structuring voltage, prevent work structuring because voltage overload and impaired.This structure path also needs good job stability, can when taking place, ESD respond fast, but also can not be influential to chip operate as normal structure.。In order effectively to protect chip, people to adopt multiple to go up electrostatic-proof protection device in each stage.Protection device construction commonly used has diode, double pole triode, gate grounding NMOS pipe (GGNMOS) and silicon controlled rectifier device (SCR) etc.Utilize SCR for preventing that ESD from being a kind of desirable solution.
SCR is very attractive device for the ESD electrostatic protection; relatively little keeping under the voltage; the regeneration feedback mechanism of itself causes hysteresis characteristic, the power consumption of SCR when this has reduced the esd event generation, and the robustness of SCR goes with GGNMOS than other diode in addition.
When SCR is applied to esd protection, little keep voltage and can bring many problems, particularly power supply clamper structure.This is because when the structure operate as normal, little keep voltage can allow SCR keep the triggering state afterwards at low impedance state, this phenomenon is the breech lock (ESD-inducedlatch up) that esd event causes.Because keep voltage less than supply voltage, it need increase keeps voltage and avoids this risk greater than supply voltage.
In relevant technology, the someone proposes to increase by the distance that increases anode and negative electrode and keeps voltage preventing the generation of breech lock, but can increase size of devices like this.The somebody has proposed to reduce the area of P+ doped region in domain, keep voltage thereby reduce the emission effciency increase, but this has reduced secondary thermal breakdown inefficacy electric current.
Summary of the invention
The object of the present invention is to provide a kind of new E SD protection device construction, and compare with traditional technology, it does not increase extra processing step.ESD safeguard structure with high maintenance voltage of the present invention can also prevent the generation of latch phenomenon.
The present invention is the parasitic controllable silicon SCR structure of a semiconductor, includes:
A P type substrate, on P type substrate, be provided with N type trap and P type trap, N type trap and P trap overlap mutually and form overlapping region, the one a N+ doped region and a P+ doped region are arranged in the N trap, the one a N+ doped region and a P+ doped region are drawn by contact hole and are linked together, and as the anode of device, the 2nd N+ doped region and the 2nd P+ doped region are arranged in the P trap, the 2nd N+ doped region and the 2nd P+ doped region link together by contact hole, as the negative electrode of device.
N trap and P trap make the concentration step-down in the zone of mutual overlapping owing to overlap and impurity compensation mutually, and the resistance of total like this resistance ratio original structure increases, and keeps voltage thereby increased.
ESD safeguard structure of the present invention has good ESD protective capacities on the one hand, on the other hand, can exempt the low contingent latch-up of voltage of keeping again.
Description of drawings
Fig. 1 is the generalized section of traditional SCR structure;
Fig. 2 is the equivalent circuit diagram of traditional SCR structure shown in Figure 1;
Fig. 3 is the volt-ampere characteristics of figure of traditional SCR structure shown in Figure 1;
Fig. 4 is the generalized section of ESD safeguard structure of the present invention;
Reference numeral, label declaration:
10,40～P type substrate
11,41～N well area
12,22～P well area
13,15,43,45～N+ doped region
14,16,44,46～P+ doped region
The overlapping region of 48～N well area and P well area
Embodiment
Fig. 1 is the generalized section of traditional side direction SCR.This is one and is manufactured on two trap devices on the P type substrate 10, on substrate 10 is N type trap 11 and P type trap 12, and N type trap 11 is connected with P+ doped region 14 by N+ doped region 13, as the anode of SCR, P type trap 12 is connected with P+ doped region 16 by N+ doped region 15, as the negative electrode of SCR; P+ doped region 14, N type trap 11, P type trap 12, and N+ doped region 15 has constituted the structure of PNPN.
Fig. 2 is the equivalent circuit diagram of structure shown in Figure 1, and it contains the PNP pipe Q1 of a parasitism and the NPN pipe Q2 of a parasitism, N trap resistance 20 and P trap resistance 21.
In traditional CMOS technology, PNP pipe Q1 and NPN pipe Q2 are parasitic components, the emitter of parasitic PNP pipe Q1, and collector electrode, base stage is respectively by P+ doped region 14, N trap 11, P type trap 12 is formed; The emitter of parasitic NPN pipe Q2, collector electrode, base stage is respectively by N+ doped region 15, P type trap 12, N type trap 11 is formed; The collector electrode of parasitic PNP pipe Q1 is connected with the base stage of parasitic NPN pipe Q2, is connected with resistance 21 then, and wherein resistance 21 is the resistance that is formed by P type trap 12; Emitter and the PAD end of parasitic PNP pipe Q1 are coupled; The base stage of parasitic PNP pipe Q1 and the collector electrode of parasitic NPN pipe Q2 are connected, and are connected with resistance 20 then, and wherein resistance 20 is the resistance that is formed by N type trap 11.
When the pressure reduction between anode and the negative electrode less than the device cut-in voltage time, the anti-reverse current of PN junction partially of N type trap 11 and 12 one-tenth of P type traps is released by " anode-13-N trap 11-P trap 12-P+ injection region, N+ injection region 15-negative electrode " passage.This moment, the flow through pressure drop deficiency of N trap resistance 20 and P trap resistance 21 of reverse current reached the cut-in voltage of parasitic PNP pipe Q1 and NPN pipe Q2.Therefore, before unlatching, the equivalence of SCR device is the resistance that resistance is high.
When the voltage difference between anode and the negative electrode arrived cut-in voltage, N trap resistance 20 or 21 pressure drops of P trap resistance had reached PNP pipe Q1 cut-in voltage, so PNP pipe Q1 opens.The unlatching of PNP pipe Q1 can make the electric current of the P trap resistance 21 of flowing through increase, and NPN pipe Q2 pressure drop has immediately also reached the cut-in voltage value.The unlatching of NPN pipe Q2 has increased the electric current of the N trap resistance 20 of flowing through again conversely.This is that a final PNP pipe Q1 of positive feedback process and NPN pipe Q2 can enter the saturation region, voltage between pad port and the Vss port can be clamped at Vsatp+Vsatn+Vav wherein, Vsatp is the saturation voltage drop of PNP pipe Q1, Vsatn is the saturation voltage drop of NPN pipe Q2, Vav is the saturation voltage drop of snowslide resistance, therefore has a tangible negative resistance to return stagnant phenomenon as can be seen from Figure 3.
When the SCR device enters after negative resistance goes back to the territory, dead zone, along with the continuation that adds esd pulse voltage increases, the current value of device increases thereupon.The reverse PN junction avalanche breakdown that this moment, N trap 11 and P trap 12 formed, the equivalence of SCR device is one " a snowslide resistance " that resistance is very low.When the electric current of the SCR device of flowing through reaches certain value, the tie region that N trap 11 and P trap 12 form can produce a lot of hot carriers, the generation of hot carrier has aggravated gathering of electric current, so power can more and more concentrate on this zone, the temperature of this regional area also can sharply rise, the SCR device can enter the second breakdown state, and second breakdown is the inefficacy damage of irrecoverable property.
When keeping voltage when very little, structure has the danger that breech lock takes place under normal operation.Keeping voltage is parasitic PNP pipe, voltage sum on parasitic NPN pipe and the snowslide resistance.In order to obtain the high voltage of keeping, must increase the resistance of keeping under the state.
Fig. 4 is the generalized section of ESD safeguard structure of the present invention.
This is one and is manufactured on two trap devices on the P type substrate 40, on P type substrate substrate 40 is N type trap 41 and P type trap 42, N type trap 41 and P type trap 42 have a fraction of mutual overlapping region 48, N type trap 41 is connected with P+ doped region 44 by N+ doped region 43, anode as SCR, P type trap 42 is connected with P+ doped region 46 by N+ doped region 45, as the negative electrode of SCR; P+ doped region 44, N type trap 41, P type trap 42, and N+ doped region 45 has constituted the structure of PNPN.
Claims (4)
1. electrostatic discharge protective SCR structure with high maintenance voltage, be formed on the device, described device comprises: P type substrate (40), on described P type substrate (40), be provided with N type trap (41) and P type trap (42), described N type trap (41) and described P type trap (42) overlap mutually and form overlapping region (48), in described N type trap (41), be provided with N+ doped region (43) and P+ doped region (44), described N+ doped region (43) and described P+ doped region (44) are drawn by contact hole and are linked together, anode as described device, in described P type trap (42), be provided with N+ doped region (45) and P+ doped region (46), described N+ doped region (45) and described P+ doped region (46) are drawn by contact hole and are linked together, negative electrode as described device is characterized in that: described electrostatic discharge protective SCR structure is by P+ doped region (44), N type trap (41), P type trap (42), overlapping region (48) and N+ doped region (45) are formed.
2. the electrostatic discharge protective SCR structure with high maintenance voltage according to claim 1 is characterized in that, described overlapping region (48) is overlapped mutually in technical process by described N type trap (41) and described P type trap (42) and forms.
3. the electrostatic discharge protective SCR structure with high maintenance voltage according to claim 1 is characterized in that the concentration of described overlapping region (48) is less than the concentration of described N type trap (41) and described P type trap (42).
4. the electrostatic discharge protective SCR structure with high maintenance voltage according to claim 1 is characterized in that, the described magnitude of voltage of keeping can be adjusted by the size of regulating described overlapping region (48).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200910233693 CN101901831A (en) | 2009-10-28 | 2009-10-28 | SCR ESD protection structure with high maintaining voltage |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200910233693 CN101901831A (en) | 2009-10-28 | 2009-10-28 | SCR ESD protection structure with high maintaining voltage |
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| CN101901831A true CN101901831A (en) | 2010-12-01 |
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| CN 200910233693 Pending CN101901831A (en) | 2009-10-28 | 2009-10-28 | SCR ESD protection structure with high maintaining voltage |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103460356A (en) * | 2011-01-05 | 2013-12-18 | 英飞凌科技双极有限责任合伙公司 | Method for producing a semiconductor component comprising an integrated lateral resistor |
| CN112103333A (en) * | 2020-11-19 | 2020-12-18 | 晶芯成(北京)科技有限公司 | Semiconductor structure and manufacturing method thereof |
-
2009
- 2009-10-28 CN CN 200910233693 patent/CN101901831A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103460356A (en) * | 2011-01-05 | 2013-12-18 | 英飞凌科技双极有限责任合伙公司 | Method for producing a semiconductor component comprising an integrated lateral resistor |
| CN103460356B (en) * | 2011-01-05 | 2017-02-15 | 英飞凌科技双极有限责任合伙公司 | Method for producing a semiconductor component comprising an integrated lateral resistor |
| CN112103333A (en) * | 2020-11-19 | 2020-12-18 | 晶芯成(北京)科技有限公司 | Semiconductor structure and manufacturing method thereof |
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Open date: 20101201 |