CN101894790A - Preparation method of semiconductor chip - Google Patents
Preparation method of semiconductor chip Download PDFInfo
- Publication number
- CN101894790A CN101894790A CN2009100276877A CN200910027687A CN101894790A CN 101894790 A CN101894790 A CN 101894790A CN 2009100276877 A CN2009100276877 A CN 2009100276877A CN 200910027687 A CN200910027687 A CN 200910027687A CN 101894790 A CN101894790 A CN 101894790A
- Authority
- CN
- China
- Prior art keywords
- titanium
- aluminium
- etched
- forms
- silicon chip
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Images
Abstract
The invention discloses a preparation method of a semiconductor chip. The method comprises the following steps: forming an oxide film on a silicon wafer, coating photoresist on the silicon wafer with the oxide film, using a mask to etch a circuit pattern on the silicon wafer with photoresist, etching to remove the residual photoresist and oxide film on the surface of the silicon wafer, forming elements required by the wafer through ion implantation, and forming metal wires on the silicon wafer, wherein the step of forming metal wires on the silicon wafer comprises the following steps: depositing metal aluminum on the surface of the wafer and etching metal aluminum to form the layout of wires. In the step of forming metal wires, when aluminum is etched, a mixed gas containing nitrogen is used as etching gas, the by-products of the reaction are less and a thermally stable film is formed, thus protecting the aluminum side wall, reducing the path of electron transfer and lowering the probability of electron transfer.
Description
[technical field]
The invention relates to a kind of semiconductor making method,, thereby can change the method for semiconductor chip metal connecting line electron transfer performance particularly about a kind of improvement semiconductor alloy line engraving method.
[background technology]
Electron transfer (EM) phenomenon is a kind of because the bump of electron stream makes metallic atom produce the effect of displacement.When passing through big electric current in the plain conductor, electrostatic field force drives electronics and is moved by the negative electrode anode, the electronics of high-speed motion and metallic atom generation energy exchange, atom is subjected to fierce electron bombardment power (being so-called electronics wind-force), but metallic atom is also received reciprocal electrostatic field force simultaneously, when the current density in the plain conductor was higher, a large amount of electron collision atoms of anode motion made electronics wind-force that metallic atom is subjected to greater than electrostatic field force.Therefore metallic atom is subjected to the driving of electronics wind-force, makes it from the directed diffusion of negative electrode anode, thereby electromigration takes place.
The inner employing of integrated circuit (IC) chip (IC) metallic film goes between and conducts operating current, and the metallic film of this conduction current is called interconnecting line.Along with the raising of chip integration, it is thinner, narrower, thinner that interconnecting line becomes, and therefore current density wherein is increasing.As previously mentioned, under higher current density effect, the metallic atom in the interconnecting line will move along the electron motion direction.The atom that is shifted may produce prominent mound and prominent palpus on the surface of interconnecting line when interconnecting line one end is assembled, the prominent mound of these outside projections and prominent palpus make easily between adjacent two interconnecting lines and produce short circuit.In addition, metallic atom displacement back produces the hole in the original place, move to the opposite direction of atom in the hole, gathers, when the hole is assembled mutually and formed the cavity, the sectional area of the current path of interconnecting line reduces, and the resistance of interconnecting line is increased, and current density increases, thus the local temperature that forms interconnecting line increases, cause interconnecting line to blow, cause and open circuit.
Therefore in the manufacture process of IC, require usually IC is carried out the electron transfer test, if IC is short-circuited in the electron transfer test or time of opening circuit less than the stipulated time, electron transfer test crash then.
The material that is used to form interconnecting line is generally aluminum metal, and the step that forms the aluminium line is carried out etching to the aluminium film, to form required lead-in wire Butut then normally earlier at semi-conductor silicon chip surface deposition aluminium.When al deposition, aluminium inside is to exist with a lot of metallic particles, and the easiest granule boundary place that occurs in particle and particle boundary of electron transfer, when al deposition, the particle that forms is big more, then the intersection of particle is just few more, and the path of electron transfer is just few more, and the probability that electron transfer takes place is low more.
In the existing technology, normally adopt fluoroform (CHF3) the aluminium film to be etched with the aluminum metal line that produces required form as etching gas.But fluoroform is during as etching gas, the accessory substance that produces during reaction is more, sidewall at the aluminum metal line can form heavier polymer, and contained fluorine ion can produce erosion to aluminum metal in these polymer, cause the original granule boundary of aluminium sidewall destroyed, and form the more particles border, so the path of electron transfer can increase, the probability that electron transfer takes place correspondingly increases, and causes the electron transfer test crash easily.
And prior art mainly solves by the thickness of regulating titanium or titanium nitride when the electron transfer test crash takes place, but effect is not purchased obviously.Perhaps solve, but cost is very high by using ion injection titanium to replace traditional physical vapour deposition (PVD) titanium.
Therefore, a kind of new solution of necessary proposition is to overcome the aforementioned disadvantages of prior art.
[summary of the invention]
The object of the present invention is to provide a kind of manufacture method of semiconductor chip, can improve the electron transfer performance of chip with lower cost.
Another object of the present invention is to provide a kind of metal connecting line engraving method that can promote semiconductor chip electron transfer performance.
For reaching aforementioned purpose, the manufacture method of a kind of semiconductor chip of the present invention, it is included in the step that forms oxide-film on the silicon chip, the step of coating photoresist on silicon chip, on silicon chip, scribe the step of circuitous pattern by mask, remove the step of the unnecessary material of silicon chip surface by etching, be infused in the step that silicon chip forms the step of the required element of wafer and form metal connecting line on silicon chip by ion, be included in the step of plated metal aluminium on the silicon chip surface and the step that metallic aluminium is etched with the formation metal connecting line in the step that forms metal connecting line on the silicon chip, wherein in the step that metallic aluminium is etched with the formation metal connecting line of aforementioned formation metal connecting line, it is the mixed gas that comprises nitrogen that metallic aluminium is carried out etched gas.
For reaching aforementioned another purpose, a kind of semiconductor alloy line of the present invention engraving method, it is included in the step of plated metal aluminium on the semi-conductor silicon chip and metallic aluminium is etched with the step that forms metal connecting line; Wherein aforementioned metallic aluminium is carried out in the etched step, it is the mixed gas that comprises nitrogen that metallic aluminium is carried out etched gas.
Compared with prior art; manufacturing method for semiconductor chips of the present invention; what wherein the metallic aluminium line is carried out that etching uses is the mixed gas that comprises nitrogen; the accessory substance that produces during reaction is less; and its polymer that is covered in aluminium line surface does not contain the fluorine ion that easily the aluminium line is caused erosion; aluminium-silicon-titanium in opposite nitrogen ion and the silicon chip forms high strength, heat-staple film; protection to the aluminium sidewall can be provided; and original granule boundary in the maintenance aluminium line; reduce the path of electron transfer, reduce the probability that electron transfer takes place.
[description of drawings]
Fig. 1 is the flow chart of manufacturing method for semiconductor chips of the present invention.
Fig. 2 forms the flow chart of the step of metal connecting line at silicon chip surface for the present invention.
Fig. 3 forms the flow chart of the step of plated metal aluminium in the metal connecting line step for the present invention.
Fig. 4 forms the flow chart that in the metal connecting line step metallic aluminium is carried out etched step for the present invention.
[embodiment]
In view of the step of other steps of semiconductor making method of the present invention and conventional semiconductor manufacturing method of chip basic identical, and these steps are not inventive point of the present invention place, therefore other steps (for example growing steps such as crystalline substance, cutting) of semiconductor making method are not described in detail one by one in this specification, and only enumerate some main indispensable steps in the semiconductor making method.
See also shown in Figure 1ly, it shows the flow chart of manufacturing method for semiconductor chips of the present invention.As shown in the figure, a kind of manufacturing method for semiconductor chips of the present invention, it comprises the steps:
Step 1: the step that at first on silicon chip surface, forms the layer of even thin oxide film;
Step 2: be coated with photoresist on the silicon chip of oxide-film equably and make silicon chip have photosensitive step being formed with then;
Step 3: follow by light source irradiation on prefabricated mask, be amplified in the step of scribing circuitous pattern on the silicon chip through lens;
Step 4: remove the unnecessary photoresist of silicon chip surface and the step of oxide-film by etching, wherein etching can be wet etching or dry etching, wherein the concrete steps of dry etching will be for putting into reative cell through the silicon chip of photoetching, feeding reacting gas, gas and silicon chip surface are reacted, etch away unwanted photoresist and oxide-film.
Step 5: be infused in the step that silicon chip forms the required element of wafer by ion,, silicon chip implemented ion inject, make part exposed on the silicon chip become semiconductor, and form the needed element of semiconductor chip by modes such as oxide-diffused or sputters.
Step 6: on silicon chip, form the step of metal connecting line, after forming the required element of semiconductor chip, need to form the layer of metal line, the circuit structure of each element on the silicon chip by design in advance interconnected.Usually the material of metal connecting line employing is aluminium or copper.This metal connecting line of Xing Chenging is an aluminum steel in embodiments of the present invention.
As shown in Figure 2, the concrete steps of formation metal connecting line further comprise on silicon chip:
Carry out the step 62 that etching forms metal connecting line in the step 61 of silicon chip surface plated metal aluminium and to metallic aluminium.
Wherein in the step 61 of silicon chip surface plated metal aluminium, it further comprises:
Step 611: form one deck first titanium, titanium nitride layer earlier at silicon chip surface
Step 612: the silicon chip that will be formed with first titanium, titanium nitride layer is put into reative cell, and the plasma ambient intermediate ion stream bombardment aluminium target material at inert gas is splashed to silicon chip surface, precipitates into the aluminum metal film that metal connecting line is used on first titanium, titanium nitride layer.
Step 613: form one deck second titanium, titanium nitride layer again on aluminum metal film surface.
The aluminum metal film is carried out etching, further comprises with the step 62 that forms metal connecting line:
Step 621: the step that forms the metal connecting line Butut at the silicon chip surface that is formed with second titanium, titanium nitride by mask lithography;
Step 622: the silicon chip that will be formed with the metal connecting line Butut is put into reative cell, feeds the mixed gas of being made up of nitrogen, chlorine and boron chloride, second titanium, titanium nitride layer and metallic aluminium is etched with the step that forms metal connecting line.
Be familiar with the person skilled in art and should be appreciated that, because the manufacture process of semiconductor chip is carrying out repeatedly of multilayer technology, so abovementioned steps 1 to step 5 can repeat according to the needs that form the different layers structure.
Manufacturing method for semiconductor chips of the present invention; what use when wherein the aluminum metal film being carried out etching is the mixed gas that comprises nitrogen; the accessory substance that produces during reaction is less; and its polymer that is covered in aluminum metal line surface does not contain the fluorine ion that easily the aluminium line is caused erosion; aluminium-silicon-titanium in opposite nitrogen ion and the silicon chip forms high strength, heat-staple film; protection to the aluminium sidewall can be provided; and original granule boundary in the maintenance aluminium line; reduce the path of electron transfer, reduce the probability that electron transfer takes place.
Claims (10)
1. the manufacture method of a semiconductor chip, the step of coating photoresist on the silicon chip that forms oxide-film, scribbling the step of scribing circuitous pattern on the silicon chip of photoresist by mask, remove the step of unnecessary photoresist of silicon chip surface and oxide-film by etching, be infused in the step that silicon chip forms the step of the required element of wafer and form metal connecting line on silicon chip by ion, wherein be included in the step of plated metal aluminium on the silicon chip surface and the step that metallic aluminium is etched with the formation metal connecting line in the step that forms metal connecting line on the silicon chip, it is characterized in that: metallic aluminium being etched with in the step that forms metal connecting line of aforementioned formation metal connecting line, it is the mixed gas that comprises nitrogen that metallic aluminium is carried out etched gas.
2. manufacturing method for semiconductor chips as claimed in claim 1 is characterized in that: the aforementioned mixed gas that comprises nitrogen is the mixed gas that nitrogen, chlorine and boron chloride are formed.
3. manufacturing method for semiconductor chips as claimed in claim 1, it is characterized in that: aforementioned on silicon face the step of plated metal aluminium also be included in silicon face and form earlier one deck first titanium, titanium nitride layer, plated metal aluminium on first titanium, titanium nitride layer, and the step that on the metallic aluminium of deposition, forms one deck second titanium, titanium nitride layer more then.
4. manufacturing method for semiconductor chips as claimed in claim 3 is characterized in that: aforementionedly metallic aluminium is etched with the step that forms metal connecting line further comprises the step that forms the line Butut by photoetching on the surface of second titanium, titanium nitride layer.
5. manufacturing method for semiconductor chips as claimed in claim 4 is characterized in that: aforementionedly metallic aluminium is etched with the step that forms metal connecting line comprises that also feeding the mixed gas that comprises nitrogen carries out etched step to second titanium, titanium nitride layer and metallic aluminium.
6. semiconductor alloy line engraving method, it is included in the step of plated metal aluminium on the semi-conductor silicon chip and metallic aluminium is etched with the step that forms metal connecting line; It is characterized in that: aforementioned metallic aluminium is carried out in the etched step, it is the mixed gas that comprises nitrogen that metallic aluminium is carried out etched gas.
7. semiconductor alloy line engraving method as claimed in claim 6 is characterized in that: the aforementioned mixed gas that comprises nitrogen is the mixed gas that nitrogen, chlorine and boron chloride are formed.
8. semiconductor alloy line engraving method as claimed in claim 6, it is characterized in that: aforementioned on silicon chip the step of plated metal aluminium also be included in silicon face and form earlier one deck first titanium, titanium nitride layer, plated metal aluminium on first titanium, titanium nitride layer, and the step that on the metallic aluminium of deposition, forms one deck second titanium, titanium nitride layer more then.
9. semiconductor alloy line engraving method as claimed in claim 8 is characterized in that: aforementionedly metallic aluminium is etched with the step that forms metal connecting line further comprises the step that forms the line Butut by photoetching on the surface of second titanium, titanium nitride layer.
10. semiconductor alloy line engraving method as claimed in claim 9 is characterized in that: aforementionedly metallic aluminium is etched with the step that forms metal connecting line comprises that also feeding the mixed gas that comprises nitrogen carries out etched step to second titanium, titanium nitride layer and metallic aluminium.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2009100276877A CN101894790A (en) | 2009-05-18 | 2009-05-18 | Preparation method of semiconductor chip |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2009100276877A CN101894790A (en) | 2009-05-18 | 2009-05-18 | Preparation method of semiconductor chip |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN101894790A true CN101894790A (en) | 2010-11-24 |
Family
ID=43103938
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2009100276877A Pending CN101894790A (en) | 2009-05-18 | 2009-05-18 | Preparation method of semiconductor chip |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN101894790A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108919407A (en) * | 2018-07-11 | 2018-11-30 | 京东方科技集团股份有限公司 | The preparation method and wire grid polarizer of metal wire and wire grating, electronic device |
-
2009
- 2009-05-18 CN CN2009100276877A patent/CN101894790A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108919407A (en) * | 2018-07-11 | 2018-11-30 | 京东方科技集团股份有限公司 | The preparation method and wire grid polarizer of metal wire and wire grating, electronic device |
| WO2020010838A1 (en) * | 2018-07-11 | 2020-01-16 | 京东方科技集团股份有限公司 | Method for preparing metal wire and method for preparing metal wire grid, and wire grid polarizer and electronic apparatus |
| US11619773B2 (en) | 2018-07-11 | 2023-04-04 | Boe Technology Group Co., Ltd. | Method of manufacturing metal wire and metal wire grid, wire grid polarizer, electronic device |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR100376955B1 (en) | Electromigration-resistant metallization for interconnecting microcircuits with RF reactive sputtered titanium tungsten and gold | |
| US9607895B2 (en) | Silicon via with amorphous silicon layer and fabrication method thereof | |
| TW201532299A (en) | Solar cell emitter region fabrication with differentiated P-type and N-type region architectures | |
| US9385031B2 (en) | Method for providing a self-aligned pad protection in a semiconductor device | |
| US20170236801A1 (en) | Semiconductor devices and processing methods | |
| KR20180123169A (en) | Metallization of solar cells with differentiated P-type and N-type region architectures | |
| US6573181B1 (en) | Method of forming contact structures using nitrogen trifluoride preclean etch process and a titanium chemical vapor deposition step | |
| KR20170132224A (en) | Polycrystalline Silicon for Blisterless Solar Cells | |
| US7202168B2 (en) | Method of producing semiconductor device | |
| CN101894790A (en) | Preparation method of semiconductor chip | |
| US5985750A (en) | Manufacturing method of semiconductor device | |
| JP5672329B2 (en) | Switching element | |
| KR20190082152A (en) | Chemical polishing of solar cell surfaces and the resulting structures | |
| CN109671668A (en) | A kind of manufacturing method of semiconductor devices | |
| CN102044478B (en) | Method for making metal plug | |
| CN103295917B (en) | The manufacture method of a kind of aluminium welding pad | |
| US7625819B2 (en) | Interconnection process | |
| CN102881637B (en) | Back end of line processing of semiconductor circuits System and method for | |
| JP5277524B2 (en) | Switching element | |
| KR100714039B1 (en) | Method for fabrication a semiconductor device | |
| KR100532748B1 (en) | Method for manufacturing metal layer in semiconductor device | |
| JP2004134617A (en) | Method for manufacturing wiring, semiconductor device, and its manufacturing process | |
| KR100990934B1 (en) | Method for forming via hole using damascene process | |
| KR100296710B1 (en) | Method of manufacturing a diamond vacuum microelectronic device | |
| KR101458038B1 (en) | Semiconductor structure with interconnect comprising silver and mehod of forming the same |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| ASS | Succession or assignment of patent right |
Free format text: FORMER OWNER: WUXI HUARUN SHANGHUA TECHNOLOGY CO., LTD. Effective date: 20120312 |
|
| C41 | Transfer of patent application or patent right or utility model | ||
| COR | Change of bibliographic data |
Free format text: CORRECT: ADDRESS; FROM: 214061 WUXI, JIANGSU PROVINCE TO: 214028 WUXI, JIANGSU PROVINCE |
|
| TA01 | Transfer of patent application right |
Effective date of registration: 20120312 Address after: 214028 Wuxi provincial high tech Industrial Development Zone, Hanjiang Road, No. 5, Jiangsu, China Applicant after: Wuxi CSMC Semiconductor Co., Ltd. Address before: 214061 No. 5 Hanjiang Road, national hi tech Industrial Development Zone, Wuxi, Jiangsu, China Applicant before: Wuxi CSMC Semiconductor Co., Ltd. Co-applicant before: Wuxi Huarun Shanghua Technology Co., Ltd. |
|
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C02 | Deemed withdrawal of patent application after publication (patent law 2001) | ||
| WD01 | Invention patent application deemed withdrawn after publication |
Application publication date: 20101124 |