CN101882605B - Chip packaging structure - Google Patents
Chip packaging structure Download PDFInfo
- Publication number
- CN101882605B CN101882605B CN 200910137114 CN200910137114A CN101882605B CN 101882605 B CN101882605 B CN 101882605B CN 200910137114 CN200910137114 CN 200910137114 CN 200910137114 A CN200910137114 A CN 200910137114A CN 101882605 B CN101882605 B CN 101882605B
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- Prior art keywords
- substrate
- chip
- packaging structure
- disposed
- solder ball
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
Landscapes
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
Abstract
The invention discloses a chip packaging structure, comprising a first substrate, a chip, a second substrate, a third substrate, a plurality of electrically conductive protrusions, a plurality of leads and a packaging colloid. The chip is configured on the first substrate. The second substrate is configured on the chip and includes a lead joint face towards the direction away from the chip. The third substrate is configured on the second substrate and includes a solder ball mounting face towards the direction away from the chip. The electrically conductive protrusions are configured between the second substrate and the third substrate so as to electrically connect the second substrate with the third substrate. The second substrate is connected with the first substrate via the leads. The packaging colloid is configured on the first substrate, covers the chip, the leads, the second substrate and the third substrate, and is exposed from the solder ball mounting face of the third substrate.
Description
Technical field
The invention relates to a kind of chip-packaging structure, but and particularly relevant for a kind of chip-packaging structure of laminated components.
Background technology
The purpose of chip encapsulation technology provides and gives the enough signal paths of chip, heat dissipation path and structural defence.Known technology proposes a kind of encapsulation stacking, and (it can reduce the shared in the circuit board area of these chip-packaging structures by the mode that a plurality of chip-packaging structures are piled up each other for package-on-package, 3D packaged type POP).
Fig. 1 illustrates known a kind of generalized section that can be applicable to the chip-packaging structure of encapsulation stacking.Please with reference to Fig. 1, a chip 110 of chip-packaging structure 100 is disposed on one first substrate 120, and one second substrate 130 is disposed on the chip 110.Second substrate 130 is electrically connected by many first leads 140 and first substrate 120, and chip 110 is electrically connected by many second leads 150 and first substrate 120.
In detail, first lead 140 is a surface 132 and first substrates 120 away from the direction of chip 110 that connect second substrate 130, and the first therefore local lead 140 is to be positioned on surperficial 132.In addition, second substrate 130 has a plurality of solder ball connecting pad 134 that are positioned at surface 132, and it is suitable for engaging with a plurality of soldered balls (not illustrating) of another element respectively.One packing colloid 160 is disposed on first substrate 120, and coating chip 110, second substrate 130, first lead 140 and second lead 150, and packing colloid 160 has a depression 162 to expose these solder ball connecting pad 134.
Yet,, therefore, need to use the mould of particular design could form packing colloid 160, and this will increase the cost of mould because packing colloid 160 need have depression 162.
Summary of the invention
The present invention proposes a kind of chip-packaging structure, and the die cost of making this chip-packaging structure is lower.
The present invention proposes a kind of chip-packaging structure and comprises one first substrate, a chip, one second substrate, one the 3rd substrate, a plurality of conductive projection, many first leads and a packing colloid.Chip configuration and electrically connects with first substrate on first substrate.Second substrate is disposed on the chip, and has the lead joint face away from the chip direction, and lead joint face has a first area and a second area that is positioned at the outside, first area.The 3rd substrate is disposed on second substrate, and the projection of the 3rd substrate on lead joint face overlap with the first area, and the 3rd substrate has the solder ball mounting face away from the chip direction.Conductive projection is disposed between second substrate and the 3rd substrate, to electrically connect second substrate to the, three substrates.First lead connects second area to the first substrate, to electrically connect second substrate to the first substrate.Packing colloid is disposed on first substrate, and coating chip, first lead, second substrate and the 3rd substrate, and packing colloid exposes the solder ball mounting face of the 3rd substrate.
In one embodiment of this invention, lead joint face with respect to the height of first substrate less than the height of solder ball mounting face with respect to first substrate.
In one embodiment of this invention, first lead with respect to the maximum height of first substrate less than the height of solder ball mounting face with respect to first substrate.
In one embodiment of this invention, solder ball mounting face and packing colloid the surface trim in fact.
In one embodiment of this invention, chip-packaging structure also comprises an insulating barrier, and it is disposed between second substrate and the 3rd substrate, and conductive projection runs through insulating barrier.
In one embodiment of this invention, the material of insulating barrier comprises a cohesive material or a packing colloid.
In one embodiment of this invention, chip-packaging structure also comprises many second leads, and it connects chip to the first substrate, to electrically connect chip to the first substrate.
In one embodiment of this invention, chip-packaging structure also comprises an adhesion coating, and it is disposed between second substrate and the chip.
In one embodiment of this invention, adhesion coating coats the part of each second lead.
In one embodiment of this invention, chip-packaging structure also comprises a distance piece, and it is disposed between second substrate and the chip.
In sum, because the present invention adopts the mode of additional configuration 1 the 3rd substrate on second substrate, make packing colloid of the present invention need not have the solder ball mounting face that depression can expose the 3rd substrate, so can reduce die cost.
Description of drawings
For letting above-mentioned and further feature of the present invention and the advantage can be more obviously understandable, the special act of hereinafter embodiment, and conjunction with figs. elaborate as follows, wherein:
Fig. 1 illustrates known a kind of generalized section that can be applicable to the chip-packaging structure of encapsulation stacking.
Fig. 2 illustrates the generalized section of the chip-packaging structure of one embodiment of the invention.
Fig. 3 illustrates the generalized section of the chip-packaging structure of another embodiment of the present invention.
Fig. 4 illustrates the generalized section of the chip-packaging structure of further embodiment of this invention.
Embodiment
Fig. 2 illustrates the generalized section of the chip-packaging structure of one embodiment of the invention.Please with reference to Fig. 2, the chip-packaging structure 200 of present embodiment comprises one first substrate 210, a chip 220, one second substrate 230, one the 3rd substrate 240, a plurality of conductive projection 250, many first leads 260 and a packing colloid 270.
In addition, in the present embodiment,,, can between second substrate 230 and chip 220, dispose a distance piece S so that on chip 220, carry out routing technology for increasing the spacing of the chip 220 and second substrate 230.Distance piece S can be a blank chip (dummy die) or the material piece of a thermal coefficient of expansion (CTE) between the chip 220 and second substrate 230.
The 3rd substrate 240 is disposed on second substrate 230, and the 3rd projection of substrate 240 on lead joint face 232 overlaps with first area 232a.The 3rd substrate 240 can be electrically connected to second substrate 230 through these conductive projections 250, and wherein these conductive projections 250 are to be disposed between second substrate 230 and the 3rd substrate 240.It should be noted that; Second substrate 230, the 3rd substrate 240 and these conductive projections 250 can constitute a substrate stacked structure; And chip 220 can be electrically connected to the substrate stacked structure through first substrate 210, and can electrically connect through substrate stacked structure and extraneous (for example other chip-packaging structure).Second substrate 230 and the 3rd substrate 240 in the substrate stacked structure all can be a transit line plate.
The 3rd substrate 240 has the solder ball mounting face 242 away from chip 220 directions.In the present embodiment because second substrate 230 is to be disposed between first substrate 210 and the 3rd substrate 240, so lead joint face 232 with respect to the height H 1 of first substrate 210 less than the height H 2 of solder ball mounting face 242 with respect to first substrate 210.Because first lead 260 is to be connected to lead joint face 232, thus the maximum height H3 of first lead 260 can be reduced with respect to first substrate 210, so that it is less than the height H 2 of solder ball mounting face 242 with respect to first substrate 210.In addition, the 3rd substrate 240 also can have a plurality of solder ball connecting pad 244 that are positioned at solder ball mounting face 242, and it is suitable for engaging with soldered ball (not illustrating).
In the present embodiment, can between second substrate 230 and the 3rd substrate 240, dispose an insulating barrier I, and these conductive projections 250 run through insulating barrier I.The material of insulating barrier I comprises filler gum.
Fig. 3 illustrates the generalized section of the chip-packaging structure of another embodiment of the present invention.Please with reference to Fig. 3, the chip-packaging structure 300 of present embodiment is similar with the chip-packaging structure 200 of Fig. 2.Being in the chip 220 of chip-packaging structure 300 of both difference is to be electrically connected to first substrate 210 through a plurality of conductive projections 310 between the chip 220 and first substrate 210, and chip-packaging structure 300 does not have the distance piece S of Fig. 2.
Fig. 4 illustrates the generalized section of the chip-packaging structure of further embodiment of this invention.Please with reference to Fig. 4, the chip-packaging structure 400 of present embodiment is similar with the chip-packaging structure 200 of Fig. 2.Both difference parts are that chip-packaging structure 400 does not have the distance piece S of Fig. 2, and have an adhesion coating 410, and it is disposed between second substrate 230 and the chip 220, and adhesion coating 410 coats the part of these second leads 280.
In sum, because the present invention adopts the mode of additional configuration 1 the 3rd substrate on second substrate, make packing colloid of the present invention need not have the solder ball mounting face that depression can expose the 3rd substrate, so can reduce die cost.
Though the present invention discloses as above with embodiment; Right its is not in order to limit the present invention; Has common knowledge the knowledgeable in the field under any; Do not breaking away from the spirit and scope of the present invention, when can doing a little change and retouching, so protection scope of the present invention is when looking being as the criterion that the claim scope defined.
Claims (11)
1. chip-packaging structure comprises:
One first substrate;
One chip is disposed on this first substrate, and electrically connects with this first substrate;
One second substrate is disposed on this chip, and has the lead joint face away from this chip direction, and this lead joint face has a first area and a second area that is positioned at this outside, first area;
One the 3rd substrate is disposed on this second substrate, and the projection of the 3rd substrate on this lead joint face overlap with this first area, and the 3rd substrate has the solder ball mounting face away from this chip direction;
A plurality of conductive projections are disposed between this second substrate and the 3rd substrate, to electrically connect this second substrate to the 3rd substrate;
Many first leads connect this second area to this first substrate, to electrically connect this second substrate to this first substrate; And
One packing colloid is disposed on this first substrate, and coats this chip, said first lead, this second substrate and the 3rd substrate, and this packing colloid exposes this solder ball mounting face of the 3rd substrate.
2. chip-packaging structure as claimed in claim 1, wherein this lead joint face with respect to the height of this first substrate less than the height of this solder ball mounting face with respect to this first substrate.
3. chip-packaging structure as claimed in claim 1, wherein said first lead with respect to the maximum height of this first substrate less than the height of this solder ball mounting face with respect to this first substrate.
4. chip-packaging structure as claimed in claim 1, wherein this solder ball mounting face and this packing colloid the surface trim.
5. chip-packaging structure as claimed in claim 1 also comprises:
One insulating barrier be disposed between this second substrate and the 3rd substrate, and said conductive projection runs through this insulating barrier.
6. chip-packaging structure as claimed in claim 5, wherein the material of this insulating barrier comprises a cohesive material.
7. chip-packaging structure as claimed in claim 6, wherein this cohesive material is a packing colloid.
8. chip-packaging structure as claimed in claim 1 also comprises:
Many second leads connect this chip to this first substrate, to electrically connect this chip to this first substrate.
9. chip-packaging structure as claimed in claim 8 also comprises:
One adhesion coating is disposed between this second substrate and this chip.
10. chip-packaging structure as claimed in claim 9, wherein this adhesion coating coats the respectively part of this second lead.
11. chip-packaging structure as claimed in claim 9 also comprises:
One distance piece is disposed between this second substrate and this chip.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200910137114 CN101882605B (en) | 2009-05-07 | 2009-05-07 | Chip packaging structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200910137114 CN101882605B (en) | 2009-05-07 | 2009-05-07 | Chip packaging structure |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN101882605A CN101882605A (en) | 2010-11-10 |
| CN101882605B true CN101882605B (en) | 2012-07-04 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 200910137114 Active CN101882605B (en) | 2009-05-07 | 2009-05-07 | Chip packaging structure |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN101882605B (en) |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1191393A (en) * | 1997-02-17 | 1998-08-26 | 精工爱普生株式会社 | Tape carrier and tape carrier device using the same |
| JP2004087882A (en) * | 2002-08-28 | 2004-03-18 | Sanyo Electric Co Ltd | Semiconductor device |
| CN1519930A (en) * | 2003-02-06 | 2004-08-11 | ������������ʽ���� | Semiconductor device, electronic appts. their mfg. methods and electronic instrument |
| CN2743971Y (en) * | 2004-11-15 | 2005-11-30 | 力成科技股份有限公司 | Spherical grid matrix packaging structure |
-
2009
- 2009-05-07 CN CN 200910137114 patent/CN101882605B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1191393A (en) * | 1997-02-17 | 1998-08-26 | 精工爱普生株式会社 | Tape carrier and tape carrier device using the same |
| JP2004087882A (en) * | 2002-08-28 | 2004-03-18 | Sanyo Electric Co Ltd | Semiconductor device |
| CN1519930A (en) * | 2003-02-06 | 2004-08-11 | ������������ʽ���� | Semiconductor device, electronic appts. their mfg. methods and electronic instrument |
| CN2743971Y (en) * | 2004-11-15 | 2005-11-30 | 力成科技股份有限公司 | Spherical grid matrix packaging structure |
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| Publication number | Publication date |
|---|---|
| CN101882605A (en) | 2010-11-10 |
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