CN101872318A - Data access method for flash memory, its storage system and controller - Google Patents

Abstract

The invention relates to a data access method for a flash memory, a storage system and a controller thereof, wherein the data access method is used for accessing data in the flash memory, and the data has at least one sub-data. The data access method includes generating an error correction code for data to be written, and writing the data to be written and the generated error correction code into a flash memory. In addition, the data access method also includes generating a corresponding bit check code for each sub-data of the data, and writing the generated bit check code into the flash memory. By the scheme, when the sub-data is read from the flash memory, whether the read sub-data has the error bit or not is judged according to the bit check unit corresponding to the read sub-data, so that the data access speed is improved.

Description

Data access method for flash memory, its storage system and controller

technical field

The invention relates to a data access method for flash memory, a flash memory storage system and a flash memory controller using the method.

Background technique

The rapid growth of digital cameras, mobile phones and MP3 players in recent years has led to a rapid increase in consumers' demand for digital content storage. Due to the characteristics of non-volatile data, power saving, small size and no mechanical structure, Flash Memory is suitable for users to carry as a storage medium for digital file transmission and exchange. Solid State Drive (SSD) is an example of using flash memory as a storage medium, and has been widely used as a main hard disk in computer host systems.

When accessing data in a flash memory storage system that uses flash memory as a storage medium, the flash memory storage system will perform an error correction process through an error correction circuit to verify whether the accessed data is correct . Specifically, when the user intends to write data into the flash memory storage system, the system will generate an error correction code for the data and write the data to be written and the generated error correction code into the flash memory middle. Later, when the user wants to read the data, the system will read the data and its error correction code from the flash memory and check and correct the read data according to the read error correction code, thus ensuring The correctness of the information read. In particular, the error correction circuits and error correction codes vary according to different correction capabilities. That is to say, lower-order error correction circuits and error correction codes can only check and correct fewer error bits, while higher-order error correction circuits and error correction codes can check and correct more error bits. The storage space required for storing the higher order error correction codes is greater than the storage space required for storing the lower order error correction codes.

In the design of the flash memory storage system, generally speaking, the flash memory of the flash memory storage system includes a plurality of physical blocks (physical blocks), and each physical block has a plurality of pages (pages). , and the data is written into the flash memory in units of pages. Each page is composed of a data bit area and a redundant bit area. The data bit area is used to store the data to be written, and the redundant bit area is used to store the control information and error correction code related to this page ( Error Correction Code, ECC). For example, when a page is configured with 1 sector (i.e., 512 bytes), the data byte area of this page will be configured with 512 bytes and the redundant byte area will be configured with 16 bytes To configure, in which 6 bytes in the redundant byte area are used to store the control information of this page and 10 bytes are used to store the error correction code for this page, that is to say, 10 bits One set is enough to store an error correction code corresponding to 512 bytes of data.

With the development of flash memory technology, the capacity of each page continues to increase. For example, a flash memory with 4 sectors (ie, 2048 bytes) per page has been developed. As the number of bytes that can be stored in a page increases, the correction capability of the error correction code for this page also needs to be improved, so as to effectively ensure the correctness of the data in the page. Therefore, in a page that configures the data byte area with 2048 bytes, the redundant byte area will be configured with 61 bytes, of which 8 bytes are used to store control information and 53 bytes are used to store Error correction code corresponding to 2048 bytes of data.

Generally speaking, a computer system accesses data in units of sectors. Therefore, in the example of a flash memory storage system in which a page of a flash memory consists of 4 sectors, since the error correction code in the page is based on The data of 4 sectors is generated, so even if the computer system only reads the data of 1 sector in this page, the flash memory storage system still has to read the complete data in this page (that is, 4 sector data) and perform error correction procedures with their corresponding error correction codes. Based on this, in an example where a computer system reads a small amount of data, this access method will seriously affect the access speed of the flash memory storage system.

Contents of the invention

An object of the present invention is to provide a data access method, which can effectively increase the speed of reading data in a flash memory.

Another object of the present invention is to provide a flash memory controller, which can effectively increase the speed of reading data in the flash memory.

Another object of the present invention is to provide a flash memory storage system, which can effectively increase the speed of reading data in the flash memory.

To achieve the above object, the present invention provides a data access method for accessing a data in a flash memory. The data access method includes receiving data from a host system, wherein the received data includes multiple sub-data. The data access method also includes generating an error correction code (Error Correction Code, ECC) for the received data, and writing the received data and the generated ECC into the flash memory. Moreover, the data access method also includes generating a corresponding one-bit check code for each sub-data, and writing the generated one-bit check code into the flash memory.

In order to achieve the above object, the present invention also proposes a flash memory controller for accessing a data in a flash memory, the flash memory controller includes a microprocessor unit and is connected to the microprocessor The host interface unit of the unit, the flash memory interface unit, the memory operation unit, the error correction unit and the bit checking unit. The host interface unit is used for connecting a host system and receiving data from the host system, wherein the received data includes multiple sub-data. The flash memory interface unit is used for connecting the flash memory. The error correction unit is used to generate an error correction code for the received data, wherein the memory operation unit writes the received data and the generated error correction code into the flash memory. The bit check unit is used to generate a bit check code for each sub-data, and the memory operation unit writes the generated bit check code into the flash memory.

The invention provides a flash memory storage system, which includes a flash memory and a flash memory controller connected to the flash memory. The flash memory controller is used to receive a data with a plurality of sub-data from a host system, the flash memory controller will generate an error correction code for the received data, and combine the received data with the generated error The correction code is written into the flash memory. In addition, the flash memory controller generates a bit check code for each sub-data, and writes the generated bit check code into the flash memory.

It can be seen from the above technical solution that when the host system wants to read less than one page of small data, it only needs to check whether there is an access error bit for the small data to be read without reading the data in the entire page. Data and their error correction codes, thereby increasing the speed of data access.

In order to make the above-mentioned features and advantages of the present invention more comprehensible, the following specific embodiments are described in detail in conjunction with the accompanying drawings.

Description of drawings

FIG. 1 is a schematic block diagram of a flash memory storage system according to an exemplary embodiment of the present invention;

FIG. 2 is a schematic block diagram of a physical block according to an exemplary embodiment of the present invention;

FIG. 3 is a flow chart of the steps of writing data according to this exemplary embodiment;

FIG. 4 is a schematic diagram of a data flow of a writing example according to an exemplary embodiment of the present invention;

FIG. 5 is an example of storing a bit check code table in a physical block according to an exemplary embodiment of the present invention;

FIG. 6 is a flow chart of data reading steps according to this exemplary embodiment.

Explanation of symbols of main components in the drawings

110: flash memory controller; 110a: microprocessor unit;

110b: memory operation unit; 110c: flash memory interface unit;

110d: host interface unit; 110e: error correction unit;

110f: bit checking unit; 120: flash memory chip;

120-0～120-N: physical block; D: data bit area;

R: redundant bit area; 400: bit check code table;

S301, S303, S305, S307, S309: data writing steps;

S601, S603, S605, S607, S609, S611, S613, S615, S617, S619, S621: data reading steps.

Detailed ways

FIG. 1 is a schematic block diagram of a flash memory storage system according to an exemplary embodiment of the present invention.

Please refer to FIG. 1 , usually the flash memory storage system 100 is used together with the host system 200, so that the host system 200 can write data into the flash memory storage system 100 or read data from the flash memory storage system 100 . In this exemplary embodiment, the flash memory storage system 100 is a solid state drive (SSD). But it must be understood that in another embodiment of the present invention, the flash memory storage system 100 can also be a memory card or a flash drive.

The flash memory storage system 100 includes a flash memory controller 110 and a flash memory chip 120 .

The flash memory controller 110 executes a plurality of logic gates or control instructions designed in hardware or firmware, and writes, reads, and executes data in the flash memory chip 120 according to the instructions of the host system 200. Erase and other operations. The flash memory controller 110 includes a microprocessor unit 110a, a memory operation unit 110b, a flash memory interface unit 110c, a host interface unit 110d, an error correction unit 110e and a bit checking unit 110f.

The microprocessor unit 110a is used for controlling the overall operation of the flash memory controller 110 . Specifically, the microprocessor unit 110a works together with the memory operation unit 110b, the flash memory interface unit 110c, the host interface unit 110d, the error correction unit 110e and the bit checking unit 110f to implement a flash memory storage system. 100 operations such as writing, reading, and erasing.

The memory operation unit 110b is connected to the microprocessor unit 110a, and is used to execute the block management mechanism. In particular, the memory operation unit 110b is used to implement the data access mechanism according to this exemplary embodiment.

In this embodiment, the memory operation unit 110b is designed in the controller 110 in the form of firmware. For example, burning a plurality of control instructions into a program memory (for example, read only memory (Read Only Memory, ROM)) and embedding this program memory in the flash memory controller 110 to design The memory operation unit 110b, wherein when the flash memory storage system 100 starts, a plurality of machine instructions of the memory operation unit 110b will be executed by the microprocessor unit 110a to complete the block management mechanism and the block management mechanism according to the embodiment of the present invention Data writing mechanism.

In another embodiment of the present invention, the control instructions of the memory operation unit 110 b can also be stored in a specific area of the flash memory chip 120 in the form of software. Likewise, when the flash memory storage system 100 starts up, the control instructions of the memory operation unit 110b will be executed by the microprocessor unit 110a. In addition, in another embodiment of the present invention, the memory operation unit 110 b can also be designed in a hardware form in the flash memory controller 110 .

The flash memory interface unit 110 c is connected to the microprocessor unit 110 a and used for accessing the flash memory chip 120 . That is to say, the data to be written into the flash memory chip 120 will be converted into a format acceptable to the flash memory chip 120 through the flash memory interface unit 110c.

The host interface unit 110 d is connected to the microprocessor unit 110 a and is used for receiving and identifying instructions sent by the host system 200 . That is to say, the commands and data sent by the host system 200 will be sent to the microprocessor unit 110a through the host interface unit 110d. In this exemplary embodiment, the host interface unit 110d is a SATA interface. However, it must be understood that the present invention is not limited thereto, and the host interface unit 110d can also be a USB interface, IEEE 1394 interface, PCIExpress interface, MS interface, MMC interface, SD interface, CF interface, IDE interface or other suitable data transmission interface .

The error correction unit 110e is connected to the microprocessor unit 110a and configured to execute an error correction procedure. Specifically, when a data is input in the error correction unit 110e, the error correction unit 110e will generate an error correction code according to the data, and when a data and an error correction code are input in the error correction unit 110e, the error correction unit 110e will The 110e performs error checking and correction for the received data according to the received error correction code. The error correction process is a common technique in data storage media, and will not be described in detail here. It is worth mentioning that the error correction capability of the error correction unit 110 e must be able to support the specification of the flash memory chip 120 . In this exemplary embodiment, the error correction unit 110e has a capability of checking and correcting 48 error bits. However, it must be understood that the present invention is not limited thereto, and any error correction unit that can support the specification of the flash memory chip 120 can be applied to the present invention.

The bit checking unit 110f is connected to the microprocessor unit 110a and is used to execute an error detection program. Specifically, when a data is input in the bit checking unit 110f, the bit checking unit 110f will generate a bit checking code according to the data, and when a data and a bit checking code are input in the bit checking unit 110f , the bit checking unit 110f performs error checking on the received data according to the received bit checking code. For example, in this exemplary embodiment, the bit checking unit 110f is designed with an error detecting circuit, and the bit checking unit 110f generates an error detection code as the bit checking code. However, in another embodiment of the present invention, the bit checking unit 110f can also be designed as a cyclic redundancy check circuit (cyclic redundancy check circuit), and the bit checking unit 110f can generate a cyclic redundancy check (cyclic redundancy check) code as a bitcheck code. Alternatively, in another embodiment of the present invention, the bit checking unit 110f can also be designed as a low-order error correcting circuit, and the bit checking unit 110f will generate a low-order error correction code as the bit checking code, Here, the low-order error correction circuit and the low-order error correction code refer to the error correction circuit and the error correction code with lower error correction capability than the error correction unit 110 e and its error correction code.

In addition, although not shown in this exemplary embodiment, the flash memory controller 110 also includes common functional modules such as a buffer memory and a power management unit for controlling the flash memory.

The flash memory chip 120 is connected to the flash memory controller 110 and has a plurality of physical blocks 120-0˜120-N for storing data. In this exemplary embodiment, the flash memory chip 120 is a multi-level memory cell (Multi Level Cell, MLC) NAND flash memory. However, it must be understood that the present invention is not limited thereto. In another embodiment of the present invention, a single level memory unit (Single Level Cell, SLC) NAND flash memory can also be applied to the present invention.

FIG. 2 is a schematic block diagram of a physical block according to an exemplary embodiment of the present invention. In this exemplary embodiment, the structure of each physical block 120 - 1 ~ 120 -N is the same, and the schematic block diagram of FIG. 2 is applicable to each physical block 120 - 0 ~ 120 -N.

Referring to FIG. 2, the physical block includes 128 pages, and each page can store data of 4 sectors. Specifically, the data bit area D of each page is 2048 bytes, and the redundant bit area R of each page is 61 bytes, wherein 8 bytes in the redundant bit area R are used It stores control information associated with the page and 53 bytes are used to store the error correction code for the page.

FIG. 3 is a flow chart of data writing steps according to this exemplary embodiment.

Referring to FIG. 2 and FIG. 3 , when the host system 200 intends to write data to the flash memory storage system 100 , in step S301 , the flash memory controller 110 receives the data to be written from the host system 200 . In this exemplary embodiment, the received data has at least one sub-data, and the size of the multiple sub-data is the smallest access unit (ie, sector) of the host system 200 . For example, when the access unit of the host system 200 is 512 bytes, the size of the subdata is also 512 bytes. Specifically, the flash memory controller 110 receives a write command and sub-data corresponding to the write command from the host system 200 through the host interface unit 110d.

Next, in step S303, the flash memory controller 110 generates corresponding error correction codes for the received data. Specifically, the data received by the host interface unit 110d will be sent to the error correction unit 110e, and the error correction unit 110e will generate a corresponding error correction code.

After that, in step S305, the memory operation unit 110b of the flash memory controller 110 writes the data to be written and its corresponding error correction code into the flash memory chip 120 through the flash memory interface unit 110c In the physical blocks 120-0 to 120-N of .

Then, in step S307, the flash memory controller 110 generates a corresponding bit check code for each sub-data. Specifically, each sub-data is sent to the bit checking unit 110f, and the bit checking unit 110f generates a corresponding bit checking code for each sub-data.

Finally, in step S309, the memory operation unit 110b writes the generated bit check code into the physical blocks 120-0˜120N of the flash memory chip 120 through the flash memory interface unit 110c. It is worth mentioning that since the redundant bit area is only enough to store the error correction code corresponding to the data when writing data in the page, the bit check code corresponding to the sub-data generated in this exemplary embodiment will be stored in another in the data bit area of a physical block. That is to say, the memory operation unit 110 b regards the plurality of bit check codes as general data and writes them into the flash memory chip 120 . It is worth mentioning that, in the exemplary embodiment of the present invention, the memory operation unit 110b creates a checksum table 400 to record the generated checksum.

FIG. 4 is a schematic diagram of a data flow of a writing example according to an exemplary embodiment of the present invention.

Referring to FIG. 4 , if the flash memory controller 110 receives data DATA with a data volume of 2048 bytes from the host system 200 , the flash memory controller 110 will generate an error correction code ECC for the data DATA. In addition, the flash memory controller 110 divides the data DATA into sub-data DATA1, sub-data DATA2, sub-data DATA3, and sub-data DATA4, and sequentially generates the corresponding bit check code BCC1, bit check code BCC2, bit Check code BCC3 and bit check code BCC4. Afterwards, the data DATA composed of the sub-data DATA1 , the sub-data DATA2 , the sub-data DATA3 and the sub-data DATA4 are written into page 0 of the physical block 120 - 0 with the error correction code ECC. At the same time, the flash memory controller 110 writes the check code table 400 recording the check code BCC1, the check code BCC2, the check code BCC3 and the check code BCC4 into the physical block 120. -N in page 0.

FIG. 5 is an example of storing a checksum table in a physical block according to an exemplary embodiment of the present invention.

Referring to FIG. 2 and FIG. 5 , for example, the bit check code table 400 recording the bit check codes of the physical blocks 120 - 0 - 120 - 127 is stored in the physical block 120 -N. In this exemplary embodiment, since the sub-data is 512 bytes and the storage space required for the bit check code of each sub-data is 4 bytes, one physical block can store corresponding 128 physical blocks The bitcheck code for . In particular, since the memory operation unit 110b stores the check code table 400 in the form of storing general data, the redundant bit area of the physical block stores the error correction code corresponding to the check code. In addition, in another exemplary embodiment of the present invention, the memory operation unit 110b will establish a bit check code mapping table to record the corresponding relationship between the bit check code and the sub-data in the bit check code table, thereby In order to facilitate reading the bit check code of the corresponding sub-data from the bit check code table.

It is worth mentioning that since the bit check code table 400 for all physical blocks in the flash memory chip 120 will require a large storage space, in another exemplary embodiment of the present invention, the memory operation unit 110b The checksum table 400 is only established for physical blocks that are often accessed by reading small data (ie, data volume less than one page). For example, the host system 200 often reads small data in the physical block storing the File Allocation Table (FAT), thereby reducing the memory space required for storing the checksum table 400 .

In addition, since the check code table 400 will be continuously updated during the access process, the check code table 400 will be loaded from the flash memory chip 120 during the operation of the flash memory storage system 100 The buffer memory (not shown) is used for updating, and when the flash memory storage system 100 is shut down, the checksum table 400 will be written back to the flash memory chip 120 .

FIG. 6 is a flow chart of data reading steps according to this exemplary embodiment. Please refer to FIG. 2, FIG. 5 and FIG. 6, when the host system 200 wants to read data from the flash memory storage system 100, in step S601, the flash memory controller 110 will determine that the host system 200 wants to read Whether the amount of data is less than 1 page. Specifically, the flash memory controller 110 will receive the read command from the host system 200 through the host interface unit 110d, and the memory operation unit 110b will determine the host computer according to the address to be read in the read command. Whether the amount of data to be read by the system 200 is less than 1 page.

For example, in the example where the page 0 of the physical block 120-0 stores data DATA composed of sub-data DATA1, sub-data DATA2, sub-data DATA3 and sub-data DATA4, if the host system 200 only wants to read the sub-data When DATA1 , sub-data DATA2 , sub-data DATA3 , and sub-data DATA4 are part of rather than the entire data DATA, it means that the amount of data to be read by the host system 200 is less than one page.

If it is determined in step S601 that the amount of data to be read by the host system 200 is not less than 1 page, then in step S603 the memory operation unit 110b will read from the flash memory chip 120 through the flash memory interface unit 110c. The data and the corresponding error correction code are read, and in step S605 the error correction unit 110e executes the error correction procedure according to the read data and the error correction code. After that, in step S607, the memory operation unit 110b transmits the data of the executed error correction program to the host system 200 through the host interface unit 110d. For example, if the host system 200 intends to read the data DATA of page 0 of the physical block 120-0, the flash memory controller 110 will read the data DATA and its error correction code ECC, and execute the error correction procedure, and then The data DATA on which the error correction procedure has been executed is sent to the host system 200 .

If it is determined in step S601 that the amount of data to be read by the host system 200 is less than 1 page, then in step S609 the memory operation unit 110b will read from the flash memory chip 120 through the flash memory interface unit 110c. Read the sub-data to be read, and in step S611, the memory operation unit 110b will obtain the corresponding bit check code from the bit check code table 400, wherein if the bit check code table 400 is not loaded into the buffer memory When memory (not shown), the memory operation unit 110 b reads the bit checksum table 400 from the flash memory chip 120 .

Afterwards, in step S613, the bit checking unit 110f determines whether there is an error bit in the read sub-data according to the read sub-data and the corresponding bit check code. If there is no error bit in the read sub-data, the memory operation unit 110b transmits the read sub-data to the host system 200 in step S615.

If there is an error bit in the read sub-data, then in step S617, the complete data and its corresponding error correction code will be read from the flash memory chip 120 through the flash memory interface unit 110c, And in step S619, the error correction unit 110e executes an error correction procedure according to the read data and the error correction code. Finally, in step S621 , the memory operation unit 110 b obtains the sub-data to be read by the host system 200 from the corrected data and transmits the obtained sub-data to the host system 200 .

For example, if the host system 200 wants to read the sub-data DATA1 of page 0 of the physical block 120-0, the flash memory controller 110 will read the sub-data DATA1 and the bit check code BCC1, and according to the bit check code The BCC1 judges whether there is an error bit in the read sub-data DATA1. If there is no error bit in the read sub-data DATA1 , the flash memory controller 110 will directly transmit the read sub-data DATA1 to the host system 200 . Conversely, if there is an error bit in the read sub-data DATA1, the flash memory controller 110 will re-read the data DATA and its error correction code ECC from the flash memory chip 120, and execute the error bit. Correction procedure, and then obtain the sub-data DATA1 from the data DATA on which the error correction procedure has been executed and transmit the acquired sub-data DATA1 to the host system 200 .

It should be understood that the execution sequence shown in FIG. 3 and FIG. 6 does not limit the present invention, and those skilled in the art may perform the above steps in a sequence different from that shown in FIG. 3 and FIG. 6 according to the spirit of the present invention.

To sum up, the present invention divides the access unit of the data corresponding to the host system into several sub-data when writing data in the page of the flash memory, and generates a one-bit check code for each data, thus when When the host system reads subdata from a page of flash memory, it can perform bit checking through the corresponding bit check code, and only when a bit error occurs, it reads the entire page from flash memory. Error correction is performed on the data, thereby increasing the read speed of the flash memory.

Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and not to limit them. Although the present invention has been described in detail with reference to the preferred embodiments, those of ordinary skill in the art should understand that: it still Modifications or equivalent replacements can be made to the technical solutions of the present invention, and these modifications or equivalent replacements cannot make the modified technical solutions deviate from the spirit and scope of the technical solutions of the present invention.

Claims (25)

1. a data access method is characterized in that, is used in a fast flash memory bank access one data, and described data access method comprises:

Receive described data from a host computer system, wherein said data comprises a plurality of sub-data;

For described data produces an error-correcting code;

Described data and described error-correcting code are write in the described fast flash memory bank;

For each described a plurality of sub-data produces a corresponding bit check code, to generate a plurality of bit check codes of corresponding described a plurality of sub-data; And

Described a plurality of bit check codes are write in the described fast flash memory bank.

2. data access method according to claim 1, it is characterized in that, comprise that also setting up a bit checks code table and check the described a plurality of bit check codes of record in the code table at described bit, wherein described a plurality of bit check codes are write step in the described fast flash memory bank and comprise described bit inspection code table is write in the described fast flash memory bank.

3. data access method according to claim 2 is characterized in that, comprises that also setting up a bit check code mapping table checks that to write down described bit the mapping between a plurality of bit check codes described in the code table and the described a plurality of sub-data concerns.

4. data access method according to claim 2, it is characterized in that, comprise that also being written into described bit from described fast flash memory bank checks in code table to a buffer memory, and from described buffer memory, read described a plurality of bit check codes of corresponding described a plurality of sub-data.

5. data access method according to claim 1 is characterized in that, also comprises:

From described fast flash memory bank, read described a plurality of sub-data;

From described fast flash memory bank, read the bit check code of the corresponding described a plurality of sub-data that read;

Judge according to the bit check code of the described a plurality of sub-data that read whether the described a plurality of sub-data that read have mistake,

Wherein working as the described a plurality of sub-data that read does not have when having mistake, gives described host computer system with the described a plurality of sub-data transmissions that read.

6. data access method according to claim 5 is characterized in that, when the described a plurality of sub-data that read had mistake, then described data access method also comprised:

From described fast flash memory bank, read described data and described error-correcting code;

Proofread and correct the described data that is read according to the described error-correcting code that is read;

From the described data of being proofreaied and correct, obtain described a plurality of sub-data of having proofreaied and correct; And

Give described host computer system with described a plurality of sub-data transmissions of having proofreaied and correct.

7. data access method according to claim 1 is characterized in that, each described a plurality of bit check code is an error detection sign indicating number or a Cyclical Redundancy Check sign indicating number.

8. data access method according to claim 1 is characterized in that, the size of each described a plurality of sub-data is a minimum access unit of described host computer system.

9. a fast-flash memory body controller is characterized in that, in order to access one data in a fast flash memory bank, described fast-flash memory body controller comprises:

One microprocessor unit;

One main frame boundary element connects described microprocessor unit, and described main frame boundary element is in order to connect a host computer system and receive described data from described host computer system, and wherein said data comprises a plurality of sub-data;

One fast flash memory bank boundary element connects described microprocessor unit and in order to connect described fast flash memory bank;

One memory body operating unit connects described microprocessor unit;

One error correction unit connects described microprocessor unit and with thinking that described data produces an error-correcting code, wherein said memory body operating unit can write described data and described error-correcting code in the described fast flash memory bank; And

One bit inspection unit, connect described microprocessor unit and with thinking that each described a plurality of sub-data produces a bit check code, to generate a plurality of bit check codes of corresponding described a plurality of sub-data, wherein said memory body operating unit can write described a plurality of bit check codes in the described fast flash memory bank.

10. fast-flash memory body controller according to claim 9 is characterized in that, described memory body operating unit is also checked code table in order to set up a bit, and wherein said a plurality of bit check codes are recorded in described bit and check in the code table.

11. fast-flash memory body controller according to claim 10, it is characterized in that described memory body operating unit also checks that to write down described bit the mapping between a plurality of bit check codes described in the code table and the described a plurality of sub-data concerns in order to set up a bit check code mapping table.

12. fast-flash memory body controller according to claim 10, it is characterized in that, described memory body operating unit is also checked in code table to a buffer memory in order to be written into described bit from described fast flash memory bank, and read described a plurality of bit check codes of corresponding described a plurality of sub-data from described buffer memory.

13. fast-flash memory body controller according to claim 9, it is characterized in that, described memory body operating unit is also in order to reading described a plurality of sub-data from described fast flash memory bank, and reads the bit check code of the corresponding described a plurality of sub-data that read from described fast flash memory bank

Wherein said bit inspection unit can judge whether the described a plurality of sub-data that read have mistake according to the bit check code of the described a plurality of sub-data that read,

Wherein working as the described a plurality of sub-data that read does not have when having mistake, and described memory body operating unit is given described host computer system with the described a plurality of sub-data transmissions that read.

14. fast-flash memory body controller according to claim 13, it is characterized in that, when the described a plurality of sub-data that read have mistake, then described memory body operating unit can read described data and described error-correcting code from described fast flash memory bank, and described error correction unit can be proofreaied and correct the described data that is read according to the described error-correcting code that is read

Wherein said memory body operating unit can obtain described a plurality of sub-data of having proofreaied and correct from the described data of being proofreaied and correct, and the described a plurality of sub-data transmissions that will proofread and correct are given described host computer system.

15. fast-flash memory body controller according to claim 9 is characterized in that, described bit inspection unit is that an error detection circuit and each described a plurality of bit check code are an error detection sign indicating number.

16. fast-flash memory body controller according to claim 9 is characterized in that, described bit inspection unit is that a cyclic redundancy check and each described a plurality of bit check code are a Cyclical Redundancy Check sign indicating number.

17. fast-flash memory body controller according to claim 9 is characterized in that, the size of each described a plurality of sub-data is a minimum access unit of described host computer system.

18. a fast flash memory bank stocking system is characterized in that, comprising:

One fast flash memory bank;

One fast-flash memory body controller connects described fast flash memory bank, and in order to receive a data from a host computer system, wherein said data has a plurality of sub-data,

Wherein said fast-flash memory body controller can produce an error-correcting code for described data, and described data and described error-correcting code are write in the described fast flash memory bank,

Wherein said fast-flash memory body controller can produce a bit check code for each described a plurality of sub-data, generating a plurality of bit check codes of corresponding described a plurality of sub-data, and described a plurality of bit check codes is write in the described fast flash memory bank.

19. fast flash memory bank stocking system according to claim 18 is characterized in that, described fast flash memory bank also comprises bit inspection code table, and wherein said a plurality of bit check codes are recorded in described bit and check in the code table.

20. fast flash memory bank stocking system according to claim 19, it is characterized in that described fast-flash memory body controller also checks that to write down described bit the mapping between a plurality of bit check codes described in the code table and the described a plurality of sub-data concerns in order to set up a bit check code mapping table.

21. fast flash memory bank stocking system according to claim 20 is characterized in that, also comprises a buffer memory,

Wherein said fast-flash memory body controller is also checked code table to described buffer memory in order to be written into described bit from described fast flash memory bank, and reads described a plurality of bit check codes of corresponding described a plurality of sub-data from described buffer memory.

22. fast flash memory bank stocking system according to claim 18, it is characterized in that, described fast-flash memory body controller is also in order to read described a plurality of sub-data from described fast flash memory bank, and from described fast flash memory bank, read the bit check code of the corresponding described a plurality of sub-data that read

Wherein said fast-flash memory body controller can judge whether the described a plurality of sub-data that read have mistake according to the bit check code of the described a plurality of sub-data that read,

Wherein working as the described a plurality of sub-data that read does not have when having mistake, and described fast-flash memory body controller can be given described host computer system with the described a plurality of sub-data transmissions that read.

23. fast flash memory bank stocking system according to claim 22, it is characterized in that, when the described a plurality of sub-data that read have mistake, then described fast-flash memory body controller can read described data and described error-correcting code from described fast flash memory bank, and proofread and correct the described data that is read according to the described error-correcting code that is read

Wherein said fast-flash memory body controller can obtain described a plurality of sub-data of having proofreaied and correct from the described data of being proofreaied and correct, and the described a plurality of sub-data transmissions that will proofread and correct are given described host computer system.

24. fast flash memory bank stocking system according to claim 18 is characterized in that, each described a plurality of bit check code is an error detection sign indicating number or a Cyclical Redundancy Check sign indicating number.

25. fast flash memory bank stocking system according to claim 18 is characterized in that, the size of each described a plurality of sub-data is a minimum access unit of described host computer system.

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