CN101872318A - Data access method for flash memory and storage system and controller thereof - Google Patents
Data access method for flash memory and storage system and controller thereof Download PDFInfo
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Abstract
The invention relates to a data access method for a flash memory and a storage system and a controller thereof. The data access method is used for accessing data in the flash memory, wherein the data is provided with at least one piece of subdata. The data access method comprises the following steps of: generating an error correcting code for the data to be written; and writing the data to be written and the generated error correcting code in the flash memory. In addition, the data access method also comprises a step of: generating corresponding bit check codes for each piece of subdata of the data, and writing the generated bit check codes in the flash memory. Due to the scheme, when the subdata is about to be read from the flash memory, whether an error bit is present in the read subdata is judged only according to a bit check unit corresponding to the read subdata so as to improve the data access speed.
Description
Technical field
The present invention relates to a kind of fast flash memory bank stocking system and fast-flash memory body controller that is used for the data access method of fast flash memory bank and uses the method.
Background technology
Digital camera, mobile phone and MP3 are very rapid in growth over the years, make the storage requirements of consumer's logarithmic code content also increase rapidly.Because fast flash memory bank (Flash Memory) has that data is non-volatile, power saving, volume is little and the characteristic of no mechanical structure etc., suitable user carries the Storage Media as digital archives transmission and exchange.(Solid State Drive is exactly with the example of fast flash memory bank as Storage Media SSD), and has been widely used in the computer host system as Primary Hard Drive solid hard disc.
When carrying out data access in using the fast flash memory bank stocking system of fast flash memory bank as Storage Media, the fast flash memory bank stocking system can be carried out an error-correcting routine by an Error-Correcting Circuit and verify whether the data of institute's access is correct.Specifically, when the user desired to write data to the fast flash memory bank stocking system, system's data for this reason produced an error-correcting code and data of desiring to write and the error-correcting code that is produced is write in the fast flash memory bank.Afterwards, when the user desires to read this data, system can from fast flash memory bank, read this data and error-correcting code thereof and according to the error-correcting code inspection of being read with proofread and correct the data that is read, guarantee the correctness of the data that reads thus.Particularly, Error-Correcting Circuit and error-correcting code can be according to different calibration capabilities and are different.That is to say, less wrong bit can be checked and proofread and correct to the Error-Correcting Circuit of lower-order and error-correcting code only, and more wrong bit can be checked and proofread and correct to the Error-Correcting Circuit of higher-order and error-correcting code, and the required storage area of error-correcting code that wherein stores higher-order can be greater than the required storage area of error-correcting code that stores lower-order.
In the design of fast flash memory bank stocking system, in general, the fast flash memory bank of fast flash memory bank stocking system comprises a plurality of physical blocks (physical block), and each physical blocks has a plurality of pages (page), and data is to be that unit writes in the fast flash memory bank with the page.Each page is made up of data bit district and redundant bit district, the data that the data bit district desires to write in order to storage, and redundant bit district in order to store relevant control information of this page and error-correcting code (Error Correction Code, ECC).For example, when the page with 1 sector (promptly, 512 bit groups) when disposing, the data bit district of this page can dispose and redundant bit district can dispose with 16 bit groups with 512 bit groups, wherein 10 bit groups are used for the error-correcting code of this page in order to storage to 6 bit groups in redundant bit district in order to the control information that stores this page, that is to say that 10 bit groups promptly enough store the error-correcting code of 512 bit group data of correspondence.
Along with the development of fast-flash memory body technique, the capacity of each page constantly increases.For example, developed at present and the fast flash memory bank that 1 page has 4 sectors (that is 2048 bit groups).Along with the number increase of storable bit group in 1 page, the calibration capability that therefore is used for this page fault correcting code also need promote, and can effectively guarantee the correctness of data in the page.Therefore, disposing in the page in data bit district with 2048 bit groups, redundant bit district can dispose with 61 bit groups, wherein 8 bit groups in order to store the control information 53 bit groups in order to the error-correcting code of the data that stores corresponding 2048 bit groups.
In general, computer system is that the unit comes the access data with the sector, therefore in the example of the fast flash memory bank stocking system that the page of fast flash memory bank is made up of 4 sectors, because the error-correcting code in the page produces according to the data of 4 sectors, so when both having made computer system only read the data of 1 sector in this page, the fast flash memory bank stocking system still must read complete information in this page (that is the data in 4 sectors) and come the execution error correction program with its corresponding error-correcting code.The base this, read in the example of a small amount of data in computer system, this kind access mode will have a strong impact on the access speed of fast flash memory bank stocking system.
Summary of the invention
A purpose of the present invention provides a kind of data access method, and it can be lifted at the speed of the data that reads in the fast flash memory bank effectively.
Another object of the present invention provides a kind of fast-flash memory body controller, and it can be lifted at the speed of the data that reads in the fast flash memory bank effectively.
A further object of the present invention provides a kind of fast flash memory bank stocking system, and it can be lifted at the speed of the data that reads in the fast flash memory bank effectively.
For achieving the above object, the present invention proposes a kind of data access method, is used in a fast flash memory bank access one data.This data access method comprises reception data from a host computer system, and wherein the data that is received comprises a plurality of sub-data.This data access method also is included as the data that is received and produces an error-correcting code (Error Correction Code ECC), and writes the data that received and the error-correcting code that produced in the fast flash memory bank.And this data access method also is included as each sub-data and produces a corresponding bit check code, and the bit check code that is produced is written in the fast flash memory bank.
For achieving the above object, the present invention also proposes a kind of fast-flash memory body controller, in order to access one data in a fast flash memory bank, this fast-flash memory body controller comprises microprocessor unit and connects the main frame boundary element of this microprocessor unit, fast flash memory bank boundary element, memory body operating unit, error correction unit and bit inspection unit.The main frame boundary element in order to connect a host computer system and from host computer system the reception data, wherein the data that is received comprises a plurality of sub-data.Fast flash memory bank boundary element and in order to connect fast flash memory bank.Error correction unit is with thinking that the data that is received produces an error-correcting code, and wherein the memory body operating unit can write data that is received and the error-correcting code that is produced in the fast flash memory bank.The bit inspection unit is with thinking that each sub-data produces a bit check code, and wherein the memory body operating unit can write the bit check code that is produced in the fast flash memory bank.
The present invention proposes a kind of fast flash memory bank stocking system, and it comprises fast flash memory bank and the fast-flash memory body controller that is connected this fast flash memory bank.The fast-flash memory body controller is in order to receive the data with a plurality of sub-data from a host computer system, the fast-flash memory body controller can produce an error-correcting code for the data that is received, and data that is received and the error-correcting code that is produced are write in the fast flash memory bank.In addition, the fast-flash memory body controller can produce a bit check code for each sub-data, and the bit check code that is produced is write in the fast flash memory bank.
As shown from the above technical solution, the present invention can be when host computer system desires to read the facts on file that is less than a page, only need to check access errors bit whether and need not read data and error-correcting code thereof in the full page, promote the speed of data access thus at the facts on file of desiring to read.
For the above-mentioned feature and advantage of the present invention can be become apparent, embodiment cited below particularly, and cooperate appended graphic being described in detail below.
Description of drawings
Fig. 1 is the general block diagram of the fast flash memory bank stocking system that one exemplary embodiment is illustrated according to the present invention;
Fig. 2 is the general block diagram of the physical blocks that exemplary embodiment illustrates according to the present invention;
Fig. 3 is the process flow diagram of the data write step that illustrates according to this exemplary embodiment;
Fig. 4 is the data flow diagram that writes example that exemplary embodiment illustrated according to the present invention;
Fig. 5 is the example that one exemplary embodiment illustrate stores bit check code table in physical blocks according to the present invention;
Fig. 6 is the process flow diagram of the data read step that illustrates according to this exemplary embodiment.
Accompanying drawing main element symbol description
110: the fast-flash memory body controller; 110a: microprocessor unit;
110b: memory body operating unit; 110c: fast flash memory bank boundary element;
110d: main frame boundary element; 110e: error correction unit;
110f: bit inspection unit; 120: the fast flash memory bank wafer;
120-0～120-N: physical blocks; D: data bit district;
R: redundant bit district; 400: bit is checked code table;
S301, S303, S305, S307, S309: data write step;
S601, S603, S605, S607, S609, S611, S613, S615, S617, S619, S621: data read step.
Embodiment
Fig. 1 is the general block diagram of the fast flash memory bank stocking system that one exemplary embodiment is illustrated according to the present invention.
Please refer to Fig. 1, fast flash memory bank stocking system 100 uses with host computer system 200 usually, so that host computer system 200 can write data fast flash memory bank stocking system 100 or read data from fast flash memory bank stocking system 100.In this exemplary embodiment, fast flash memory bank stocking system 100 be solid hard disc (Solid State Drive, SSD).But it must be appreciated that fast flash memory bank stocking system 100 also can be memory card or carry-on dish in another embodiment of the present invention.
Fast flash memory bank stocking system 100 comprises fast-flash memory body controller 110 and fast flash memory bank wafer 120.
Fast-flash memory body controller 110 can be carried out a plurality of logic locks or the steering order with hardware pattern or the design of solidification software pattern, and carries out the runnings such as writing, read and erase of data in fast flash memory bank wafer 120 according to the instruction of host computer system 200.Fast-flash memory body controller 110 comprises microprocessor unit 110a, memory body operating unit 110b, fast flash memory bank boundary element 110c, main frame boundary element 110d, error correction unit 110e and bit inspection unit 110f.
Memory body operating unit 110b connects microprocessor unit 110a, and in order to carry out block management mechanism.Particularly, memory body operating unit 110b is in order to carry out the data access mechanism according to this exemplary embodiment.
In the present embodiment, memory body operating unit 110b designs in controller 110 with a solidification software pattern.For example, to comprise that a plurality of steering orders (for example are burned onto a formula memory body, ROM (Read Only Memory, ROM)) be embedded in the fast-flash memory body controller 110 to design memory body operating unit 110b in and with this formula memory body, wherein when fast flash memory bank stocking system 100 started, a plurality of machine instructions of memory body operating unit 110b can be carried out to finish the block management mechanism and data writing mechanism according to the embodiment of the invention by microprocessor unit 110a.
In another embodiment of the present invention, the steering order of memory body operating unit 110b also can the software pattern be stored in the specific region of fast flash memory bank wafer 120.Same, when fast flash memory bank stocking system 100 started, the steering order of memory body operating unit 110b can be carried out by microprocessor unit 110a.In addition, in another embodiment of the present invention, memory body operating unit 110b also can a hardware pattern design in fast-flash memory body controller 110.
Fast flash memory bank boundary element 110c connects microprocessor unit 110a and in order to access flash memory chip 120.That is to say that the data of desiring to write fast flash memory bank wafer 120 can be converted to 120 receptible forms of fast flash memory bank wafer via fast flash memory bank boundary element 110c.
The instruction that main frame boundary element 110d connects microprocessor unit 110a and transmitted in order to reception and identification host computer system 200.That is to say that instruction that host computer system 200 is transmitted and data can see through main frame boundary element 110d and be sent to microprocessor unit 110a.In this exemplary embodiment, main frame boundary element 110d is the SATA interface.Yet, it must be appreciated to the invention is not restricted to this that main frame boundary element 110d also can be USB interface, IEEE 1394 interfaces, PCIExpress interface, MS interface, MMC interface, SD interface, CF interface, IDE interface or other data transport interface that is fit to.
Bit inspection unit 110f connects microprocessor unit 110a and in order to carry out an error detection program.Specifically, when input one data in bit inspection unit 110f, bit inspection unit 110f can produce a bit check code according to this data, and when importing a data and a bit check code at bit inspection unit 110f, bit inspection unit 110f can come to carry out bug check for the data that is received according to the bit check code that is received.For example, in this exemplary embodiment, bit inspection unit 110f designs with error detection circuit (error detecting circuit), and bit inspection unit 110f can produce error detection sign indicating number (error detection code) as the bit check code.Yet, in another embodiment of the present invention, bit inspection unit 110f also can design by cyclic redundancy check (cyclicr edundancy check circuit), and bit inspection unit 110f can produce Cyclical Redundancy Check (cyclic redundancy check) sign indicating number as the bit check code.Perhaps, in another embodiment of the present invention, bit inspection unit 110f also can design by low order Error-Correcting Circuit (error correcting circuit), and bit inspection unit 110f can produce the low order error-correcting code as the bit check code, is meant Error-Correcting Circuit and the error-correcting code that tool hangs down error correction capability for error correction unit 110e and its error-correcting code at this low order Error-Correcting Circuit and low order error-correcting code.
In addition, though be not illustrated in this exemplary embodiment, fast-flash memory body controller 110 comprises that also buffer memory, Power Management Unit etc. are used to control the general utility functions module of fast flash memory bank.
Fast flash memory bank wafer 120 connects fast-flash memory body controller 110 and has a plurality of physical blocks 120-0～120-N to store data.In this exemplary embodiment, fast flash memory bank wafer 120 is multilayer mnemon (Multi Level Cell, MLC) a NAND fast flash memory bank.Yet, it must be appreciated, the invention is not restricted to this.In another embodiment of the present invention, (Single Level Cell, SLC) the NAND fast flash memory bank also can be applicable to the present invention to individual layer mnemon.
Fig. 2 is the general block diagram of the physical blocks that exemplary embodiment illustrates according to the present invention.The structure of each physical blocks 120-1～120-N is identical in this exemplary embodiment, and the general block diagram of Fig. 2 is applicable to each physical blocks 120-0～120-N.
Please refer to Fig. 2, physical blocks comprises 128 pages, and each page can store the data of 4 sectors.Specifically, the data bit district D of each page is 2048 bit groups, and the redundant bit district R of each page is 61 bit groups, and 8 bit groups are used to store the control information relevant with the page and 53 bit groups are used to store the error-correcting code that is used for the page among the wherein redundant bit district R.
Fig. 3 is the process flow diagram of the data write step that illustrates according to this exemplary embodiment.
Please refer to Fig. 2 and Fig. 3, when host computer system 200 desired to write data to fast flash memory bank stocking system 100, in step S301, fast-flash memory body controller 110 can receive the data of desiring to write from host computer system 200.In this exemplary embodiment, the data that is received has at least one sub-data, and the size of these a plurality of sub-data is the minimum access unit (that is sector) of host computer system 200.For example, when the access unit of host computer system 200 was 512 bit groups, the size of sub-data also was 512 bit groups.Specifically, fast-flash memory body controller 110 can receive to write to instruct from host computer system 200 and write the sub-data of instruction with corresponding this through main frame boundary element 110d.
Then, in step S303, fast-flash memory body controller 110 can produce corresponding error-correcting code for the data that is received.Specifically, the received data of main frame boundary element 110d can be sent to error correction unit 110e, and produces corresponding error-correcting code by error correction unit 110e.
Afterwards, in step S305, the memory body operating unit 110b of fast-flash memory body controller 110 can write data and the corresponding error-correcting code of desiring to write thereof among the physical blocks 120-0～120-N of fast flash memory bank wafer 120 through fast flash memory bank boundary element 110c.
Then, in step S307, fast-flash memory body controller 110 can produce corresponding bit check code for each sub-data.Specifically, each sub-data can be transferred into bit inspection unit 110f, and bit inspection unit 110f can produce corresponding bit check code for each sub-data.
At last, in step S309, memory body operating unit 110b can see through the bit check code that is produced fast flash memory bank boundary element 110c and write among the physical blocks 120-0～120N of fast flash memory bank wafer 120.What deserves to be mentioned is, because redundant bit district only enough stores the error-correcting code of corresponding this data when writing data in the page, therefore the bit check code of the corresponding sub-data that produces is stored in the data bit district of another physical blocks in the meeting of this exemplary embodiment.That is to say that memory body operating unit 110b is considered as physical data with described a plurality of bit check codes and writes in the fast flash memory bank wafer 120.What deserves to be mentioned is that in exemplary embodiment of the present invention, memory body operating unit 110b can set up a bit and check that code table 400 writes down the bit check code that is produced.
The data flow diagram that writes example that Fig. 4 is that exemplary embodiment illustrated according to the present invention.
Please refer to Fig. 4, if fast-flash memory body controller 110 receives the data DATA that data quantity is 2048 bit groups from host computer system 200, fast-flash memory body controller 110 can produce error-correcting code ECC for data DATA.In addition, fast-flash memory body controller 110 can be divided into data DATA data DATA1, sub-data DATA2, sub-data DATA3 and sub-data DATA4 and corresponding bit check code BCC1, bit check code BCC2, bit check code BCC3 and the bit check code BCC4 of generation in regular turn.Afterwards, can write in the page 0 of physical blocks 120-0 with error-correcting code ECC by the data DATA that sub-data DATA1, sub-data DATA2, sub-data DATA3 and sub-data DATA4 formed.Simultaneously, fast-flash memory body controller 110 can check that code table 400 can be written in the page 0 of physical blocks 120-N with the bit of record bit check code BCC1, bit check code BCC2, bit check code BCC3 and bit check code BCC4.
Fig. 5 is the example that one exemplary embodiment illustrate stores bit check code table in physical blocks according to the present invention.
Please refer to Fig. 2 and Fig. 5, for example, the bit of record physical blocks 120-0～120-127 bit check code checks that code table 400 is stored among the physical blocks 120-N.In this exemplary embodiment, be 4 bit groups because sub-data is the required storage area of bit check code of 512 bit groups and each sub-data, therefore 1 physical blocks can store the bit check code of corresponding 128 physical blocks.Particularly, because memory body operating unit 110b stores bit check code table 400 in the mode that stores physical data, so can there be the error-correcting code of corresponding bit check code in the redundant bit district of physical blocks.In addition, in another exemplary embodiment of the present invention, memory body operating unit 110b can set up a bit check code mapping table with the corresponding relation between bit check code and the sub-data in the record bit check code table, is beneficial to thus check the bit check code that reads corresponding sub-data the code table from bit.
What deserves to be mentioned is, check that code table 400 can need bigger storage area owing to set up bit for all physical blocks in the fast flash memory bank wafer 120, therefore in another exemplary embodiment of the present invention, memory body operating unit 110b only can be at often carrying out the physical blocks of access and set up bit and check code table 400 to read the facts on file data quantity of a page (that is, less than) mode.For example, host computer system 200 can (File Allocation Table reads facts on file in physical blocks FAT), can reduce thus to store the required memory body space of bit check code table 400 through the save File allocation list of being everlasting.
In addition, because bit check code table 400 can constantly be updated in access procedure, therefore during the running of fast flash memory bank stocking system 100, bit checks that code table 400 can be written in the buffer memory (not illustrating) in order to renewal from fast flash memory bank wafer 120, and when 100 shutdown of fast flash memory bank stocking system, bit checks that code table 400 can be written back to fast flash memory bank wafer 120.
Fig. 6 is the process flow diagram of the data read step that illustrates according to this exemplary embodiment.Please refer to Fig. 2, Fig. 5 and Fig. 6, when host computer system 200 desires read data from fast flash memory bank stocking system 100, in step S601, fast-flash memory body controller 110 can judge that whether data quantity that host computer system 200 desires to read is less than 1 page.Specifically, fast-flash memory body controller 110 can see through main frame boundary element 110d receive reading command from host computer system 200, and memory body operating unit 110b can judge that whether data quantity that host computer system 200 desires to read is less than 1 page according to the address of desiring in the reading command to read.
For example, store with sub-data DATA1, sub-data DATA2, sub-data DATA3 and sub-data DATA4 at the page 0 of described physical blocks 120-0 and to be formed in the example of data DATA, if only desiring to read the some of sub-data DATA1, sub-data DATA2, sub-data DATA3 and sub-data DATA4, host computer system 200 during whole data DATA, represents that then the data quantity that host computer system 200 is desired to read is less than 1 page.
If judge that in step S601 data quantity that host computer system 200 desires to read is non-during less than 1 page, then memory body operating unit 110b can see through fast flash memory bank boundary element 110c and read data and corresponding error-correcting code thereof from fast flash memory bank wafer 120 in step S603, and error correction unit 110e can be according to data that is read and error-correcting code execution error correction program in step S605.Afterwards, in step S607, memory body operating unit 110b can see through main frame boundary element 110d and give host computer system 200 with the data transmission of executed error-correcting routine.For example, when if host computer system 200 desires to read the data DATA of the page 0 of physical blocks 120-0, fast-flash memory body controller 110 can read data DATA and error-correcting code ECC thereof, and the execution error correction program, and then the data DATA of executed error-correcting routine is sent to host computer system 200.
If when judging that in step S 601 data quantity that host computer system 200 desires to read is less than 1 page, then memory body operating unit 110b can see through fast flash memory bank boundary element 110c and read the sub-data desiring to read from fast flash memory bank wafer 120 in step S609, and memory body operating unit 110b can check from bit and obtain corresponding bit check code the code table 400 in step S611, if wherein bit checks that when code table 400 was not written into buffer memory (not illustrating), memory body operating unit 110b can read bit and check code table 400 from fast flash memory bank wafer 120.
Afterwards, bit inspection unit 110f can judge in the sub-data that is read whether have wrong bit according to sub-data that is read and corresponding bit check code in step S613.If the sub-data that is read does not have when having wrong bit, then memory body operating unit 110b can be with the sub-data transmission that read to host computer system 200 in step S615.
If when the sub-data that is read has wrong bit, then in step S617, can see through fast flash memory bank boundary element 110c and from fast flash memory bank wafer 120, read complete information and corresponding error-correcting code thereof, and error correction unit 110e can be according to data that is read and error-correcting code execution error correction program in step S619.At last, memory body operating unit 110b can obtain sub-data that host computer system 200 desires to read and give host computer system 200 with the sub-data transmission that is obtained from the data of having proofreaied and correct in step S621.
For example, when if host computer system 200 desires to read the sub-data DATA1 of the page 0 of physical blocks 120-0, fast-flash memory body controller 110 can read sub-data DATA1 and bit check code BCC1, and judges among the sub-data DATA1 that is read whether have wrong bit according to bit check code BCC1.If do not have among the sub-data DATA1 that is read when having wrong bit, then fast-flash memory body controller 110 can directly send the sub-data DATA1 that is read to host computer system 200.Otherwise, if when having wrong bit among the sub-data DATA1 that is read, then fast-flash memory body controller 110 can read data DATA and error-correcting code ECC thereof again from fast flash memory bank wafer 120, and the execution error correction program, and then obtain sub-data DATA1 and the sub-data DATA1 that is obtained is sent to host computer system 200 from the data DATA of executed error-correcting routine.
It must be appreciated, the described execution sequence of Fig. 3 and Fig. 6 and unrestricted the present invention, these those skilled in the art can be according to carrying out above-mentioned steps to be different from the described order of Fig. 3 and Fig. 6 under the spirit of the present invention.
In sum, the present invention is divided into several sub-data with the access unit of data respective hosts system when writing data in the page to fast flash memory bank, and for each data produces a bit check code, thus when host computer system reads sub-data from the page of fast flash memory bank, can see through corresponding bit check code and carry out the bit inspection, and the data that only just reads full page when the bit mistake takes place from fast flash memory bank is carried out error recovery, can promote the reading speed of fast flash memory bank thus.
It should be noted that at last: above embodiment is only in order to technical scheme of the present invention to be described but not limit it, although the present invention is had been described in detail with reference to preferred embodiment, those of ordinary skill in the art is to be understood that: it still can make amendment or be equal to replacement technical scheme of the present invention, and these modifications or be equal to replacement and also can not make amended technical scheme break away from the spirit and scope of technical solution of the present invention.
Claims (25)
1. a data access method is characterized in that, is used in a fast flash memory bank access one data, and described data access method comprises:
Receive described data from a host computer system, wherein said data comprises a plurality of sub-data;
For described data produces an error-correcting code;
Described data and described error-correcting code are write in the described fast flash memory bank;
For each described a plurality of sub-data produces a corresponding bit check code, to generate a plurality of bit check codes of corresponding described a plurality of sub-data; And
Described a plurality of bit check codes are write in the described fast flash memory bank.
2. data access method according to claim 1, it is characterized in that, comprise that also setting up a bit checks code table and check the described a plurality of bit check codes of record in the code table at described bit, wherein described a plurality of bit check codes are write step in the described fast flash memory bank and comprise described bit inspection code table is write in the described fast flash memory bank.
3. data access method according to claim 2 is characterized in that, comprises that also setting up a bit check code mapping table checks that to write down described bit the mapping between a plurality of bit check codes described in the code table and the described a plurality of sub-data concerns.
4. data access method according to claim 2, it is characterized in that, comprise that also being written into described bit from described fast flash memory bank checks in code table to a buffer memory, and from described buffer memory, read described a plurality of bit check codes of corresponding described a plurality of sub-data.
5. data access method according to claim 1 is characterized in that, also comprises:
From described fast flash memory bank, read described a plurality of sub-data;
From described fast flash memory bank, read the bit check code of the corresponding described a plurality of sub-data that read;
Judge according to the bit check code of the described a plurality of sub-data that read whether the described a plurality of sub-data that read have mistake,
Wherein working as the described a plurality of sub-data that read does not have when having mistake, gives described host computer system with the described a plurality of sub-data transmissions that read.
6. data access method according to claim 5 is characterized in that, when the described a plurality of sub-data that read had mistake, then described data access method also comprised:
From described fast flash memory bank, read described data and described error-correcting code;
Proofread and correct the described data that is read according to the described error-correcting code that is read;
From the described data of being proofreaied and correct, obtain described a plurality of sub-data of having proofreaied and correct; And
Give described host computer system with described a plurality of sub-data transmissions of having proofreaied and correct.
7. data access method according to claim 1 is characterized in that, each described a plurality of bit check code is an error detection sign indicating number or a Cyclical Redundancy Check sign indicating number.
8. data access method according to claim 1 is characterized in that, the size of each described a plurality of sub-data is a minimum access unit of described host computer system.
9. a fast-flash memory body controller is characterized in that, in order to access one data in a fast flash memory bank, described fast-flash memory body controller comprises:
One microprocessor unit;
One main frame boundary element connects described microprocessor unit, and described main frame boundary element is in order to connect a host computer system and receive described data from described host computer system, and wherein said data comprises a plurality of sub-data;
One fast flash memory bank boundary element connects described microprocessor unit and in order to connect described fast flash memory bank;
One memory body operating unit connects described microprocessor unit;
One error correction unit connects described microprocessor unit and with thinking that described data produces an error-correcting code, wherein said memory body operating unit can write described data and described error-correcting code in the described fast flash memory bank; And
One bit inspection unit, connect described microprocessor unit and with thinking that each described a plurality of sub-data produces a bit check code, to generate a plurality of bit check codes of corresponding described a plurality of sub-data, wherein said memory body operating unit can write described a plurality of bit check codes in the described fast flash memory bank.
10. fast-flash memory body controller according to claim 9 is characterized in that, described memory body operating unit is also checked code table in order to set up a bit, and wherein said a plurality of bit check codes are recorded in described bit and check in the code table.
11. fast-flash memory body controller according to claim 10, it is characterized in that described memory body operating unit also checks that to write down described bit the mapping between a plurality of bit check codes described in the code table and the described a plurality of sub-data concerns in order to set up a bit check code mapping table.
12. fast-flash memory body controller according to claim 10, it is characterized in that, described memory body operating unit is also checked in code table to a buffer memory in order to be written into described bit from described fast flash memory bank, and read described a plurality of bit check codes of corresponding described a plurality of sub-data from described buffer memory.
13. fast-flash memory body controller according to claim 9, it is characterized in that, described memory body operating unit is also in order to reading described a plurality of sub-data from described fast flash memory bank, and reads the bit check code of the corresponding described a plurality of sub-data that read from described fast flash memory bank
Wherein said bit inspection unit can judge whether the described a plurality of sub-data that read have mistake according to the bit check code of the described a plurality of sub-data that read,
Wherein working as the described a plurality of sub-data that read does not have when having mistake, and described memory body operating unit is given described host computer system with the described a plurality of sub-data transmissions that read.
14. fast-flash memory body controller according to claim 13, it is characterized in that, when the described a plurality of sub-data that read have mistake, then described memory body operating unit can read described data and described error-correcting code from described fast flash memory bank, and described error correction unit can be proofreaied and correct the described data that is read according to the described error-correcting code that is read
Wherein said memory body operating unit can obtain described a plurality of sub-data of having proofreaied and correct from the described data of being proofreaied and correct, and the described a plurality of sub-data transmissions that will proofread and correct are given described host computer system.
15. fast-flash memory body controller according to claim 9 is characterized in that, described bit inspection unit is that an error detection circuit and each described a plurality of bit check code are an error detection sign indicating number.
16. fast-flash memory body controller according to claim 9 is characterized in that, described bit inspection unit is that a cyclic redundancy check and each described a plurality of bit check code are a Cyclical Redundancy Check sign indicating number.
17. fast-flash memory body controller according to claim 9 is characterized in that, the size of each described a plurality of sub-data is a minimum access unit of described host computer system.
18. a fast flash memory bank stocking system is characterized in that, comprising:
One fast flash memory bank;
One fast-flash memory body controller connects described fast flash memory bank, and in order to receive a data from a host computer system, wherein said data has a plurality of sub-data,
Wherein said fast-flash memory body controller can produce an error-correcting code for described data, and described data and described error-correcting code are write in the described fast flash memory bank,
Wherein said fast-flash memory body controller can produce a bit check code for each described a plurality of sub-data, generating a plurality of bit check codes of corresponding described a plurality of sub-data, and described a plurality of bit check codes is write in the described fast flash memory bank.
19. fast flash memory bank stocking system according to claim 18 is characterized in that, described fast flash memory bank also comprises bit inspection code table, and wherein said a plurality of bit check codes are recorded in described bit and check in the code table.
20. fast flash memory bank stocking system according to claim 19, it is characterized in that described fast-flash memory body controller also checks that to write down described bit the mapping between a plurality of bit check codes described in the code table and the described a plurality of sub-data concerns in order to set up a bit check code mapping table.
21. fast flash memory bank stocking system according to claim 20 is characterized in that, also comprises a buffer memory,
Wherein said fast-flash memory body controller is also checked code table to described buffer memory in order to be written into described bit from described fast flash memory bank, and reads described a plurality of bit check codes of corresponding described a plurality of sub-data from described buffer memory.
22. fast flash memory bank stocking system according to claim 18, it is characterized in that, described fast-flash memory body controller is also in order to read described a plurality of sub-data from described fast flash memory bank, and from described fast flash memory bank, read the bit check code of the corresponding described a plurality of sub-data that read
Wherein said fast-flash memory body controller can judge whether the described a plurality of sub-data that read have mistake according to the bit check code of the described a plurality of sub-data that read,
Wherein working as the described a plurality of sub-data that read does not have when having mistake, and described fast-flash memory body controller can be given described host computer system with the described a plurality of sub-data transmissions that read.
23. fast flash memory bank stocking system according to claim 22, it is characterized in that, when the described a plurality of sub-data that read have mistake, then described fast-flash memory body controller can read described data and described error-correcting code from described fast flash memory bank, and proofread and correct the described data that is read according to the described error-correcting code that is read
Wherein said fast-flash memory body controller can obtain described a plurality of sub-data of having proofreaied and correct from the described data of being proofreaied and correct, and the described a plurality of sub-data transmissions that will proofread and correct are given described host computer system.
24. fast flash memory bank stocking system according to claim 18 is characterized in that, each described a plurality of bit check code is an error detection sign indicating number or a Cyclical Redundancy Check sign indicating number.
25. fast flash memory bank stocking system according to claim 18 is characterized in that, the size of each described a plurality of sub-data is a minimum access unit of described host computer system.
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| CN200910133685A CN101872318B (en) | 2009-04-22 | 2009-04-22 | Data access method for flash memory and storage system and controller thereof |
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| CN200910133685A CN101872318B (en) | 2009-04-22 | 2009-04-22 | Data access method for flash memory and storage system and controller thereof |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102819467A (en) * | 2012-03-06 | 2012-12-12 | 宜鼎国际股份有限公司 | Flash memory device capable of improving data correction capability |
| TWI497511B (en) * | 2012-11-08 | 2015-08-21 | Ind Tech Res Inst | Chip with embedded non-volatile memory and testing method therefor |
| CN106021035A (en) * | 2016-05-25 | 2016-10-12 | 浪潮电子信息产业股份有限公司 | Method for realizing fault verification on memory particles to enhance stability of module bar |
| CN106155581A (en) * | 2015-02-05 | 2016-11-23 | 慧荣科技股份有限公司 | Data storage device and data maintenance method thereof |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4074029B2 (en) * | 1999-06-28 | 2008-04-09 | 株式会社東芝 | Flash memory |
| KR100680473B1 (en) * | 2005-04-11 | 2007-02-08 | 주식회사 하이닉스반도체 | Flash memory device with reduced access time |
| CN100465910C (en) * | 2006-06-02 | 2009-03-04 | 上海思必得通讯技术有限公司 | Method for error protecting and error correcting of flash memory data in products |
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2009
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102819467A (en) * | 2012-03-06 | 2012-12-12 | 宜鼎国际股份有限公司 | Flash memory device capable of improving data correction capability |
| TWI497511B (en) * | 2012-11-08 | 2015-08-21 | Ind Tech Res Inst | Chip with embedded non-volatile memory and testing method therefor |
| CN106155581A (en) * | 2015-02-05 | 2016-11-23 | 慧荣科技股份有限公司 | Data storage device and data maintenance method thereof |
| CN106155581B (en) * | 2015-02-05 | 2019-04-12 | 慧荣科技股份有限公司 | Data storage device and data maintenance method thereof |
| CN106021035A (en) * | 2016-05-25 | 2016-10-12 | 浪潮电子信息产业股份有限公司 | Method for realizing fault verification on memory particles to enhance stability of module bar |
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| CN101872318B (en) | 2012-10-24 |
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