CN101868788B - Scheduling based on turnaround event - Google Patents
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Abstract
Transmission of a signal is scheduled to avoid sending the signal during a designated event associated with another signal. For example, the time at which a signal is transmitted may be scheduled to avoid a turnaround time period of a bidirectional signal path. This technique may be employed, for example, in a memory system where a memory controller communicates with one or more memory devices or memory modules. Here, the memory system may be configured to avoid sending memory request signals during a driver turnaround window corresponding to when a bidirectional memory data interface switches from being driven by the memory controller to being driven by a memory device/module, or vice versa.
Description
Technical field
The application relates generally to data processing, and more specifically but not exclusively relate to scheduling operation.
Background technology
Data handling system can adopt two-way link, adopts thus to write at interval and read the link data converted interface between the interval.For example, accumulator system can adopt bi-directional data (DQ) link, and wherein Memory Controller and memory devices drive this link at different time.Through using this two-way link, system can use available package pins more effectively and allocated bandwidth flexibly is provided.
In the practice, adopted when being designed for the signaling framework (for example, difference signaling or coding signaling) that reduces switch current even work as, the handoff procedure between the distinct device of driving link still can produce significant relatively switch current on link.Switch relevant noise issuable any harmful effect on link in order to reduce this driver; Can use so-called timing " bubbling "; During the time window that is associated with driver turnover (for example, write from reading, or vice versa), avoid data transmission thus.Through using this timing " bubbling ", can solve the noise that is associated with the driver turnover if having time, will produce dysgenic possibility to the data transmission on the link thereby reduce noise.
The action that opens and closes driver possibly cause that also switch current passes through the power supply coupling, thereby on another signal path, causes voltage noise.In some aspects, this voltage noise may directly reduce the receiver voltage tolerant.In some aspects, this noise may cause the timing jitter (perhaps phase noise) that increases in other signal paths, because the voltage noise on the power supply may influence driver output or receiver input delay and clock edge time of arrival.The inductance or the electric capacity that are coupling between the link also possibly cause the link that is experiencing turnover and not experience crosstalking between the contiguous link that has enough to meet the need.The voltage noise of this turnover induction also possibly reduce the voltage and/or the timing tolerance limit of other signal paths.A method that is used to solve these noise problems comprises: operate other signal paths with the signal rate that with respect to data routing, reduces and the voltage swing of Geng Gao.In fact, this method allows bigger timing and voltage tolerant, and in fact timing that this is bigger and voltage tolerant can absorb any degradation owing to the data routing switching noise in other signal paths.Yet, in some applications, do not expect to reduce the signal rate on the signal path or increase the voltage signal swing.Therefore, need be used to be supported in the effective technology that uses fast signal speed and/or big voltage signal swing on the signal path.
Description of drawings
Sample characteristics of the present disclosure, aspect and advantage will be described in detailed description at the back and claims and accompanying drawing, in the accompanying drawings:
Fig. 1 shows the reduced graph with the example of avoiding the signal turnaround event is dispatched in signal transmission;
Fig. 2 shows the reduced graph of the example of signal noise;
Fig. 3 can be carried out the process flow diagram with the embodiment of the operation of avoiding the signal turnaround event is dispatched in signal transmission by equipment;
Fig. 4 can be carried out by equipment to postpone for through the process flow diagram of scheduling with the embodiment of the operation of the action of the received signal of avoiding the signal turnaround event;
Fig. 5 is configured to handle through the simplified block diagram of scheduling with the embodiment of the apparatus assembly of the signal of avoiding the signal turnaround event;
Fig. 6 shows the reduced graph with the example of avoiding the signal turnaround event is dispatched in signal transmission; And
Fig. 7 shows the reduced graph with the example of avoiding the signal turnaround event is dispatched in signal transmission.
According to convention, the various characteristics shown in the accompanying drawing needn't be drawn in proportion.Correspondingly, the size of various characteristics can at random to enlarge in order knowing or to dwindle.In addition, some accompanying drawing can be simplified in order to know.Therefore, accompanying drawing can not described all component to locking equipment or method.At last, run through instructions and accompanying drawing, same reference numerals can be used to represent identical characteristic.
Embodiment
The disclosure relates in some aspects dispatches to avoid during the particular event that joins with another signal correction, sending this signal signal transmission.For example, can dispatch the transmission time that is used for signal on the channel avoid with another channel on two-way signaling switch the period be associated.
For illustrative purposes; Various aspects of the present disclosure will be described in the context of accumulator system; Its middle controller (for example, Memory Controller) is dispatched the transmission of request (RQ) channel signal of going to one or more memory devices or memory module (in instructions, being called " memory devices " for ease) on the RQ bus.Particularly; Controller is avoided (for example having enough to meet the need the period at driver; Turnover window 102 among Fig. 1) sends the RQ signal during; This driver turnover period, from switched to the time by memory device driver by controller drives, vice versa corresponding to ovonic memory data (DQ) channel on the DQ bus.Should be appreciated that the instruction here can be applied to signal, assembly and the system of other types.In addition, should be appreciated that this assembly can realize in other assemblies (for example, processor or memory module), and the instruction here can realize in the equipment of other types.
Fig. 1 shows the example of signal timing, and this signal timing can be used for during window continuous time (for example, time slot), carrying out memory access.The DQ channel relates to the signal on the two-way DQ bus (for example, data signal path).For example, data write (for example, writing to the packet of memory devices) by expressions such as W0, W1, and data read (packet of for example, reading from memory devices) by expressions such as R0, R1.Controller TX_ENABLE channel is represented can be at the transmission enable signal of controller place generation.Storer TX_ENABLE channel is represented can be at the transmission enable signal of memory devices place generation.
The RQ channel relates to by the request signal by the controller generation on the RQ bus (for example, request path).RQ-optimizes channel and representes the request that writes (for example, W0, W1 etc.) that can be generated by controller according to the instruction here and read (for example, R0, R1 etc.).For purpose relatively, the RQ-normal channel is represented can be by the request that writes (for example, W0, W1 etc.) and the request of reading (for example, R0, R1 etc.) of controller generation according to conventional practice.As shown in fig. 1, write request (for example, W0) or the request of reading (for example, R0) can correspondence write data (for example, W0) or reading of data (for example, R0) send before the transmission intercal.
As used herein, term " writes request " and " request of reading " relates to various types of signals (except data and clock signal) that can be used for visit data.For example, sort signal can comprise address and/or control information (for example, command, " C/A ").For the memory devices such as DRAM, sort signal can comprise: for example, and any combination of group address, row address, column address, operational code or these signals.In some implementations, each request (for example, W0) is divided into groups corresponding to a request.Like a simplification example, W0 can comprise that activation command and row address divide into groups; W1 can comprise write command and column address grouping; And W3 can comprise precharge command and group address grouping etc.
As shown in fig. 1, write or be written to the transition period of reading reading, can calm down on the DQ bus to allow switching noise introducing idling cycle (for example, time slot) on the DQ bus.For example, the W3 and first that writes at last on the DQ bus reads five idling cycles is provided between the R0.In addition, owing to idling cycle is inserted into the DQ bus, therefore can on the RQ bus, introduce idling cycle.For example, writing W0-W3 and reading on the conventional bus of RQ-provides three idling cycles between the R0-R5.
As indicated above, Fig. 1 shows and reads the turnover window 102 that R0 switching DQ interface is associated from writing W3 to the first at last.Particularly, controller stops to drive the DQ bus after time window 6, and memory devices begins to drive the DQ bus at time window 8 places.In conventional system, can observe the turnover window 102 during controller can transmit the RQ-normal signal (for example, R0-R2).Therefore, the result as turnover DQ bus possibly induce noise on the RQ-normal signal.
Fig. 2 shows the example of signal, and this signal can generate when driver opens and closes.Waveform 202 is examples of differential signal, and waveform 204 is examples of single-ended signal.The driver of differential signal is opened with arrow 208 indicated time point places at arrow 206 respectively and is closed then.The driver of single-ended signal is opened with arrow 212 indicated time points at arrow 210 respectively and is closed then.Data were transmitted during the time interval 214.As indicated among Fig. 2, because the possibility of the opening and closing institute generted noise of driver is high relatively during time window 216 and time window 218 respectively.
As used herein; Term " driver turnover window " expression greatly about a driver (for example; When data driver) beginning to close, and greatly about calmed down the time window that finishes when enough being used for reliable transmission from the noise of the driver of another unlatching.For example; The turnover window (for example; The turnover window 102 of Fig. 1) can be defined as and (for example be used to cover the potential noise period; Time window 218 and time window 216) and these potential noise periods between the period, this potential noise period closes with a driver and another driver unlatching is associated.
For the switch current that prevents to be caused by these turnaround events is gone up the induced voltage noise at other signal paths (such as the RQ bus), accumulator system can be configured to avoid between the turnover window phase, send request.For this reason, accumulator system can provide the prestrain of request impact damper before the turnover window.Here, controller can send one or more requests in early days, during idling cycle, sends one or more requests in other cases.Memory devices can cushion these requests then with before the inner issue request of memory devices, and suitable delay is provided.
The RQ-of Fig. 1 optimizes signal and shows how to dispatch the example of RQ signal to avoid between the turnover window phase, sending any RQ signal.Here, first group writes request (W0-W3) and during time window 0-3, transmits.Yet now, the R0-R2 that reads request transmits during time window 4-6, and do not have request signal with turnover window 102 that time window 7-9 is associated during transmit.As in the RQ-regular situation, the remaining request R3-R5 that reads transmits during time window 10-12 then.To RQ-optimize write signal W0-W2 adopt similar scheduling mechanism with avoid with turnover window 104 that time window 18-20 is associated during transmission requests.
Use above technology can advantageously reduce the susceptibility that request channel (for example, RQ bus) is gone up noise.Through reducing this noise, accumulator system can adopt request channel narrower and more at a high speed.For example, the request channel can be operating with the signal rate that the signal rate of data channel (for example, data bus) is compared.Use request channel narrower and more high speed can much more more to ask channels and to support the visit granularity that use is meticulousr so that controller pin expense reduces, support is used then.
To combine now Fig. 3-Fig. 7 describe in further detail of the present disclosure these with other aspects.Fig. 3 has described the controller of basis the instruction here can carry out the some operations with dispatch request.Fig. 4 has described memory devices and can carry out to handle the some operations through the request of scheduling.Fig. 5 shows the sample embodiment of accumulator system 500, and this accumulator system 500 comprises Memory Controller 502 and memory devices 504.Memory Controller 502 comprises memory interface 526; This memory interface 526 is configured to communicate via the control unit interface 528 of interconnection 506 (memory buss that for example, comprise data signal path, clock signal path and control signal path) with memory devices 504.Fig. 6 and Fig. 7 show memory access signals additional example regularly.
For convenience's sake, the operation of Fig. 3 and Fig. 4 (perhaps operation of discussing here or instructing) can be described as being carried out by specific components (for example, the assembly of system 500).Yet should be appreciated that these operations can be carried out by the assembly of other types, and can use the assembly of varying number to carry out.Be also to be understood that in given realization and can not adopt one or more operations described here.
As represented by the frame 302 of Fig. 3, Memory Controller 502 receives one or more orders (perhaps other suitable message) from one or more associated device (for example, processor) of the memory array 508 of request reference-to storage equipment 504.According to conventional practice, Memory Controller 502 (for example, scheduler 510) can be carried out operation such as arbitration and scheduling handling these message, and sends respective request to memory devices 504 in due course.
According to the instruction here, scheduling operation can comprise through dispatch request during the available requests channel time slot before the turnaround event avoids the request of during the turnaround time, sending, and possibly between the turnover window phase, dispatch in other cases should request.In some aspects, this can write or be written to the suitable priori that reads turnaround event through reading of being described below, priori and the priori of basic timing parameters of one or more requests after this turnaround event realizes.
Represented like frame 304, Memory Controller 502 (for example, the turnaround event detecting device 512) confirms when turnover will take place on the DQ bus.For example, in Fig. 6, scheduler 510 can have the W0-W3 that writes of previous scheduling, writes request in time window 0-3 place issue thus, and is in to provide on the DQ bus at time window 6-9 and writes data W 0-W3.In addition, scheduler 510 possibly confirmed next will dispatch the request of reading.In this case, turnaround event detecting device 512 can confirm that turnaround event 602 (for example, turnover window) will occur in time window 12-14 place.
Represented like frame 306, Memory Controller 502 (for example, scheduler 510) scheduling is read request R0-R5 to avoid turnaround event 602.Indicated like the conventional bus of RQ-, in legacy system, read request R0-R5 and can dispatch after sending through the DQ bus writing data W 0-W3.In this case, request signal R1-R3 may dispatch during turnaround event 602 and possibly suffer switching noise thus.On the contrary, it is indicated to optimize bus like RQ-, scheduler 510 can scheduling request signal R0-R3 so that transmission before turnaround event 602.Here, owing to write the idling cycle on the DQ bus after the data W 3, scheduler 510 can be discerned the some idling cycles (for example, time slot 604A-604C) that occur on the RQ bus.Scheduler 510 can use these idle RQ cycles then and dispatch RQ-at the time slot at time window 11 places and optimize the request R0-R3 shown in the bus.Request R4 and R5 can dispatch (for example, in the RQ-regular situation) then after turnaround event 602.
Fig. 7 shows the similar operations that when the DQ bus writes conversion from reading, can carry out.Here, the reading of data R0-R5 in time window 8-11, the scheduling of 15 and 16 places exports the DQ bus at time window 24-29 place to by memory devices 504.In addition, scheduler 510 has been confirmed next will dispatch the request of writing.In this case, turnaround event detecting device 512 confirms that turnaround event 702 occurs in time window 30-32 place.Scheduler 510 is dispatched then and is write request W0-W7 to avoid turnaround event 702.It is indicated to optimize bus like RQ-, and scheduler 510 can come scheduling request signal W0-W5 so that transmission before turnaround event 702 after the some idling cycle 704A-704C of identification.Scheduler 510 can use these idle RQ cycles and the time slot at time window 27-29 place to come dispatch request W0-W5 then.Request W6 and W7 can dispatch after turnaround event 702 then.In this case, and then Memory Controller 502 is placed on the DQ bus after the turnaround event 702 and is write data W 0-W7.
Refer again to Fig. 3; Represented like frame 308, Memory Controller 502 (for example, request postpones indicator 514) can send indication to memory devices 504; Its instruction memory equipment 504 postpones the action (for example, issue) for the request of scheduling before the turnaround time.This indication can be before the request of sending or along with one or more requests (frame 310) are sent to memory devices 504.In some implementations, how long this indication can instruction memory equipment 504 should postpone (for example, the quantity of clock period or time window) before the action for given request.Discuss below and can be used for config memory equipment 504 to postpone other mechanism of received request.
Represented like frame 310, Memory Controller 502 (for example, scheduler 510) is in scheduling time place's transmission request.For example, as shown in Figure 6, during time window 8-11,15 and 16, send and read request R0-R5.
Represented like frame 312, Memory Controller 502 is then based on request reference-to storage equipment 504.For example, as shown in Figure 7, Memory Controller 502 receives reading of data R0-R5 during time window 24-29.
With reference now to Fig. 4,, can be with discussing in further detail by the complement operation of memory devices 504 execution.In some implementations, this can comprise: some requests that will during the idle request cycle before the data turnaround event, load in other cases are preloaded into the request impact damper 516 in the memory devices 504.Through these the requests in the delay memory equipment 504 suitably through buffering, during turnaround event, on the DQ bus in memory devices 504 the issue request be possible, thereby avoided on the RQ bus voltage or the degradation of tolerance limit regularly.
Represented like frame 402, in some implementations, memory devices 504 (for example, request postpones indicator 518) can receive the indication that should how to postpone at memory devices 504 places about one or more requests.For example, said at frame 308 like preceding text, memory devices 504 can or combine one or more requests (frame 404) to receive this indication before receiving request.
Represented like frame 404, memory devices 504 (for example, memory accessing controller 524) receives the request of being sent at frame 310 by Memory Controller 502.Be described below, memory devices 504 is configured to handle effectively request, even also be (for example, shown in Fig. 6 and Fig. 7, the request in one group of given request is spaced apart on time) like this when the turnaround event period does not receive request.
Represented like frame 406, in some implementations, the time of the turnaround event that memory devices 504 (for example, the turnaround event detecting device 520) can be confirmed to be associated with received request.In this case, memory devices 504 can use the turnaround event time to determine whether to postpone the amount of asking and/or postponing.For example, whenever memory devices 504 detects to read writes conversion (or vice versa), and memory devices 504 can be according to defined delay period (for example, postponing three cycles to three requests) automatically delaying.Equally, memory devices 504 can detect the request that during turnover period (for example, three cycles), does not have entering, and request impact damper 516 should be empty (supposing the degree of depth of three requests) as a result.In this case, memory devices 504 will not postpone subsequently the request that receives from this group request.
As represented at frame 408, memory devices 504 (for example, request delayer 522) can postpone (for example, postponing issue) previous any request of sending (for example, before the turnaround event).In some aspects, this can comprise with the request that receives be stored in the request impact damper 516 in, be used for time up to appointment for the action of this request.
As stated, in some implementations, memory devices 504 receives given request will postpone indication how long, or utilize this indication to be configured in other cases.For example, in request in the received incident, request delayer 522 can be with the time delay that should request postpones indication in the request in this indication.In some cases, postpone request so that after turnaround event begins, move.For example, in Fig. 6, memory devices 504 can act on request R1 (for example, 3 time windows postpone) during time window 12, even on RQ bus (RQ-optimization), do not have flow this moment.
As represented at frame 410, memory devices 504 (for example, memory accessing controller 524) provides the visit to memory array 508 based on request then.For example, as shown in Fig. 7, memory devices 504 is exported reading of data R0-R5 during time window 24-29.
As the scheduling of the request of being instructed here or other signals can realize through variety of way.For example, various technology as mentioned above can be used to utilize following information configuration memory devices 504, and this information indicates whether the given request of delay and how long postpones.
In some implementations, memory devices 504 (for example, request postpones indicator 518) comprises the register of the value programming that utilizes indication lag.In this case, given request can comprise the indication (for example, bit) whether this particular request of indication will postpone.If will postpone, memory devices 504 can be with should request postponing the time quantum by the register value indication.
In some implementations, memory devices 504 is configured to after writing, not issue immediately and reads (vice versa).In this case, memory devices 504 can automatically postpone this read or write (for example, the period of definition).
In some aspects, accumulator system 500 can adopt the storer control protocol to optimize the performance of disclosed mechanism, and this agreement raising (for example, has maximized) probability of the idle request channel time slot before the turnaround event.In some aspects, this can provide the agreement of the idling cycle of enough confirming to realize on the RQ bus through using.For example, when use agreement, can relatively easily request be moved to idling cycle, this agreement provide usually request and data transmit between 1: 1 corresponding relation, and the fixed intervals between these requests and the data transmission are provided.On the contrary, owing to always do not have available idling cycle at optimal location, so when use agreement, possibly be difficult to more request is moved to idling cycle, wherein this agreement is used the time slot of variable number to every group of request.
In some aspects, the quantity of available time slot can improve through using less request packet access memory devices.For example, replace and send some request commands (for example, separately activation, read/write and precharge are divided into groups), agreement can be sent request as individual command.Here, order can comprise full address (for example, group, row, row).In addition, order can be adopted implicit expression regularly (for example, RAS is to CAS timing (t
RCD), be pre-charged to and activate regularly (t
RP), auto-precharge).As an example, through using auto-precharge (for example, memory devices 504 is issue precharge automatically when reading or writing end), precharge command needn't be sent through the request bus.As another example, memory devices 504 can comprise state machine, and this state machine is configured to adopt the row address that is provided by individual command; Issue activation command immediately; Then postpone row through predetermined timing parameters (for example, 5 cycles), issue auto-precharge then at last.In operation such as these operations employed any timing parameters can be predefined maybe can be configurable, and be stored in the register of memory devices 504.
Accumulator system can also adopt the agreement that provides the support that reduces turnover noise strategy.For example, this agreement can keep TX to open up to RD after WR.
Therefore, Memory Controller 502 can be configured to support one or more above-mentioned characteristics.For example, Memory Controller 502 can be for agreement provides support, the probability of the idle request channel time slot of this agreement maximization before turnaround event.Memory Controller 502 can comprise the function that detects upcoming turnaround event and do not send to conflict request ahead of time.Memory Controller 502 can comprise whether instruction memory equipment 504 will cushion/postpone request, what cycles request should postpone or should not issue the function of request immediately.
Similarly, any memory devices that is associated (or memory module) can be configured to support one or more above characteristics.For example, memory devices 504 can be for agreement provides support, the probability of the idle request channel time slot of this agreement maximization before turnaround event.Memory devices 504 can comprise supports reliable operation between driver turnover window phase, not receive the function of request simultaneously.Memory devices 504 can comprise and is used for the function between request that will cushion/postpone and the request that will issue immediately, distinguished.Memory devices 504 can comprise the function that is used for cushioning alternatively a plurality of requests and suitable delay request before the issue request.
The instruction here can advantageously be used in various memory system architectures.For example, some embodiment can adopt the memory architecture of fully differential.For example, this framework can adopt difference command (" C/A ") signal and differential data (DQ) signal.
In some implementations, full C/A channel (for example, RQ bus) can be provided in the single differential link with the DQ th rate.For example, the signaling rate of C/A signal (for example, request signal) can be compared (signaling rate that for example, equals the DQ signal) with the signaling rate of DQ signal.In this case, can advantageously adopt the instruction here to reduce the noise on the sort signal (it can have very little timing or voltage tolerant).The single C/A of each channel can be provided in addition.By this way, can significantly reduce the expense at controller place.In addition, can adopt similar circuit design, thereby simplify overall design to C/A and DQ channel.In some implementations, controller can be calibrated the transmission phase place of C/A channel.
The instruction according to here can realize the request grouping through variety of way.For example, in some embodiments, can use 32 bit requests to divide into groups, its provide 2 nanoseconds that the addressability that runs through 16Gbit generated, provided 16Gbps granularity and the flexible allocation of group/OK/column address bit is provided regularly.
Can also combine extendible memory architecture to adopt the instruction here.This extensibility can relate to capacity and visit granularity.For example; Provide the controller of four C/A links (for example can be configured to a memory devices; Have 32 bit width DQ buses) all four C/A links are provided, each memory devices (for example, having 16 bit width DQ buses) of being configured to two memory devices provides two C/A links; Each memory devices (for example, having 8 bit width DQ buses) that perhaps is configured to four memory devices provides a C/A link.
In some implementations, can combine dynamic point-to-point (DPP) memory architecture to adopt the instruction here.An example of sort memory framework discloses in the open No.2004/0221106 of U.S. Patent application, by reference this openly is incorporated into this.
In some implementations; Can combine configurable point-to-point framework to adopt the instruction here; This framework allows the expansion of RQ bandwidth usage data (DQ) bandwidth through using similar point-to-point topological sum signaling rate, allows to be used to keep being provided with of constant or low visit granularity simultaneously and carries out capacity extension.An example of this framework is at U.S. Provisional Patent Application No.60/988, and 826, be described among the broker file number No.RA608.Provl.US, by reference this openly is incorporated into this.
The instruction here can realize through various forms, some form can show as with open embodiment in those are very different.Therefore, ad hoc structure disclosed herein and function detail only are representative but do not limit disclosure scope.For example, based on the instruction here, it should be appreciated by those skilled in the art that and can various 26S Proteasome Structure and Function details disclosed herein be incorporated in the embodiment that is independent of any other structure or function detail.Therefore, can use any amount of structure or the function detail of in any disclosed embodiment, setting forth to come realization equipment or hands-on approach.Equally, except the structure or the function detail of in any disclosed embodiment, setting forth, can also use other structures or function detail to come realization equipment or hands-on approach.
As the controller equiment (integrated circuit that for example, has merged controller function) and the memory devices (integrated circuit that for example, has merged memory core) of instruction here can adopt various forms.For example, controller equiment can comprise the Memory Controller chip, comprise processor chips or some other suitable device of controller function.In some aspects, memory devices can comprise the semiconductor integrated circuit apparatus that comprises cell group, and this cell group can provide the part of memory array or memory array jointly.The sort memory example of equipment comprises volatile memory devices, non-volatile memory devices, DRAM, SRAM and flash memory device.
In some implementations, described here memory devices function can realize in the storage buffer assembly of memory module.In some aspects, storage buffer can comprise integrated circuit, and this integrated circuit is coupling between the signaling paths of each memory devices on memory interface contacts and the memory module of memory module.The example of storage buffer 26S Proteasome Structure and Function is described in the open No.2007/0070669 of U.S. Patent application, by reference this openly is incorporated into this.
As the accumulator system of instruction here can be used in various application.For example, can the sort memory system be incorporated into to computer graphics card, video game console, printer, personal computer, server or utilizes some other equipment of data storage.
Various 26S Proteasome Structure and Functions described here can be realized through variety of way and use various device.For example, equipment can realize through various nextport hardware component NextPorts, such as, some combination of processor, controller, state machine, one or more these assemblies of logical OR.
In some embodiments, the code (for example, software, firmware, middleware etc.) that comprises instruction can be carried out on one or more treatment facilities and realize one or more described functions or assembly.Code and the assembly that is associated (for example, data structure and other code components or be used for the assembly of run time version) can be stored in the readable proper data storer of treatment facility (for example, being commonly referred to computer-readable medium).
In the process disclosed herein, frame enumerate the order only be the example of proper method.Therefore, the operation that is associated with this frame can be arranged again, remains in the scope of the present disclosure simultaneously.Similarly, appended claim to a method has presented the operation according to sample order, and needn't be limited to the particular order that is appeared.
Assembly described here and function can be connected or are coupled through variety of way.In a way, the mode that realizes this purpose can partly depend on assembly whether and how with other components apart.In some embodiments, by some connection of lead-in wire expression in the accompanying drawing or coupling can be in integrated circuit, realize on the circuit board or as the lead of separation or with some other mode.
Here the signal of being discussed can adopt various forms.For example, in some embodiments, signal can comprise through lead carry out the electrons transmitted signal, the light pulse transmitted through the optical medium such as optical fiber or air or RF ripple of transmitting through the medium such as air interface etc.In addition, can a plurality of signals be called signal jointly here.Above-mentioned signal can also adopt the form of data.For example, in some embodiments, application program can be sent signal to the Another Application program.Can sort signal be stored in the data-carrier store.
Equally, should be appreciated that and use such as " first ", " second " any quantity or order that does not limit these elements usually of quoting of specifying here element.But these appointments can be herein as the short-cut method of between two or more elements or element instance, distinguishing.Therefore, quoting of first and second elements do not meant that only can adopt two elements, do not mean that perhaps first element must occupy before second element with some mode.Equally, except as otherwise noted, element set can comprise one or more elements.
Though it only is explanation rather than the restriction to instruction here that some sample embodiment, should be appreciated that this embodiment in above-detailed and shown in the drawings.Especially, should be realized that the instruction here can be applied to various equipment and method.Therefore, can make various modifications to shown embodiment and other embodiments of being instructed here, and not break away from wherein invention scope widely recognizing.In view of mentioned above, should be appreciated that the instruction here is not limited to specific embodiment or disclosed arrangement, and be intended to cover any change, adjustment or the modification in the appended claims scope.
Claims (22)
1. method of operating that is used to dispatch storer comprises:
Confirm that the driver that is associated with bidirectional data signal paths has enough to meet the need the timing of period; And
Dispatch the transmission of memory requests based on the timing of confirming, the scheduling of wherein said transmission comprises the transmission time of selecting to be used for said memory requests, and the said transmission time does not coincide with the said driver turnover period.
2. method according to claim 1, the scheduling of wherein said transmission comprises:
The idle time slot of identification request channel, the timing of wherein said idle time slot is before said driver has enough to meet the need the period; And
During said idle time slot, dispatch the transmission of said memory requests.
3. method according to claim 1 further comprises and sends the indication that said memory requests will postpone.
4. method according to claim 1, the wherein said driver turnover period relates to:
On said bidirectional data signal paths from reading the conversion that writes; Perhaps
On said bidirectional data signal paths from being written to the conversion of reading.
5. apparatus operating that is used to dispatch storer comprises:
The turnaround event detecting device, it is configured to confirm that the driver that is associated with bidirectional data signal paths has enough to meet the need the timing of period; And
Scheduler, it is configured to dispatch based on the timing of confirming the transmission of memory requests, and wherein said scheduler further is configured to select to be used for the transmission time of said memory requests, and the said transmission time does not coincide with the said driver turnover period.
6. equipment according to claim 5, wherein said scheduler further is configured to:
The idle time slot of identification request channel, the timing of wherein said idle time slot is before said driver has enough to meet the need the period; And
During said idle time slot, dispatch the transmission of said memory requests.
7. equipment according to claim 5 comprises that further request postpones indicator, and it is configured to send the indication that said memory requests will postpone.
8. equipment according to claim 5, the wherein said driver turnover period relates to:
On said bidirectional data signal paths from reading the conversion that writes; Perhaps
On said bidirectional data signal paths from being written to the conversion of reading.
9. method of operating that is used to dispatch storer comprises:
Reception memorizer request, said memory requests are scheduled as the turnaround event that is associated with bidirectional data signal paths of getting along well and coincide, and wherein said memory requests was received before said turnaround event; And
Postpone said memory requests.
10. method according to claim 9 comprises further and detects said turnaround event that wherein the result according to said detection postpones said memory requests.
11. method according to claim 9 comprises further receiving the indication that said memory requests will postpone that wherein said delay is based on said indication.
12. method according to claim 9, wherein said delay is based on the predefined delay period.
13. method according to claim 9 further comprises the timing of confirming said turnaround event, wherein said delay is based on the timing of confirming.
14. method according to claim 9 comprises further and detects said turnaround event that the said delay of wherein said memory requests makes moves to said memory requests after turnaround event begins.
15. method according to claim 9, wherein said turnaround event relate to the driver turnover period that is used for bidirectional signal paths.
16. an apparatus operating that is used to dispatch storer comprises:
Memory accessing controller, it is configured to the reception memorizer request, and said memory requests is scheduled as the turnaround event that is associated with bidirectional data signal paths of getting along well and coincides, and wherein said memory requests was received before said turnaround event; And
The request delayer, it is configured to postpone said memory requests.
17. equipment according to claim 16 further comprises the turnaround event detecting device, it is configured to detect said turnaround event, and wherein the result according to said detection postpones said memory requests.
18. equipment according to claim 16 comprises that further request postpones indicator, it is configured to receive the indication that said memory requests will postpone, and wherein said request delayer further is configured to postpone based on said indication.
19. equipment according to claim 16, wherein said request delayer further are configured to postpone based on the predefined delay period.
20. equipment according to claim 16 further comprises the turnaround event detecting device, it is configured to confirm the timing of said turnaround event, and wherein said request delayer further is configured to postpone based on the timing of confirming.
21. equipment according to claim 16 further comprises the turnaround event detecting device, it is configured to detect said turnaround event, and the said delay of wherein said memory requests makes moves to said memory requests after turnaround event begins.
22. equipment according to claim 16, wherein said turnaround event relate to the driver turnover period that is used for bidirectional signal paths.
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US98887807P | 2007-11-19 | 2007-11-19 | |
| US60/988,878 | 2007-11-19 | ||
| PCT/US2008/084003 WO2009067496A1 (en) | 2007-11-19 | 2008-11-19 | Scheduling based on turnaround event |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN101868788A CN101868788A (en) | 2010-10-20 |
| CN101868788B true CN101868788B (en) | 2012-12-26 |
Family
ID=40385138
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN200880116498.0A Active CN101868788B (en) | 2007-11-19 | 2008-11-19 | Scheduling based on turnaround event |
Country Status (7)
| Country | Link |
|---|---|
| US (1) | US20100293343A1 (en) |
| EP (1) | EP2223224B1 (en) |
| JP (1) | JP2011503753A (en) |
| KR (1) | KR20100098622A (en) |
| CN (1) | CN101868788B (en) |
| AT (1) | ATE511676T1 (en) |
| WO (1) | WO2009067496A1 (en) |
Families Citing this family (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR101700492B1 (en) * | 2012-03-26 | 2017-01-26 | 인텔 코포레이션 | Timing optimization for memory devices employing error detection coded transactions |
| US9740485B2 (en) | 2012-10-26 | 2017-08-22 | Micron Technology, Inc. | Apparatuses and methods for memory operations having variable latencies |
| US9754648B2 (en) * | 2012-10-26 | 2017-09-05 | Micron Technology, Inc. | Apparatuses and methods for memory operations having variable latencies |
| US9734097B2 (en) | 2013-03-15 | 2017-08-15 | Micron Technology, Inc. | Apparatuses and methods for variable latency memory operations |
| US9727493B2 (en) | 2013-08-14 | 2017-08-08 | Micron Technology, Inc. | Apparatuses and methods for providing data to a configurable storage area |
| CN104866238B (en) | 2015-05-25 | 2018-12-14 | 华为技术有限公司 | Access request dispatching method and device |
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| US5903916A (en) * | 1996-12-16 | 1999-05-11 | Intel Corporation | Computer memory subsystem and method for performing opportunistic write data transfers during an access latency period within a read or refresh operation |
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| US7187572B2 (en) * | 2002-06-28 | 2007-03-06 | Rambus Inc. | Early read after write operation memory device, system and method |
| US5819027A (en) * | 1996-02-28 | 1998-10-06 | Intel Corporation | Bus patcher |
| US6272600B1 (en) * | 1996-11-15 | 2001-08-07 | Hyundai Electronics America | Memory request reordering in a data processing system |
| US7610447B2 (en) * | 2001-02-28 | 2009-10-27 | Rambus Inc. | Upgradable memory system with reconfigurable interconnect |
| US6889304B2 (en) * | 2001-02-28 | 2005-05-03 | Rambus Inc. | Memory device supporting a dynamically configurable core organization |
| US6785793B2 (en) * | 2001-09-27 | 2004-08-31 | Intel Corporation | Method and apparatus for memory access scheduling to reduce memory access latency |
| US7149841B2 (en) * | 2003-03-31 | 2006-12-12 | Micron Technology, Inc. | Memory devices with buffered command address bus |
| US8595459B2 (en) * | 2004-11-29 | 2013-11-26 | Rambus Inc. | Micro-threaded memory |
| US7464225B2 (en) * | 2005-09-26 | 2008-12-09 | Rambus Inc. | Memory module including a plurality of integrated circuit memory devices and a plurality of buffer devices in a matrix topology |
| WO2007095080A2 (en) * | 2006-02-09 | 2007-08-23 | Metaram, Inc. | Memory circuit system and method |
| US7613883B2 (en) * | 2006-03-10 | 2009-11-03 | Rambus Inc. | Memory device with mode-selectable prefetch and clock-to-core timing |
| JP2008033657A (en) * | 2006-07-28 | 2008-02-14 | Toshiba Corp | Memory control device, information processor and memory control method |
-
2008
- 2008-11-19 CN CN200880116498.0A patent/CN101868788B/en active Active
- 2008-11-19 JP JP2010534276A patent/JP2011503753A/en active Pending
- 2008-11-19 KR KR1020107012483A patent/KR20100098622A/en not_active Application Discontinuation
- 2008-11-19 EP EP08851995A patent/EP2223224B1/en active Active
- 2008-11-19 WO PCT/US2008/084003 patent/WO2009067496A1/en active Application Filing
- 2008-11-19 AT AT08851995T patent/ATE511676T1/en not_active IP Right Cessation
- 2008-11-19 US US12/743,565 patent/US20100293343A1/en not_active Abandoned
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5903916A (en) * | 1996-12-16 | 1999-05-11 | Intel Corporation | Computer memory subsystem and method for performing opportunistic write data transfers during an access latency period within a read or refresh operation |
Also Published As
| Publication number | Publication date |
|---|---|
| CN101868788A (en) | 2010-10-20 |
| US20100293343A1 (en) | 2010-11-18 |
| EP2223224B1 (en) | 2011-06-01 |
| EP2223224A1 (en) | 2010-09-01 |
| WO2009067496A4 (en) | 2009-07-16 |
| JP2011503753A (en) | 2011-01-27 |
| ATE511676T1 (en) | 2011-06-15 |
| KR20100098622A (en) | 2010-09-08 |
| WO2009067496A1 (en) | 2009-05-28 |
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