CN101866690B - Method for using thin film transistor (TFT) as nonvolatile memory - Google Patents
Method for using thin film transistor (TFT) as nonvolatile memory Download PDFInfo
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- CN101866690B CN101866690B CN 200910130080 CN200910130080A CN101866690B CN 101866690 B CN101866690 B CN 101866690B CN 200910130080 CN200910130080 CN 200910130080 CN 200910130080 A CN200910130080 A CN 200910130080A CN 101866690 B CN101866690 B CN 101866690B
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Abstract
The invention discloses a method for using the substrate storage charge of a thin film transistor (TFT) and a device thereof. The thin film transistor TFT is electrically operated and the common element of thin film transistor TFT is used as the memory unit of the nonvolatile memory so that the device such as the logic circuit or TFT-LCD pixel transistor, and the like which is formed by the nonvolatile memory and the common element of TFT can be integrated on a plane without adopting the additional process.
Description
Technical field
The present invention relates to a kind of method and device thereof that utilizes membrane transistor (TFT) substrate store charge as nonvolatile memory, particularly utilize the electrical method of operating of membrane transistor (TFT), and use the storage unit of general membrane transistor (TFT) as nonvolatile memory.
Background technology
In recent years, because flat-panel screens is used on the electronic products such as computer, TV and communication widely, also more and more higher for the flat-panel screens performance demands, the circuit of display periphery is produced on low temperature polycrystalline silicon (LTPS) the TFT-LCD panel simultaneously, can reaches the purpose of system combination.Wherein, use membrane transistor (TFT) as nonvolatile memory, especially system combination important step.
At present nonvolatile memory is integrated in the technology on the panel, major part is that general membrane transistor (TFT) structure is changed, with store charge.Please refer to U.S. Patent Publication No. US20040206957 " semiconductor device and manufacture method thereof " and United States Patent (USP) notification number US6005270 " semiconductor nonvolatile memory device and manufacture method thereof " is with the prior art of TFT as nonvolatile memory.U.S. Patent Publication No. US20040206957 scatters silicon grain (silicon particles) to be used for mending and to catch electric charge on the grid oxic horizon of general membrane transistor (TFT), be covered with one deck second grid oxide layer again; United States Patent (USP) notification number US6005270 increases an electric charge storage layer (charging storing layer) with store charge between the grid of general membrane transistor (TFT) and gate insulator.
Yet, above-mentioned and other similar increase floating grids (floating gate) or penetrate oxide layer means such as (tunneling oxide), processing procedure is than general membrane transistor (TFT) complexity, so cost of manufacture is higher.In addition, in the time of the electronic component microminiaturization, penetrating oxide layer also will microminiaturization, and the hold capacity of storer may have problems.Therefore, existing with the technology of general membrane transistor (TFT) as nonvolatile memory, still have problem to need to be resolved hurrily.
Summary of the invention
Purpose of the present invention is providing a kind of method of utilizing membrane transistor (TFT) substrate store charge as nonvolatile memory, it is an electrical method of operating of utilizing membrane transistor (TFT), membrane transistor (TFT) can produce self-heating phenomena and produce electron hole pair when conducting, after the vertical electric field of grid separates electron hole pair, electric charge is injected and is stored into the substrate of membrane transistor (TFT), finish and write, can apply to nonvolatile memory, be beneficial to that element constituted as logical circuit with general membrane transistor (TFT), device such as LCD base plate array is integrated mutually, and need not to increase extra processing procedure.
Another purpose of the present invention is providing a kind of non-volatile memory device that utilizes membrane transistor (TFT) as storage unit, and further is integrated on the same substrate with other general membrane transistor (TFT) elements, and does not need to increase extra processing procedure.
Utilize the method for membrane transistor (TFT) substrate store charge for reaching aforementioned purpose the present invention as nonvolatile memory, wherein a membrane transistor (TFT) is that a substrate and two ends are respectively a drain electrode in the middle of having, the semi-conductor layer of one source pole, be arranged on the substrate with an insulating surface, one gate insulator is arranged on this semiconductor layer, and one grid be arranged on this gate insulator, this utilizes membrane transistor (TFT) substrate store charge to comprise as the method for nonvolatile memory: a write activity, its drain electrode that is included in this membrane transistor applies one first drain voltage, grid at this membrane transistor applies a grid voltage, and with the source ground of this membrane transistor, wherein, when Jiao Erre (Joule heating is the product of drain current and drain voltage) that this grid voltage and this drain voltage produced is enough to cause oneself's heating (self-heating) effect, majority carrier in this membrane transistor is injected the substrate of this membrane transistor, and cause this membrane transistor starting potential to change, finish write activity; An and erasing move, its drain electrode that is included in this membrane transistor applies one second drain voltage, source electrode at this membrane transistor applies one source pole voltage, and with the grounded-grid of this membrane transistor, wherein, this source electrode and between the two bias voltage of second drain electrode remove the majority carrier in the semiconductor layer of this storer in substrate.
Another embodiment of the present invention is a kind ofly to be applied to utilize membrane transistor (TFT) as the method for deleting of the non-volatile memory device of storage unit and the non-volatile memory device of wiring method, it comprises a storer, be used for access data, it comprises at least one storage unit and is constituted with array way, this storage unit comprises semi-conductor layer and is arranged on the substrate with an insulating surface, one gate insulator is arranged on this semiconductor layer, and a grid is arranged on this gate insulator; One logical circuit, be used for control data, wherein, this semiconductor layer of this storage unit is made of a substrate and the one source pole and the drain electrode institute that lay respectively at these substrate two ends, this storage unit is general membrane transistor (TFT) structure, and this storer and this logical circuit are integrated on the aforesaid base plate.
Description of drawings
Fig. 1 is the present invention first preferred embodiment element section figure;
Fig. 2 is that the present invention's first preferred embodiment writes the voltage synoptic diagram;
Fig. 3 is the present invention's first preferred embodiment erasing voltage synoptic diagram;
Fig. 4 is the present invention's second preferred embodiment nonvolatile memory synoptic diagram;
Fig. 5 is the present invention's second preferred embodiment memory cell array synoptic diagram;
Fig. 6 is the present invention's second preferred embodiment storage unit sectional view;
Fig. 7 is that synoptic diagram is integrated in the present invention's second preferred embodiment.
Embodiment
Relevant the present invention is for reaching above-mentioned purpose, and technological means that is adopted and effect thereof are lifted preferred embodiment now, and conjunction with figs. is illustrated as follows:
Please refer to Fig. 1, be the present invention first preferred embodiment element section figure.As shown in Figure 1, the present invention utilizes a membrane transistor 10, it in the middle of wherein this membrane transistor 10 has the semi-conductor layer 20 that a substrate 21 and two ends are respectively a drain electrode 22, one source pole 23, be arranged on the substrate 30 with an insulating surface 31, one gate insulator 41 is arranged on this semiconductor layer 20, and one grid 40 be arranged on this gate insulator 41, Charge Storage of the present invention comprises a write activity and an erasing move in the method for membrane transistor 10 substrates 21.
With reference to figure 2, Fig. 2 writes the voltage synoptic diagram for the present invention's first preferred embodiment again.As shown in Figure 2, wherein, this write activity is that the drain electrode 22 at this membrane transistor 10 applies a drain voltage, and in the present embodiment, this drain voltage is 15 volts; Grid 40 at this membrane transistor 10 applies a grid voltage simultaneously, and in the present embodiment, this grid voltage is 25 volts; And with source electrode 23 ground connection of this membrane transistor 10, wherein, when Jiao Erre (Joule heating is the product of drain current and drain voltage) that this grid voltage and this drain voltage produced is enough to cause oneself's heating (self-heating) effect, this moment, electronics was under the electric field action of this grid 40, can be emitted to conduction band (conductor band) by the valence band (valence band) of semiconductor layer 20 by thermal field emission (thermion fieldemission) and produce electron hole pair (electron-hole pair), electron hole pair can be separated by the vertical electric field of this grid 40, this substrate 21 that majority carrier (is the hole with the n passage) injects this membrane transistor 10, and cause this membrane transistor starting potential (threshold voltage) to change, finish write activity, the present embodiment data instance, with the n passage, write activity is 1 millisecond of time, and memory window (memorywindow) can reach 3V.
Please refer to Fig. 3, Fig. 3 is the present invention's first preferred embodiment erasing voltage synoptic diagram.As shown in Figure 3, wherein, this erasing move is that the drain electrode 22 at this membrane transistor 10 applies a drain voltage, and in the present embodiment, this drain voltage is-5 volts; Source electrode 23 at this membrane transistor 10 applies one source pole voltage simultaneously, and in the present embodiment, this source voltage is 10 volts; And with grid 40 ground connection of this membrane transistor 10, wherein, voltage difference between this drain voltage and this source voltage, when being enough to allow majority carrier in this substrate 21 overcome the energy barrier (energy barrier) that crystal boundary in the substrate (grain boundary) made, bias voltage removes the majority carrier in the semiconductor layer 20 of this membrane transistor 10 in this substrate 21 between the two, finishes erasing move, with the present embodiment data instance, with the n passage, the erasing move time is 0.1 second.
Please refer to Fig. 4 and Fig. 5, Fig. 4 is the present invention's second preferred embodiment nonvolatile memory synoptic diagram, and Fig. 5 is the present invention's second preferred embodiment memory cell array synoptic diagram.As shown in Figure 4, the present invention utilizes the non-volatile memory device of a membrane transistor as storage unit, this non-volatile memory device comprises that a storer 110 is used for access data and a logical circuit 60 is used for control data, this logical circuit 60 is made up of at least one membrane transistor (TFT), and with this storer 110, be integrated on this substrate 30, as shown in Figure 5, this storer 110 is made of with array way at least one storage unit 100, and a data write activity and data erase action are provided.
With reference to figure 6, Fig. 6 is the present invention's second preferred embodiment storage unit sectional view again.As shown in Figure 6, this storage unit 100, comprise that semi-conductor layer 20 is arranged on the substrate 30 with an insulating surface 31, one gate insulator 41 is arranged on this semiconductor layer 20, and one grid 40 be arranged on this gate insulator 41, wherein, this semiconductor layer 20 by a substrate 21 and lay respectively at these substrate 21 two ends one source pole 23 and one the drain electrode 22 constitute, and this storage unit 100 is general membrane transistor (TFT) structure, coated by an insulating film of intermediate layer 50 on it, and form relevant circuit binding by metal level 51.
When carrying out write activity, be that drain electrode 22 in this storage unit 100 applies a drain voltage, grid 40 in this storage unit 100 applies a grid voltage simultaneously, and with source electrode 23 ground connection of this storage unit 100, wherein, when Jiao Erre (Jouleheating is the product of drain current and drain voltage) that this grid voltage and this drain voltage produced is enough to cause oneself's heating (self-heating) effect, this moment, electronics was under the electric field action of this grid 40, can be emitted to conduction band (conductor band) by the valence band (valence band) of semiconductor layer 20 by thermal field emission (thermion field emission) and produce electron hole pair (electron-hole pair), electron hole pair can be separated by the vertical electric field of this grid 40, this substrate 21 that majority carrier (is the hole with the n passage) injects this storage unit 100, and cause this storage unit starting potential (threshold voltage) to change, finish write activity.
When carrying out erasing move, be that drain electrode 22 in this storage unit 100 applies a drain voltage, source electrode 23 at this membrane transistor 10 applies one source pole voltage simultaneously, and with grid 40 ground connection of this storage unit 100, wherein, voltage difference between this drain voltage and this source voltage, when being enough to allow majority carrier in this substrate 21 overcome the energy barrier (energy barrier) that crystal boundary in the substrate (grain boundary) made, bias voltage removes the majority carrier in the semiconductor layer 20 of this storage unit 100 in this substrate 21 between the two, finishes erasing move.
Please refer to Fig. 7, Fig. 7 integrates synoptic diagram for the present invention's second preferred embodiment.As shown in Figure 7, nonvolatile memory of the present invention can further combine with the general liquid crystal pixel membrane transistor 70 of same process, be integrated on this substrate 30, and this substrate can be the low temperature polycrystalline silicon glass substrate.
Be with, a kind of method and device thereof that utilizes membrane transistor (TFT) substrate store charge as nonvolatile memory provided by the present invention, make the nonvolatile memory can be in conjunction with flat-panel screens or LCD (Liquid Crystal Display LCD), be integrated on the panel, and only need utilize general membrane transistor (TFT) structure, do not need extra floating grid (floating gate) or penetrate oxide layer (tunneling oxide) to come store charge, therefore can reduce the processing procedure of storer, and then the cost of manufacture of reduction storer, be beneficial to the use of related industry, so the present invention has progressive and meets the important document of applying for patent of invention.
Below the present invention has been done a detailed description, only the above person only is a preferred embodiment of the present invention, when not limiting scope of the invention process.Be that all equalizations of doing according to the present patent application scope change and modify etc., all should still belong in the patent covering scope of the present invention.
Claims (13)
1. a Charge Storage is in the method for membrane transistor substrate, it is characterized in that, it in the middle of one membrane transistor has the semi-conductor layer that a substrate and two ends are respectively a drain electrode, one source pole, be arranged on the substrate with an insulating surface, one gate insulator is arranged on this semiconductor layer, and one grid be arranged on this gate insulator, this Charge Storage comprises in the method for membrane transistor substrate:
One write activity, its drain electrode that is included in this membrane transistor applies one first drain voltage, grid at this membrane transistor applies a grid voltage, and with the source ground of this membrane transistor, wherein, the Jiao Erre that is produced when this grid voltage and this first drain voltage, be enough to cause self-heating effect, majority carrier in this membrane transistor injects the substrate of this membrane transistor, and causes this membrane transistor starting potential to change, and finishes write activity; And
One erasing move, its drain electrode that is included in this membrane transistor applies one second drain voltage, source electrode at this membrane transistor applies one source pole voltage, and with the grounded-grid of this membrane transistor, wherein, voltage difference between this second drain voltage and this source voltage, when being enough to allow majority carrier in this substrate overcome the energy barrier that crystal boundary is made in this substrate, bias voltage removes the majority carrier in this semiconductor layer in substrate between the two.
2. a kind of Charge Storage as claimed in claim 1 is characterized in that in the method for membrane transistor substrate this grid voltage and this first drain voltage are positive voltage.
3. a kind of Charge Storage as claimed in claim 1 is characterized in that in the method for membrane transistor substrate this membrane transistor is integrated on the same substrate with the element that general membrane transistor constitutes.
4. a method for deleting that is applied to non-volatile memory device is characterized in that, this non-volatile memory device comprises:
One storer, be used for access data, it comprises at least one storage unit and is constituted with array way, and this storage unit comprises semi-conductor layer and is arranged on the substrate with an insulating surface, one gate insulator is arranged on this semiconductor layer, and a grid is arranged on this gate insulator;
One logical circuit, be used for control data, wherein, this semiconductor layer of this storage unit is made of a substrate and the one source pole and the drain electrode institute that lay respectively at these substrate two ends, this storage unit is general thin-film transistor structure, and this storer and this logical circuit are integrated on the described substrate;
This method for deleting comprises: the drain electrode at this membrane transistor applies a drain voltage, source electrode at this membrane transistor applies one source pole voltage, and with the grounded-grid of this membrane transistor, wherein, voltage difference between this drain voltage and this source voltage, when being enough to allow majority carrier in this substrate overcome the energy barrier that crystal boundary is made in the substrate, bias voltage removes the majority carrier in this semiconductor layer in substrate between the two, finishes erasing move.
5. a kind of method for deleting that is applied to non-volatile memory device as claimed in claim 4 is characterized in that, this drain voltage is 10 volts positive voltage for this source voltage of negative voltage of-5 volts.
6. a kind of method for deleting that is applied to non-volatile memory device as claimed in claim 4 is characterized in that this logical circuit comprises at least one membrane transistor, and this membrane transistor and this storer are integrated on this substrate.
7. a kind of method for deleting that is applied to non-volatile memory device as claimed in claim 4 is characterized in that this substrate is the low temperature polycrystalline silicon substrate.
8. a kind of method for deleting that is applied to non-volatile memory device as claimed in claim 4 is characterized in that, this nonvolatile memory combines with the general panel of LCD of same process, is integrated on the same low temperature polycrystalline silicon substrate.
9. a wiring method that is applied to non-volatile memory device is characterized in that, this non-volatile memory device comprises:
One storer, be used for access data, it comprises at least one storage unit and is constituted with array way, and this storage unit comprises semi-conductor layer and is arranged on the substrate with an insulating surface, one gate insulator is arranged on this semiconductor layer, and a grid is arranged on this gate insulator; And
One logical circuit, be used for control data, wherein, this semiconductor layer of this storage unit is made of a substrate and the one source pole and the drain electrode institute that lay respectively at these substrate two ends, this storage unit is general thin-film transistor structure, and this storer and this logical circuit are integrated on the described substrate;
Wherein this wiring method comprises: the drain electrode at this membrane transistor applies a drain voltage, grid at this membrane transistor applies a grid voltage, and with the source ground of this membrane transistor, wherein, as the Jiao Erre that this grid voltage and this drain voltage produced, be enough to cause self-heating effect, the majority carrier in this membrane transistor injects the substrate of this membrane transistor, and cause this membrane transistor starting potential to change, finish write activity.
10. a kind of wiring method that is applied to non-volatile memory device as claimed in claim 9 is characterized in that this drain voltage and this grid voltage are positive voltage.
11. a kind of wiring method that is applied to non-volatile memory device as claimed in claim 9 is characterized in that this logical circuit comprises at least one membrane transistor, and this membrane transistor and this storer are integrated on this substrate.
12. a kind of wiring method that is applied to non-volatile memory device as claimed in claim 9 is characterized in that this substrate is the low temperature polycrystalline silicon substrate.
13. a kind of wiring method that is applied to non-volatile memory device as claimed in claim 9 is characterized in that, this nonvolatile memory combines with the general panel of LCD of same process, is integrated on the same low temperature polycrystalline silicon substrate.
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| CN 200910130080 CN101866690B (en) | 2009-04-14 | 2009-04-14 | Method for using thin film transistor (TFT) as nonvolatile memory |
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| CN 200910130080 CN101866690B (en) | 2009-04-14 | 2009-04-14 | Method for using thin film transistor (TFT) as nonvolatile memory |
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| CN101866690B true CN101866690B (en) | 2013-07-24 |
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| CN107301879B (en) * | 2016-04-15 | 2020-06-02 | 东南大学 | Application of thin film transistor with adjustable threshold voltage as nonvolatile memory |
| CN113451309A (en) | 2020-03-25 | 2021-09-28 | 长鑫存储技术有限公司 | Semiconductor structure and preheating method thereof |
Citations (4)
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|---|---|---|---|---|
| US5572461A (en) * | 1995-02-14 | 1996-11-05 | Micron Technology, Inc. | Static random access memory cell having a capacitor and a capacitor charge maintenance circuit |
| US6849905B2 (en) * | 2002-12-23 | 2005-02-01 | Matrix Semiconductor, Inc. | Semiconductor device with localized charge storage dielectric and method of making same |
| CN101093839A (en) * | 2006-06-21 | 2007-12-26 | 旺宏电子股份有限公司 | Memory devices |
| JP2008166748A (en) * | 2006-12-05 | 2008-07-17 | Semiconductor Energy Lab Co Ltd | Manufacturing method of semiconductor device |
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Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5572461A (en) * | 1995-02-14 | 1996-11-05 | Micron Technology, Inc. | Static random access memory cell having a capacitor and a capacitor charge maintenance circuit |
| US6849905B2 (en) * | 2002-12-23 | 2005-02-01 | Matrix Semiconductor, Inc. | Semiconductor device with localized charge storage dielectric and method of making same |
| CN101093839A (en) * | 2006-06-21 | 2007-12-26 | 旺宏电子股份有限公司 | Memory devices |
| JP2008166748A (en) * | 2006-12-05 | 2008-07-17 | Semiconductor Energy Lab Co Ltd | Manufacturing method of semiconductor device |
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