CN101866604A - Multi-partition pixel drive circuit and method thereof - Google Patents
Multi-partition pixel drive circuit and method thereof Download PDFInfo
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- CN101866604A CN101866604A CN 201010127482 CN201010127482A CN101866604A CN 101866604 A CN101866604 A CN 101866604A CN 201010127482 CN201010127482 CN 201010127482 CN 201010127482 A CN201010127482 A CN 201010127482A CN 101866604 A CN101866604 A CN 101866604A
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Abstract
A kind of multi-partition pixel drive circuit disclosed in this invention, comprise: the multi-partition pixel array, comprise plural main pixel, plural number time pixel, a plurality of sweep traces and a plurality of data lines, wherein the multi-partition pixel array comprises a virtual scan line, lists in after a plurality of sweep traces; And a distribution, between article one sweep trace and virtual scan line of a plurality of sweep traces that are coupled, the last item sweep trace that is beneficial to a plurality of sweep traces gets normally and shows.
Description
Technical field
The present invention is about a kind of pixel-driving circuit and method thereof, particularly relevant for a kind of multi-partition pixel drive circuit and method thereof.
Background technology
Along with the progress of optics science and technology with semiconductor technology, display panels has been widely used on the electronic product display panel.Advantages such as LCD has that high image quality, volume are little, in light weight, low voltage drive, low consumpting power and applied range, it has replaced the mainstream technology that traditional cathode-ray tube (CRT) becomes display.
Generally speaking, display panels (LCD) comprises two substrates and has liquid crystal to be sealed in therebetween, pixel electrode and thin film transistor (TFT) (TFT) are set on the substrate, and are set on another substrate with respect to the common electrode that the color filter film and of each pixel electrode is shared on each pixel.Color filter film comprises red (R), green (G), blue (B) three kinds, and can be provided with a kind of filter coating in these three kinds of colors in each pixel.The mutual neighbour of red, green, blue color pixel establishes and constitutes a pixel together.
With development of technologies, industry has had multi partition vertical orientation (the Multi-domain Vertical Alignment of preferable viewing angle characteristic; MVA) formula LCD, this technology also is applied on the liquid crystal display television, and technical characterictic is that it cuts apart a pixel is four subregions (4domain).The LCD of multi partition vertical orientation technology manufacturing has advantages such as high contrast, wide viewing angle and large scale compatibility, but its LCD screen is in the comparison of forward sight and side-looking, can find still that side-looking produces to appear in one's mind in vain resembles (color washout), and response time is slower, and this will reduce the quality of image of multi partition vertical alignment mode.Reduce colour cast, the method for full blast can adopt octant (8domain) technology to solve, and promptly pixel partitions is increased to 8 subregions or more from 4 subregions.It can utilize capacitive coupling type (CapacitanceCoupling type, C-C type), Double Data or double grid type (T-T type) and common voltage swing (common voltage swinging, Com-swing) technology and produce 8 subregion pixels.Therefore Double Data or double grid type (T-T type) and the common voltage extra circuit signal of Technology Need (being produced by integrated circuit and electronic component) that swings has wherein increased the cost in loop.Though capacitive coupling type technology can not increase manufacturing cost, because its floating electrode from the electric capacity that is coupled can cause serious image residue.
Multi partition vertical alignment mode (the AMVA of the enhancing of technology formerly, Advanced-MVA mode) in, please refer to the SID periodical 2007 18.3, a kind of additional renewal technology (ART of its teaching, AdditionalRefresh Technology), it is cut apart pixel and is that primary area and time district are to provide the octant pixel.Additional renewal technology is that the octant pixel of utilizing autoacceleration to drive (self-overdriving) reduces to appear in one's mind in vain and resembles and shorten response time.
In addition, please refer to Fig. 1, be depicted as existing 8 subregion image element circuit frameworks, comprise main pixel (Mainpixel) A and time pixel (Sub pixel) B, main thin film transistor (TFT) 50 and electric capacity 61,62 are arranged in the main pixel A, and having inferior thin film transistor (TFT) 60 and electric capacity 63,64, data line 10 to be connected in the inferior pixel B with sweep trace 30, voltage concussion line 20 is connected data line 10 and connects electric capacity 61 and 63 respectively with 40.This principle is at main pixel A and time pixel B, utilizes different voltage oscillator signals, makes winner's pixel reach the effect of 8 subregion pixels with voltage difference that time the pixel generation is different.
The shortcoming of above-mentioned traditional design is: (1). complex circuit designs, (2). and common voltage concussion (CS) signal is interchange (AC) signal, and this will cause the load of exerting oneself of integrated circuit (IC) end heavier, and cost improves; (3). the pixel of capacitive coupling type is burnt the problem of paying because of (Floating) electrode structure of floating has; (4). the common voltage kenel that swings has more serious stravismus reddish yellow band.
Therefore, in response to the swing shortcoming of design of common voltage, the invention provides a kind of embodiment that is better than the new 8 subregion pixels of known technology, it is the incomparable person of known technology, and can increase liquid crystal display usefulness effectively.
Summary of the invention
In order to overcome the known technology problem, the invention provides a kind of pixel-driving circuit and method thereof of display panel of octant pixel, to solve the problem of display panel the last item sweep trace (Gate line) display abnormality.
A further object of the present invention provides a kind of multi-partition pixel driving method, and described method is to utilize a distribution to connect article one sweep trace and virtual scan line, and display panel the last item sweep trace can normally be shown.
Another purpose of the present invention provides a kind of multi-partition pixel driving method, and described method need not increase additional circuit signal or loop end newly, and can reach the effect of multi-partition pixel.
A kind of multi-partition pixel drive circuit disclosed in this invention comprises; One article one sweep trace is coupled to a data line; One virtual scan line is coupled to data line; And a distribution, coupling article one sweep trace and virtual scan line.
The present invention discloses a kind of multi-partition pixel drive circuit, comprise a multi-partition pixel array, comprise plural main pixel, plural number time pixel, a plurality of sweep traces and a plurality of data lines, wherein m is listed as, the pixel that n is capable comprises the first main pixel and the pixel first time, wherein the first main pixel comprises a main pixel thin film transistor, first pixel capacitance and first storage capacitors are arranged in this main pixel, and wherein main pixel thin film transistor has the first grid m bar sweep trace that is coupled, the first source-coupled n bar data line, first drain coupled, first pixel capacitance and first storage capacitors; The above-mentioned pixel first time comprises first and second thin film transistor (TFT), second pixel capacitance, second storage capacitors and the 3rd storage capacitors, be arranged in this time pixel, wherein this, thin film transistor (TFT) had the second grid m bar sweep trace that is coupled first time, have the second source-coupled n bar data line data line, thin film transistor (TFT) has second drain coupled to the second pixel capacitance, second storage capacitors, the 3rd storage capacitors for the first time; Thin film transistor (TFT) has between the 3rd gate coupled (m+1) bar sweep trace, second drain electrode of the 3rd source-coupled and second pixel capacitance for the second time, has between the 3rd drain coupled the 3rd storage capacitors and the 4th storage capacitors; Wherein multi partition parallel circuit array comprises a virtual scan line, lists in after a plurality of sweep traces; And a distribution, between article one sweep trace and virtual scan line of a plurality of sweep traces that are coupled, the last item sweep trace that is beneficial to a plurality of sweep traces gets normally and shows.
Multi-partition pixel drive circuit of the present invention also comprises the last item sweep trace n bar data line that is coupled.Above-mentioned pixel-driving circuit also comprises: one second main thin film transistor (TFT) is arranged in one second main pixel, its gate coupled the last item sweep trace, its source-coupled n bar data line, its drain coupled the 3rd pixel capacitance and the 5th storage capacitors; No. one the 1 thin film transistor (TFT) is arranged in a pixel for the second time, its gate coupled the last item sweep trace, its source-coupled n bar data line, its drain coupled the 4th pixel capacitance, the 6th storage capacitors and the 7th storage capacitors; And No. one the 4th thin film transistor (TFT), being arranged in pixel for the second time, its gate coupled virtual scan line is between its source-coupled the 5th drain electrode and the 4th pixel capacitance, between its drain coupled the 6th storage capacitors and the 7th storage capacitors.Distribution is right edge or the limit, left side that is disposed at display panel, and wherein the distribution on this limit, left side is the virtual source polar curve.
Disclosed a kind of multi-partition pixel driving method, wherein this multi-partition pixel driving method is to see through a multi-partition pixel drive circuit to carry out, multi-partition pixel drive circuit comprises that a multi-partition pixel array comprises plural main pixel, plural number time pixel, a plurality of sweep traces, a plurality of data lines and a virtual scan line, each main pixel comprises a main thin film transistor (TFT), one first pixel capacitance and one first storage capacitors, pixel comprises one first and one thin film transistor (TFT) for the second time each time, one second pixel capacitance, one second storage capacitors, one the 3rd storage capacitors and one the 4th storage capacitors, virtual scan line wherein, list in after a plurality of sweep traces, this multi-partition pixel driving method comprises: make the scanning in regular turn from top to bottom of a plurality of sweep traces; When being scanned up to a m bar sweep trace, this m bar sweep trace is a noble potential, so that main thin film transistor (TFT) and thin film transistor (TFT) unlatching for the first time, then n bar data line charges to first pixel capacitance, first storage capacitors, second pixel capacitance, second storage capacitors, the 3rd storage capacitors and the 4th storage capacitors, and makes main pixel identical with the voltage of time pixel; When being scanned up to next article (m+1) bar sweep trace, then m bar sweep trace returns back to electronegative potential, main thin film transistor (TFT) and for the first time thin film transistor (TFT) close, and (m+1) bar sweep trace is a noble potential, so that for the second time thin film transistor (TFT) is opened and caused the second storage capacitors short circuit and cause main pixel different with the voltage of inferior pixel; And by being coupled a distribution between article one sweep trace and virtual scan line of a plurality of sweep traces, utilize scanning article one sweep trace, see through this distribution and be passed to virtual scan line to discharge with the signal with article one sweep trace, the last item sweep trace that is beneficial to a plurality of sweep traces gets normally and shows.
Description of drawings
Said elements, and further feature of the present invention and advantage, by the content of reading embodiment and graphic after, will be more obvious:
Fig. 1 is the equivalent circuit diagram of the display panel 8 subregion pixels of prior art.
Fig. 2 is the equivalent circuit diagram of one 8 subregion pixels in the display panel.
Fig. 3 is the equivalent circuit diagram of one 8 subregion pixels in the display panel of the present invention.
Fig. 4 is the synoptic diagram of an embodiment of display panel of the present invention.
Fig. 5 is the synoptic diagram of another embodiment of display panel of the present invention.
Embodiment
The present invention will cooperate its preferred embodiment and the diagram of enclosing to be specified in down.Should the person of understanding be that all preferred embodiments only are the usefulness of illustration among the present invention, be not in order to restriction.Therefore the preferred embodiment in literary composition, the present invention also can be widely used among other embodiment.And the present invention is not limited to any embodiment, should be with the claim scope of enclosing and equivalent fields thereof and decide.
In order to overcome the known technology problem, the invention provides a kind of pixel-driving circuit and method thereof of display panel of octant pixel, to solve the problem of display panel the last item sweep trace (Gate line) display abnormality.The invention provides a kind of display panel of octant pixel, can be applicable to wide viewing angle pixel (Wideviewing angle pixel).
Based on the shortcoming that display panel the last item sweep trace in the prior art can't normally show, it is auxiliary to need many virtual scan lines (Dummy gate line), and therefore must use the grid integrated circuits (gate IC) of special requirement.The present invention utilizes the lead that is connected that connects article one sweep trace (G1) and virtual scan line, display panel the last item sweep trace can normally be shown, and need not increase the cost of grid integrated circuits.
Fig. 2 is the equivalent circuit diagram of one 8 subregion pixels in the display panel.It is the shortcoming of (CS-Swing) design that swings in response to common voltage, the embodiment of a kind of new 8 subregion pixels that proposed.In the various embodiments of the present invention, identical constitutive requirements are repeated description or explanation not.In addition, embodiments of the invention only are used to illustrate that notion of the present invention is not the display panel that is used to limit the inventive method made.Display panel comprises but is not defined as LCD, plasma scope etc.
Be illustrated in figure 2 as the framework and the operation of 8 subregion pixel design, in 8 subregion pixel design, the grid of the main thin film transistor (TFT) (TFT) 100 in the main pixel A (Main Pixel) is to be electrically connected at m bar sweep trace Gm, its source electrode is to be electrically connected at n bar data line Sn, and its drain electrode then is electrically connected at Clca and Csta.Inferior thin film transistor (TFT) (sub-TFT) 101 and 102 in the inferior pixel B (Sub Pixel) has width/height (W/L) and the charging ratio different with main thin film transistor (TFT) 100 in image element circuit.Inferior thin film transistor (TFT) 101 grids are to be electrically connected at m bar sweep trace Gm, and its source electrode is to be electrically connected at n bar data line Sn, and its drain electrode then is electrically connected at Clcb, Cstc and Cstd.In addition, inferior thin film transistor (TFT) 102 grids are to be electrically connected at time one article of (m+1) bar sweep trace G (m+1), and its source electrode is to be electrically connected between 101 drain electrodes of time thin film transistor (TFT) and the Clcb, and its drain electrode is electrically connected between Cstc and the Cstb.
For an embodiment, main thin film transistor (TFT) 100 and time thin film transistor (TFT) 101 and 102 are to be configured on first substrate; Above-mentioned m bar sweep trace Gm, n bar data line Sn, (m+1) bar sweep trace G (m+1) are configured on first substrate.First substrate is an active component array base board, and its material comprises glass, quartz or flexible materials, and second substrate is a colored optical filtering substrates, corresponding to active component array base board.Liquid crystal is configurable between colored optical filtering substrates and active component array base board.
Above-mentioned label Clca and Clcb are respectively the pixel capacitance of main pixel A and inferior pixel B, and its area and capacitance size can be arbitrary proportion, look closely reality or design needs and adjust its size.Label Csta, Cstb, Cstc, Cstd are storage capacitors, and its capacitance size can be arbitrary proportion, look closely reality or design needs and adjust its size.
When display panel drove, sweep trace (G-Line) is scanning in regular turn from top to bottom, and when m bar sweep trace Gm was noble potential, main thin film transistor (TFT) 100 and time thin film transistor (TFT) 101 were opened, and n bar data line Sn can be to all electric capacity chargings.When the electric capacity charging is finished, the voltage V of reference point A and B
AAnd V
BVoltage (the V that meeting and n bar data line Sn are provided
Sn) identical.This moment voltage (V
Sn, V
AAnd V
B), charge volume (q
AAnd q
B) and the relational expression of above-mentioned electric capacity as described in following equation 1 and 2:
q
A＝(Clca+Csta)V
Sn＝(Clca+Csta)V
A (1)
When being scanned up to next bar sweep trace G (m+1), then sweep trace Gm returns back to electronegative potential, and sweep trace Gm+1 becomes noble potential, and this moment, main pixel A was closed because of main thin film transistor (TFT) 100, and enter maintenance (holding) state, so the voltage of pixel capacitance Clca and Clcb remains unchanged; And inferior pixel B dimension thin film transistor (TFT) 102 is opened, and causes storage capacitors Cstc short circuit, thereby ineffective, and this moment, equivalent capacity will change.Based on principle of charge conservation, can obtain following equation 3:
Learn from aforesaid equation 3, utilize next bar sweep trace and open inferior thin film transistor (TFT) of time pixel B, make the display voltage V of winner's pixel A and inferior pixel B
AAnd V
BInequality, thereby cause display panel to have the effect of 8 subregion pixels.Suitably allocate above-mentioned each capacity area, can be with the demonstration grade optimization of display panel.8 subregion pixel design modes of the present invention need not increase the additional circuit signal newly, therefore need not increase the loop end newly, equally can reach the effect of multi partition (multi-domains) pixel.
It should be noted that above-mentioned pixel design is only for one embodiment of the invention but not in order to limit the present invention.
In one embodiment, above-mentioned pixel design needs another sweep trace to come inferior pixel is done the action of discharge, otherwise the last item pixel line (pixel line) has unusual demonstration problem.With display panels resolution 1366 * 768, the number of its employed grid integrated circuits pin (pin) is 256 passages (Channel).And the actual scan line cabling that the display panels of this pixel design needs is (768+1) bar, a newly-increased output connecting pin is used to connect the last item sweep trace, thereby must select the grid integrated circuits of 257 special passage output connecting pin numbers, so will increase the integrated circuit cost of display panels.
As mentioned above, under multi partition (for example 8 subregions) pixel design mode, need many virtual scan lines (Dummy gate line) to solve the problem that can't normally show, therefore must use the grid integrated circuits (gate IC) of special requirement based on display panel the last item sweep trace.In one embodiment of the invention, utilize the lead that is connected that connects article one sweep trace (G1) and virtual scan line, display panel the last item sweep trace can normally be shown, and need not increase the cost of grid integrated circuits.Fig. 3 is the equivalent circuit diagram of one 8 subregion pixels in the display panel of the present invention, and wherein part configuration and element and Fig. 2 are similar, and same section then repeats no more.As shown in Figure 3, in 8 subregion pixel design, the grid of the main thin film transistor (TFT) 204 in the main pixel A is connected in the last item sweep trace 201, and its source electrode is electrically connected at n bar data line Sn, and its drain electrode then is connected in Clca and Csta.Inferior thin film transistor (TFT) 203 and 206 in the inferior pixel B has width/height (W/L) and the charging ratio different with main thin film transistor (TFT) 204 in image element circuit.Inferior thin film transistor (TFT) 203 grids are electrically connected at the last item sweep trace 201, and its source electrode then is electrically connected at n bar data line Sn, and its drain electrode is electrically connected at Clcb, Cstc and Cstd.In addition, inferior thin film transistor (TFT) 206 grids are electrically connected at a time virtual scan line (Dummy gate line) 205 of the last item sweep trace 201, its source electrode is electrically connected between 203 drain electrodes of time thin film transistor (TFT) and the Clcb, and its drain electrode is electrically connected between Cstc and the Cstb.In addition, article one sweep trace 200 sees through a distribution 202 connection virtual scan lines 205.Distribution 202 can be disposed at the right side or the left side of display panel, looks closely actual needs or design and decides.The person of noting, article one sweep trace 200 also disposes and is same as element shown in Figure 2 and circuit framework, is convenient illustrations, does not show in Fig. 2.When scanning was carried out, sweep trace was scanned up to the last item sweep trace 201 in regular turn from article one sweep trace 200, returned back to article one sweep trace 200 scanning in regular turn again then.Yet, connect virtual scan line 205 based on article one sweep trace 200, therefore when returning back to article one sweep trace 200 when rescaning, the signal (Vgh) that inputs to article one sweep trace 200 also is passed to virtual scan line 205 makes its discharge, and the result makes the last item sweep trace 201 be able to normal demonstration.
As shown in Figure 4.Display panels 300 drives wherein pixel by source electrode driven integrated circuit 301 and grid-driving integrated circuit 302.Based on 8 above-mentioned subregion pixel design,, connect article one sweep trace 303 and virtual scan line 304 at the newly-increased distribution 305 of multi-partition pixel array 300 1 sides (for example right edge) of display panels 300.Distribution 305 is to be the be connected cabling of article one sweep trace 303 with virtual scan line 304.When article one sweep trace 303 carries out scanning motion, seeing through distribution 305 is able to the signal (Vgh) of article one sweep trace 303 is passed to virtual scan line 304 to carry out discharge process, make that the last item sweep trace of display panels 300 is shown, effect of the present invention makes all panel sweep traces all can normally show.。
In another embodiment, the pixel-driving circuit of display panels 300 comprises the distribution (wiring) of periphery, the virtual source polar curve of the multi-partition pixel left side array of display panels 300 (Dummysource line) 306 for example, it is the virtual source polar curve of virtual thin film transistor (TFT).Utilize virtual source polar curve 306 that article one sweep trace 303 is connected with virtual scan line 304.Virtual source polar curve 306 is to be the be connected cabling of article one sweep trace 303 with virtual scan line 304.When article one sweep trace 303 carries out scanning motion, seeing through virtual source polar curve 306 is able to signal (Vgh) with article one sweep trace 303 and is passed to virtual scan line 304 and carries out discharge process, and then the last item sweep trace of display panels 300 is shown, the result makes all scan line pixels can normally show the octant pixel, as shown in Figure 5.
Comprehensively above-mentioned, the invention provides a kind of enforcement framework and mode of new octant pixel, compared to prior art, have following advantage:
(1). cost can not increase: new 8 subregion loops of the present invention design, can be identical with 4 traditional subregions, so cost and display quality are all more competitive than traditional design.
(2). burn cash payment and resemble lighter: pixel design of the present invention, no any floating (Floating) electrode exists, and therefore can not produce the problem of paying of burning.
(3). stravismus reddish yellow band is lighter: (CS-Swing Type) is little for kenel because the low contrast voltage difference of main pixel-inferior pixel swings than common voltage in design of the present invention, and it is slighter therefore to look side ways the reddish yellow band.
(4). need not use the expensive grid integrated circuits of special requirement.
To being familiar with this field skill person, though the present invention illustrates as above with preferred embodiments, so it is not in order to limit spirit of the present invention.Modification of being done in not breaking away from spirit of the present invention and scope and similarly configuration all should be included in the above-mentioned claim scope, and this scope should cover all similar modification and similar structures, and should do the broadest annotation.
Claims (9)
1. a multi-partition pixel drive circuit is characterized in that, comprising:
One multi-partition pixel array comprises plural main pixel, plural number time pixel, a plurality of sweep traces, a plurality of data lines and a virtual scan line;
Wherein each this main pixel comprises a main thin film transistor (TFT), one first pixel capacitance and one first storage capacitors;
Wherein each this time pixel comprise one for the first time thin film transistor (TFT) with one the second time thin film transistor (TFT), one second pixel capacitance, one second storage capacitors, one the 3rd storage capacitors and one the 4th storage capacitors;
Wherein this virtual scan line is listed in after these a plurality of sweep traces; And
One distribution, between article one sweep trace and this virtual scan line of these a plurality of sweep traces that are coupled, the last item sweep trace that is beneficial to these a plurality of sweep traces gets normally and shows.
2. multi-partition pixel drive circuit as claimed in claim 1, it is characterized in that this main thin film transistor (TFT) has a first grid be coupled a m bar sweep trace of these a plurality of sweep traces, a n bar data line, this first pixel capacitance of one first drain coupled and this first storage capacitors of one first these a plurality of data lines of source-coupled.
3. multi-partition pixel drive circuit as claimed in claim 2, it is characterized in that, this, thin film transistor (TFT) had a second grid this m bar sweep trace that is coupled first time, this n bar data line of one second source-coupled, one second drain coupled is to this second pixel capacitance, this second storage capacitors, the 3rd storage capacitors, wherein this, thin film transistor (TFT) had one the 3rd gate coupled one (m+1) bar sweep trace second time, between this second drain electrode of one the 3rd source-coupled and this second pixel capacitance, between one the 3rd drain coupled the 3rd storage capacitors and the 4th storage capacitors.
4. multi-partition pixel drive circuit as claimed in claim 3 is characterized in that, this m bar sweep trace is the last item sweep trace, and wherein this (m+1) bar sweep trace is this virtual scan line.
5. multi-partition pixel drive circuit as claimed in claim 4 is characterized in that, this last item sweep trace of this multi-partition pixel array is this n bar data line of coupling, and it is this virtual scan line sweep trace before.
6. multi-partition pixel drive circuit as claimed in claim 1 is characterized in that, this distribution is the right edge that is disposed at this multi-partition pixel road array, the limit, left side or a virtual source polar curve of this multi-partition pixel road array.
7. multi-partition pixel driving method, it is characterized in that, this multi-partition pixel driving method is to see through a multi-partition pixel drive circuit to carry out, this multi-partition pixel drive circuit comprises that a multi-partition pixel array comprises plural main pixel, plural number time pixel, a plurality of sweep traces, a plurality of data lines and a virtual scan line, each this main pixel comprises a main thin film transistor (TFT), one first pixel capacitance and one first storage capacitors, each this time pixel comprise one for the first time thin film transistor (TFT) with one the second time thin film transistor (TFT), one second pixel capacitance, one second storage capacitors, one the 3rd storage capacitors and one the 4th storage capacitors, this virtual scan line wherein, list in after these a plurality of sweep traces, this multi-partition pixel driving method comprises:
Make the scanning in regular turn from top to bottom of these a plurality of sweep traces;
When being scanned up to a m bar sweep trace, this m bar sweep trace is a noble potential, so that this main thin film transistor (TFT) and this thin film transistor (TFT) unlatching for the first time, then a n bar data line charges to this first pixel capacitance, this first storage capacitors, this second pixel capacitance, this second storage capacitors, the 3rd storage capacitors and the 4th storage capacitors, and makes this main pixel identical with the voltage of this time pixel;
When being scanned up to next article (m+1) bar sweep trace, then this m bar sweep trace returns back to electronegative potential, this main thin film transistor (TFT) and this first time thin film transistor (TFT) close, and this (m+1) bar sweep trace is a noble potential, so that thin film transistor (TFT) was opened and caused this second storage capacitors short circuit and cause this main pixel different with the voltage of this time pixel second time this; And
By being coupled a distribution between article one sweep trace and this virtual scan line of these a plurality of sweep traces, utilize this article one sweep trace of scanning, see through this distribution and be passed to this virtual scan line to discharge with the signal with this article one sweep trace, the last item sweep trace that is beneficial to these a plurality of sweep traces is able to normal demonstration.
8. multi-partition pixel driving method as claimed in claim 7 is characterized in that, this last item sweep trace of this multi-partition pixel array is this n bar data line of coupling, and it is a last sweep trace of this virtual scan line.
9. multi-partition pixel driving method as claimed in claim 7 is characterized in that, this distribution is the right edge that is disposed at this multi-partition pixel array, the limit, left side or a virtual source polar curve of this multi-partition pixel array.
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| CN103680447A (en) * | 2013-12-12 | 2014-03-26 | 深圳市华星光电技术有限公司 | Liquid crystal display device and pixel driving method thereof |
| CN103700321A (en) * | 2013-12-25 | 2014-04-02 | 京东方科技集团股份有限公司 | Pixel structure, array substrate and display device |
| CN104157255A (en) * | 2014-08-18 | 2014-11-19 | 深圳市华星光电技术有限公司 | Image display method and display system thereof |
| CN106847226A (en) * | 2017-04-13 | 2017-06-13 | 深圳市华星光电技术有限公司 | The optimal method for adjusting common voltage of 3T pixels |
| CN108877681A (en) * | 2017-05-11 | 2018-11-23 | 三星显示有限公司 | Display device with illusory scan line |
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