CN100444241C - Liquid-crystal display panel driving circuit and liquid-crystal display panel therewith - Google Patents
Liquid-crystal display panel driving circuit and liquid-crystal display panel therewith Download PDFInfo
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- CN100444241C CN100444241C CNB2005101206750A CN200510120675A CN100444241C CN 100444241 C CN100444241 C CN 100444241C CN B2005101206750 A CNB2005101206750 A CN B2005101206750A CN 200510120675 A CN200510120675 A CN 200510120675A CN 100444241 C CN100444241 C CN 100444241C
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Abstract
A driving circuit of LCD face plate is prepared as arranging scan line and storage capacity line alternatively to each other, making data line and scan line as well as storage capacity line be insulation-crossed, setting the first and the second film transistors separately at two sides of scan line near to data line, connecting the first and the second pixel electrodes separately to two said transistors, connecting one end of the first and the second storage capacities separately to two said transistors and another end to storage capacity line, and making volume of the first storage capacity be difference to that of the seconds one.
Description
[technical field]
The invention relates to a kind of liquid crystal display panel drive circuit, especially about a kind of multiregional vertical align (Multi-domain Vertical Alignment, MVA) driving circuit of liquid crystal display panel with wide visual angle of being applied to.
[background technology]
Display panels has been widely used in modernized information equipments such as TV, notebook, computing machine, mobile phone, personal digital assistant owing to have advantages such as light, thin, that power consumption is little.But traditional display panels visual angle is narrow.For addressing this problem, Japanese fujitsu (Fujitsu) company proposes a kind of multiregional vertical align wide viewing angle technology.This technology is that the upper and lower substrate at display panels is provided with the several projections thing and liquid crystal molecule is taked vertical orientation, when applying voltage, liquid crystal molecule is to each different directions deflection, light by liquid crystal molecule compensates light path and phase place mutually, thereby effectively improves the visual angle of this display panels.For making compensation more abundant, industry proposes a kind of new technology again, be about to an original pixel and be divided into two sub-pixels, these two sub-pixels are applied different operating voltage respectively, make the liquid crystal deflecting element angle of this two sub-pixel have a fine difference, thereby make by light light path, the phase compensation each other of this pixel liquid crystal molecule more fully, reach the purpose that increases the visual angle.
See also Fig. 1, Fig. 1 is the circuit configuration synoptic diagram of the super wide viewing angle technology of a kind of double thin-film transistors type (Two Transistor Type Super PatternedVertical Alignment the is called for short TT PVA) liquid crystal display panel drive circuit of Korea S's Samsung (Samsung) company proposition.This liquid crystal display panel drive circuit 100 comprise some first sweep traces 101, some second sweep traces 201, plurality of data line 102, some storage capacitance line 103, some the first film transistors (Thin Film Transistor, TFT) 104, some second thin film transistor (TFT) 204 and public (Common) electrodes 107.
This first, second sweep trace 101,201 is arranged parallel to each other along first direction.This data line 102 along second direction be arranged parallel to each other and and this first, second sweep trace 101,201 insulation intersect vertically and therebetween define some pixels 500.First, second sweep trace of this storage capacitance line 103 and this 101,201 is parallel and link to each other with this public electrode 107.
See also Fig. 2, Fig. 2 is the single image element circuit of the liquid crystal display panel drive circuit 100 shown in Figure 1 enlarged diagram of arranging.This first film transistor 104 is positioned at the intersection of this first sweep trace 101 and this data line 102, and its grid 1040 links to each other with this first sweep trace 101, and its source electrode 1041 links to each other with this data line 102.This second thin film transistor (TFT) 204 is positioned at the intersection of this second sweep trace 201 and this data line 102, and its grid 2040 links to each other with this second sweep trace 201, and source electrode 2041 links to each other with this data line 102.This pixel 500 comprises one first sub-pixel 501 and one second sub-pixel 502.This first sub-pixel 501 comprises one first pixel electrode 106 and one first memory capacitance 109 that links to each other with the drain electrode 1042 of this first film transistor 104 respectively.This second sub-pixel 502 comprises one second pixel electrode 206 and one second memory capacitance 209 that links to each other with the drain electrode 2042 of this second thin film transistor (TFT) 204 respectively.This first, second pixel electrode 106,206 respectively and this public electrode 107 form first liquid crystal capacitances (Capacitor Of LiquidCrystal), 108 and second liquid crystal capacitance 208.The other end of this first, second memory capacitance 109,209 links to each other with this storage capacitance line 103 respectively.
The drive principle of this liquid crystal display panel drive circuit 100 sees also Fig. 3, Fig. 3 (A) is the voltage waveform signal figure of data line 102, Fig. 3 (B) is the scanning voltage waveform figure of first sweep trace 101, Fig. 3 (C) is the scanning voltage waveform figure of second sweep trace 201, Fig. 3 (D) is the voltage oscillogram of first pixel electrode 106, and Fig. 3 (E) is the voltage oscillogram of second pixel electrode 206.In the t1 moment, scanning line driver (figure does not show) provides the first scanning voltage V
G1Grid 1040 by first sweep trace, 101 driving the first film transistors 104 provides the second scanning voltage V simultaneously
G2By the grid 2040 of second sweep trace, 201 drivings, second thin film transistor (TFT) 204, this first film transistor 104 and this second thin film transistor (TFT) 204 are opened.Data line driving device (figure does not show) provides a data voltage V
DhTransfer to the source electrode 1041 of this first film transistor 104 and the source electrode 2041 of this second thin film transistor (TFT) 204 respectively by data line 102, first liquid crystal capacitance 108, second liquid crystal capacitance 208, first memory capacitance 109 and second memory capacitance 209 are charged.In the t2 moment, this first liquid crystal capacitance 108, this second liquid crystal capacitance 208, this first memory capacitance 109 and this second memory capacitance 209 both be charged to voltage V
DhAt this moment, data line driving device stops to drive, and scanning driving device stops to drive this first film transistor 104, and this first film transistor 104 is closed, and the voltage of this first liquid crystal capacitance 108 and this first memory capacitance 109 remains V
DhUntil next one t4 zero hour scan period.Simultaneously, scanning driving device continues to drive this second thin film transistor (TFT) 204, keep this second thin film transistor (TFT) 204 and be open mode, this second liquid crystal capacitance 208 and this second memory capacitance 209 are by the drain electrode 2042 and source electrode 2041 discharges of this second thin film transistor (TFT) 204.In the t3 moment, this second liquid crystal capacitance 208 and these second memory capacitance, 209 voltages are discharged to V
DlAt this moment, scanning driving device stops to drive second thin film transistor (TFT) 204, and the voltage of this second memory capacitance 208 and this second liquid crystal capacitance 209 remains V
Dl' until next one t4 zero hour scan period.
Because the voltage at liquid crystal capacitance two ends is the operating voltage of pixel, so the operating voltage of this first, second sub-pixel 501,502 promptly is respectively the voltage V at these first, second liquid crystal capacitance 108,208 two ends
Dh, V
Dl, and V
DhBe not equal to V
DlThereby, make the operating voltage of this first, second sub-pixel 501,502 different.Yet this liquid crystal display panel drive circuit 100 drives owing to same pixel 500 is provided with two sweep traces, and it is more to connect up.Thereby adopting that the aperture opening ratio of display panels of this driving circuit is corresponding will be lower.
[summary of the invention]
In order to solve in the prior art liquid crystal display panel drive circuit more problem that connects up, be necessary to provide a kind of less liquid crystal display panel drive circuit and adopt the display panels of this driving circuit of connecting up.
A kind of liquid crystal display panel drive circuit, it comprises some sweep traces, some storage capacitance line, the plurality of data line, some the first film transistors, some second thin film transistor (TFT)s, some first pixel electrodes, some second pixel electrodes, some first memory capacitance and some second memory capacitance, arrange this sweep trace and this storage capacitance line space, this data line and this sweep trace and the insulation of this storage capacitance line are intersected, this is first years old, second thin film transistor (TFT) lays respectively at the both sides of this sweep trace and is adjacent to this data line setting, and this is first years old, the grid of second thin film transistor (TFT) links to each other with this sweep trace respectively; The source electrode of this first, second thin film transistor (TFT) links to each other with this data line respectively, this first, second pixel electrode links to each other with the drain electrode of this first, second thin film transistor (TFT) respectively, one end of this first, second memory capacitance links to each other with the drain electrode of this first, second thin film transistor (TFT) respectively, the other end links to each other with this storage capacitance line respectively, and the capacitance of the capacitance of this first memory capacitance and this second memory capacitance is different.
A kind of display panels, it comprises one first substrate, one second substrate and a liquid crystal layer, this is first years old, second substrate is oppositely arranged, this liquid crystal layer be arranged at this first, between second substrate, this first substrate comprises some sweep traces, some storage capacitance line, the plurality of data line, some the first film transistors, some second thin film transistor (TFT)s, some first pixel electrodes, some second pixel electrodes, some first memory capacitance and some second memory capacitance, arrange this sweep trace and this storage capacitance line space, this data line and this sweep trace and the insulation of this storage capacitance line are intersected, this is first years old, second thin film transistor (TFT) lays respectively at the both sides of this sweep trace and is adjacent to this data line setting, and this is first years old, the grid of second thin film transistor (TFT) links to each other with this sweep trace respectively; The source electrode of this first, second thin film transistor (TFT) links to each other with this data line respectively, this first, second pixel electrode links to each other with the drain electrode of this first, second thin film transistor (TFT) respectively, one end of this first, second memory capacitance links to each other with the drain electrode of this first, second thin film transistor (TFT) respectively, the other end links to each other with this storage capacitance line respectively, and the capacitance of the capacitance of this first memory capacitance and this second memory capacitance is different.
Compared to prior art, liquid crystal display panel drive circuit of the present invention utilizes thin film transistor (TFT) to have stray capacitance and exists and recalcitrates (Kick-back) voltage, and this recalcitrates the voltage characteristic relevant with the memory capacitance amount of capacity, first, second pixel electrode is provided with two thin film transistor (TFT)s and two memory capacitance that capacitance is different, utilize same sweep trace and same data line to drive these two thin film transistor (TFT)s and reach the purpose that makes this first, second pixel electrode operating voltage different, it is less to connect up.Display panels of the present invention is owing to adopting this driving circuit to drive thereby having high aperture opening ratio.
[description of drawings]
Fig. 1 is the circuit configuration synoptic diagram of prior art liquid crystal display panel drive circuit.
Fig. 2 is the circuit configuration enlarged diagram of the single pixel of driving circuit shown in Figure 1.
Fig. 3 (A) is the data line signal voltage sequential chart of driving circuit shown in Figure 1.
Fig. 3 (B) is the first sweep trace scanning voltage sequential chart of driving circuit shown in Figure 1.
Fig. 3 (C) is the second sweep trace scanning voltage sequential chart of driving circuit shown in Figure 1.
Fig. 3 (D) is the operating voltage sequential chart of first sub-pixel of driving circuit shown in Figure 1.
Fig. 3 (E) is the operating voltage sequential chart of second sub-pixel of driving circuit shown in Figure 1.
Fig. 4 is the structural representation of display panels of the present invention.
Fig. 5 is the circuit configuration synoptic diagram of driving circuit shown in Figure 4.
Fig. 6 is the circuit configuration enlarged diagram of the single pixel of driving circuit shown in Figure 5.
Fig. 7 (A) is the data line signal voltage sequential chart of driving circuit shown in Figure 5.
Fig. 7 (B) is the sweep trace scanning voltage sequential chart of driving circuit shown in Figure 5.
Fig. 7 (C) is the operating voltage sequential chart of driving circuit first sub-pixel shown in Figure 5.
Fig. 7 (D) is the operating voltage sequential chart of driving circuit second sub-pixel shown in Figure 5.
[embodiment]
See also Fig. 4, it is the structural representation of display panels 1 of the present invention.This display panels 1 comprises one first substrate 2, one second substrate 3 and a liquid crystal layer 4.
This first substrate 2 and this second substrate 3 are oppositely arranged, and this liquid crystal layer 4 is arranged between this first substrate 2 and this second substrate 3.
This first substrate 2 is provided with a public electrode 17.
This second substrate 3 is provided with one drive circuit 10.See also Fig. 5, it is the circuit configuration synoptic diagram of this driving circuit 10.This driving circuit 10 comprises some sweep traces 11, plurality of data line 12, some storage capacitance line 13, some the first film transistors 14 and some second thin film transistor (TFT)s 24.
This sweep trace 11 is arranged parallel to each other along first direction.This data line 12 is arranged parallel to each other and intersects vertically with these sweep trace 11 insulation along second direction.This storage capacitance line 13 is arranged with these sweep trace 11 spaced and parallel and is linked to each other with this public electrode 17.This storage capacitance line 13 and this data line 12 define some pixels 50.
See also Fig. 6, it is the single image element circuit of the driving circuit 10 shown in Figure 5 enlarged diagram of arranging.This first film transistor 14 and this second thin film transistor (TFT) 24 are arranged on the intersection of this sweep trace 11 and this data line 12 and are separately positioned on the both sides of this sweep trace 11.The grid 140,240 of this first, second thin film transistor (TFT) 14,24 links to each other with this sweep trace 11 respectively, and source electrode 141,241 links to each other with this data line 12 respectively.This first film transistor 14 and this second thin film transistor (TFT) 24 be on-off element, control its unlatchings by this sweep trace 11 at work or close.
Each pixel 50 comprises one first sub-pixel 51 and one second sub-pixel 52 respectively.This first sub-pixel 51 comprises one first pixel electrode 16 and one first memory capacitance 19 that links to each other with the drain electrode 142 of this first film transistor 14 respectively.This second sub-pixel 52 comprises one second pixel electrode 26 and one second memory capacitance 29 that links to each other with the drain electrode 242 of this second thin film transistor (TFT) 24 respectively.This first, second pixel electrode 16,26 forms first liquid crystal capacitance 18 and second liquid crystal capacitance 28 with public electrode 17 respectively.The other end of this first, second memory capacitance 19,29 links to each other with two storage capacitance line 13 respectively.The capacitance of this first, second memory capacitance 19,29 is different, and it is to reach the different purpose of capacitance that makes this two electric capacity by making different structures.
One thin film transistor (TFT) generally is accompanied by a stray capacitance (Parasitic Capacitor), i.e. the actual parallel-connection structure that should be considered as a desirable thin film transistor (TFT) and a stray capacitance of a thin film transistor (TFT).This driving circuit 10 promptly utilizes this characteristic of thin film transistor (TFT) to reach the different purpose of first, second sub-pixel 51,52 operating voltage that makes this pixel 50 by same pixel 50 being provided with two different memory capacitance 19,29 of capacity.
The course of work of this driving circuit 10 sees also Fig. 7, Fig. 7 (A) is the voltage waveform signal figure of data line 12, Fig. 7 (B) is the scanning voltage waveform figure of sweep trace 11, and Fig. 7 (C) is the operating voltage oscillogram of first sub-pixel, and Fig. 7 (D) is the operating voltage oscillogram of second sub-pixel.In the t1 moment, sweep trace 11 provides scan voltage V
g(capacitance of its stray capacitance is C with the first film transistor 14
Gd1) and second thin film transistor (TFT) 24 (capacitance of its stray capacitance is C
Gd2) open.Simultaneously, data line 12 provides a signal voltage V
d(capacitance is C by the first film transistor 14 and 24 pairs first liquid crystal capacitances 18 of second thin film transistor (TFT) respectively
Lc1) and first memory capacitance 19 (capacitance is C
St1) and second liquid crystal capacitance 28 (capacitance is C
Lc2) and second memory capacitance 29 (capacitance is C
St2) charge.In the t2 moment, these four electric capacity both be charged to voltage V
d, the stray capacitance of this first film transistor 14 and this second thin film transistor (TFT) 24 (figure does not show) then charges to voltage (V respectively
g-V
d) (i.e. the lock of this first, second thin film transistor (TFT) 14,24, the voltage difference of drain electrode).At this moment, this sweep trace 11 and this data line 12 stop to drive, and this first, second thin film transistor (TFT) 14,24 cuts out simultaneously, the vanishing respectively of its grid voltage, and the voltage of its stray capacitance is respective change also.The Partial charge of the stray capacitance of this first film transistor 14 flows into this first liquid crystal capacitance 18 and this first memory capacitance 19, makes this first liquid crystal capacitance 18 and this first memory capacitance 19 produce one and recalcitrates voltage Δ V
P1The voltage of this first liquid crystal capacitance 18 and this first memory capacitance 19 becomes V
1, the voltage of the stray capacitance of this first film transistor 14 becomes (V
1) and keep until next of t3 always the zero hour scan period.The Partial charge of the stray capacitance of this second thin film transistor (TFT) 24 flows into second liquid crystal capacitance 28 and second memory capacitance 29, makes this second liquid crystal capacitance 28 and this second memory capacitance 29 produce another and recalcitrates voltage Δ V
P2This second liquid crystal capacitance 28 and these second memory capacitance, 29 voltages become V
2, the voltage of the stray capacitance of this second thin film transistor (TFT) 24 becomes (V
2) and keep until next of t3 always the zero hour scan period.
According to charge conservation (Law Of Conservation Of Charge) theorem, this recalcitrates voltage Δ V
P1With Δ V
P2Size be respectively:
And the operating voltage V of this first, second sub-pixel
1, V
2Size then be respectively:
V
1＝V
d-ΔV
p1 (3)
V
2＝V
d-ΔV
p2 (4)
By (1)～(4) formula, can draw:
By (3)～(6) formula, can obtain the different voltage Δ V that recalcitrates by the capacitance of adjusting this first memory capacitance 19 and this second memory capacitance 29
P1With Δ V
P2Thereby, make operating voltage V1, the V2 of this first, second sub-pixel 51,52 different.Because this first film transistor 14 is identical structures with this second thin film transistor (TFT) 24, its stray capacitance C
Gd1And C
Gd2About equally, this first liquid crystal capacitance 18 and this second liquid crystal capacitance 28 also are same structures, its capacitance C
Lc1And C
Lc2Therefore also about equally, with the capacitance C of this first memory capacitance 19 and this second memory capacitance 29
St1, C
St2Be set to the different different voltage Δ V that recalcitrates that promptly can obtain
P1With Δ V
P2Thereby, reach the different purpose of operating voltage V1, V2 that makes this first, second sub-pixel 51,52.
Compared to prior art, two sub-pixels 51,52 of 10 pairs of same pixels 50 of driving circuit of the present invention only are provided with an one scan line and a data line, and it is less to connect up.This display panels 1 is owing to adopt this driving circuit 10 to drive, and its aperture opening ratio is higher.
The capacitance of this first memory capacitance 19 is set to be greater than or less than the capacitance of this second memory capacitance 29 can reach the different purpose of operating voltage that makes this first, second sub-pixel 51,52.
Claims (7)
1. liquid crystal display panel drive circuit, it comprises: some sweep traces, some storage capacitance line, the plurality of data line, some the first film transistors, some second thin film transistor (TFT)s, some first pixel electrodes, some second pixel electrodes, some first memory capacitance and some second memory capacitance, arrange this sweep trace and this storage capacitance line space, this data line and this sweep trace and the insulation of this storage capacitance line are intersected, this is first years old, second thin film transistor (TFT) lays respectively at the both sides of this sweep trace and is adjacent to this data line setting, and this is first years old, the grid of second thin film transistor (TFT) links to each other with this sweep trace respectively; The source electrode of this first, second thin film transistor (TFT) links to each other with this data line respectively, this first, second pixel electrode links to each other with the drain electrode of this first, second thin film transistor (TFT) respectively, one end of this first, second memory capacitance links to each other with the drain electrode of this first, second thin film transistor (TFT) respectively, the other end links to each other with this storage capacitance line respectively, and the capacitance of the capacitance of this first memory capacitance and this second memory capacitance is different.
2. liquid crystal display panel drive circuit as claimed in claim 1 is characterized in that the capacitance of this first memory capacitance is less than the capacitance of this second memory capacitance.
3. liquid crystal display panel drive circuit as claimed in claim 1 is characterized in that the capacitance of this first memory capacitance is greater than the capacitance of this second memory capacitance.
4. display panels, it comprises: one first substrate, one second substrate and a liquid crystal layer, this is first years old, second substrate is oppositely arranged, this liquid crystal layer be arranged at this first, between second substrate, this first substrate comprises: some sweep traces, some storage capacitance line, the plurality of data line, some the first film transistors, some second thin film transistor (TFT)s, some first pixel electrodes, some second pixel electrodes, some first memory capacitance and some second memory capacitance, arrange this sweep trace and this storage capacitance line space, this data line and this sweep trace and the insulation of this storage capacitance line are intersected, this is first years old, second thin film transistor (TFT) lays respectively at the both sides of this sweep trace and is adjacent to this data line setting, and this is first years old, the grid of second thin film transistor (TFT) links to each other with this sweep trace respectively; The source electrode of this first, second thin film transistor (TFT) links to each other with this data line respectively, this first, second pixel electrode links to each other with the drain electrode of this first, second thin film transistor (TFT) respectively, one end of this first, second memory capacitance links to each other with the drain electrode of this first, second thin film transistor (TFT) respectively, the other end links to each other with this storage capacitance line respectively, and the capacitance of the capacitance of this first memory capacitance and this second memory capacitance is different.
5. display panels as claimed in claim 4 is characterized in that the capacitance of this first memory capacitance is less than the capacitance of this second memory capacitance.
6. display panels as claimed in claim 4 is characterized in that the capacitance of this first memory capacitance is greater than the capacitance of this second memory capacitance.
7. display panels as claimed in claim 4 is characterized in that, this first, second pixel electrode forms first, second liquid crystal capacitance with this second substrate respectively.
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| Application Number | Priority Date | Filing Date | Title |
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| CNB2005101206750A CN100444241C (en) | 2005-12-13 | 2005-12-13 | Liquid-crystal display panel driving circuit and liquid-crystal display panel therewith |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2005101206750A CN100444241C (en) | 2005-12-13 | 2005-12-13 | Liquid-crystal display panel driving circuit and liquid-crystal display panel therewith |
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| CN100444241C true CN100444241C (en) | 2008-12-17 |
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Families Citing this family (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101393716B (en) * | 2007-09-21 | 2013-03-13 | 统宝光电股份有限公司 | Electronic system |
| KR101458903B1 (en) * | 2008-01-29 | 2014-11-07 | 삼성디스플레이 주식회사 | Liquid crystal display and driving method thereof |
| WO2010134439A1 (en) * | 2009-05-21 | 2010-11-25 | シャープ株式会社 | Liquid crystal panel |
| CN104777638B (en) * | 2015-04-13 | 2018-04-20 | 深圳市华星光电技术有限公司 | Liquid crystal display panel and liquid crystal display device |
| CN104834116B (en) * | 2015-05-26 | 2019-01-25 | 深圳市华星光电技术有限公司 | A kind of liquid crystal display panel and its driving method |
| CN106940505B (en) * | 2017-05-08 | 2019-11-15 | 深圳市华星光电技术有限公司 | Liquid crystal display panel and liquid crystal display device |
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| JPS62182717A (en) * | 1986-02-06 | 1987-08-11 | Nec Corp | Liquid crystal display device |
| JPH1068973A (en) * | 1997-07-23 | 1998-03-10 | Seiko Epson Corp | Display device |
| CN1182887A (en) * | 1996-10-18 | 1998-05-27 | 佳能株式会社 | Active matrix substrate, LCD device and display device for using it |
| US20030214472A1 (en) * | 2002-05-15 | 2003-11-20 | Toppoly Optoelectronics Corp. | Display circuit structure for liquid crystal display |
| US20050134751A1 (en) * | 2003-12-17 | 2005-06-23 | Adiel Abileah | Light sensitive display |
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| JPS62182717A (en) * | 1986-02-06 | 1987-08-11 | Nec Corp | Liquid crystal display device |
| CN1182887A (en) * | 1996-10-18 | 1998-05-27 | 佳能株式会社 | Active matrix substrate, LCD device and display device for using it |
| JPH1068973A (en) * | 1997-07-23 | 1998-03-10 | Seiko Epson Corp | Display device |
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| US20050134751A1 (en) * | 2003-12-17 | 2005-06-23 | Adiel Abileah | Light sensitive display |
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