CN101866574A - Digital video experiment device and experiment method - Google Patents
Digital video experiment device and experiment method Download PDFInfo
- Publication number
- CN101866574A CN101866574A CN 201010169614 CN201010169614A CN101866574A CN 101866574 A CN101866574 A CN 101866574A CN 201010169614 CN201010169614 CN 201010169614 CN 201010169614 A CN201010169614 A CN 201010169614A CN 101866574 A CN101866574 A CN 101866574A
- Authority
- CN
- China
- Prior art keywords
- signal
- digital video
- digital
- image processor
- observer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Landscapes
- Controls And Circuits For Display Device (AREA)
Abstract
The invention discloses a digital video experiment device and a digital video experiment method. The device is characterized in that an FPGA serving as a core is matched with other special integrated circuits ADC, an HDMI receiving decoder, a DAC, an MCU, a memory and the like to form a circuit system; by compiling different FPGA programs and MCU programs, a digital video image processor circuit has different functions, can realize different digital video experiment teachings and is favorable for understanding various different digital video international standards such as VESA, ITUT, CCIR and the like. The device fills the blank of the domestic domain, and is favorable for cultivating digital video professionals.
Description
Technical field
The present invention relates to the teaching equipment technical field, particularly a kind of teaching digital video experimental provision and experimental technique.
Background technology
Since millions upon millions of year, the human mode of obtaining information from nature is the perception by " face ", wherein it seems acquisition by eyes more than 90%; But since invention in 19 end of the centurys Braun tube (CRT), this information of being obtained by eyes can not write down and reappear; The demonstration of information finally all is that the mode with simulating signal is shown.Entered for 20th century, appearance and development along with medium such as television broadcasting medium and computing machines, information acquisition, transmission, processing and storage develop to the digitizing direction, in order to obtain better display effect, digitized display terminal becomes the focus of many research institutions and enterprises pay attention, and various novel display devices are poured into market like the mushrooms after rain.CRT is still keeping overlord's status in numerous displays, and LCD (LCD) then being that the center has obtained to develop by leaps and bounds with personal computer, mobile communication market, has been started the personal information society of today after computing machine occurs.That is to say that CRT has constructed the modern industrial society in mass media's epoch, LCD has then constructed the advanced information society that individual media is taken as the leading factor.The information society of 21 century and market have entered into well-known multimedia era, display technique no longer is confined to former Braun tube (CRT), LCD (LCD), plasma display panel (PDP), digital light are handled (DLP), Organic Light Emitting Diode multiple novel display technique and display modes such as (OLED), be accompanied by the development of information communication medium and the update of display, the digitizing display technique has also obtained development fast.Record and the electric signal that reproduces these display message are called vision signal, and what CRT received is simulating signal, so our original TV signal is the analog form transmission; But novel device for display of message such as LCD, PDP, DLP, OLED etc. receive and processing digital signal has higher efficient and better quality; Therefore the method (digital video) of the video information of representing with digital signal is arisen at the historic moment; Digital video technology comprises modulus conversion technique (ADC), high-speed digital circuit designing technique, image processing techniques, numerical coding and demodulation techniques, Circuits System designing technique etc.; But analog video used 100 years, galaxy of talent, and there is the countless simulated television maintenance talents in town and country; The appearance of digital video seldom has relevant course also soon in the Chinese Universities, rare especially relevant experimental facilities, and the demand for talent very big (having thousands of TV stations, more than one hundred million digital televisions need to be about to maintenance and repair) to digital video is gone up by society.
Summary of the invention
It is difficult and lack the problem of suitable experiment porch and a kind of device and the experimental technique that provide at the digital video experimental teaching to the objective of the invention is, this device has not only solved the platform problem of putting into practice of digital video experimental teaching, also the training for the digital video slip-stick artist provides a kind of effective means, and then has improved work efficiency.
The object of the present invention is achieved like this:
A kind of digital video experimental provision, characteristics are that this device comprises:
One digital video image processor is used for control and calculates with digital video;
One OSD produces and the image overlay device, and the stack that is used for custom menu and digital video image is synthetic;
One high-speed data storer and high-speed data memory controller circuit thereof are connected to the digital video image processor, are used to store input digit video data Frame, superimposed image data Frame and output digital video data Frame;
One analog to digital converter (ADC) comprises Video Decoder, is used to realize the conversion of analog video signal to digital video signal (RGBHsVs or YCbCr signal);
One HDMI signal receiving and decoding device receives and is decoded into digital rgb signal or YCbCr signal to the TMDS differential signal of external digital video signal source (computing machine or digital TV set-top box etc.) input;
One microprocessor (MCU) is connected to digital video image processor, digital to analog converter (ADC) and HDMI signal receiving and decoding device, produces the message exchange signal according to outside input trigger pip;
One SD card read-write controller is used to connect outside SD and snaps into the digital video image processor;
One SD card is used to store static number vision signal (as the Frame of the photo of digital camera or the dynamic video image of catching);
One output digital video signal converter is used for the signal (LVDS or TMDS etc.) that becomes external display device to discern to the encoding digital video signals that the digital video image processor produces;
One LCD display is used for the digital video signal that the digital video image processor produces is converted into the directly information of perception of human eye;
One signal observer 1, the digital video signal after being used to observe analog video signal and passing through analog to digital converter (ADC) conversion;
One signal observer 2 is used for observing simulation TMDS differential signal and decoded digital rgb signal or YCbCr signal;
One signal observer 3 is used for observing the tracking of various digital video signal and experimentation program debug signal and states by the digital video image processor processing;
One signal observer 4 is used to observe the digital video signal after the digital video image processor processing;
One signal observer 5 is used to observe the LVDS behind output digital video signal converter coding or the digital video signal of TMDS form;
One signal observer 6 is used to observe the digital video signal of dynamic exchange between high-speed data storer and controller circuitry and the digital video image processor;
One signal observer 7 is used to observe the digital video signal of dynamic exchange between SD card and the digital video image processor;
Described digital video image processor, OSD produce and image overlay device, SD card read-write controller, output digital video signal converter are loaded among a slice programming device (FPGA) by coding.Described microprocessor (MCU) is connected in an external computer (PC) by USB.
A kind of digital video experimental technique, this method comprises the steps:
A) selected outer video signal source and be connected to experimental provision (concrete device);
What b) microprocessor (MCU) read respectively that the value of the status register of analog to digital converter (ADC) and HDMI signal receiving and decoding device judges input is analog video signal or digital video signal, and detect the form of video, be provided with by the I2C serial line interface then that analog to digital converter (ADC) comprises Video Decoder and HDMI signal receiving and decoding device is done corresponding handling procedure;
C) the digital video image processor receives the digital video signal that analog to digital converter (ADC) comprises Video Decoder and the output of HDMI signal receiving and decoding device, and digital video signal is sent into the high-speed data memory interface circuit;
D) the digital video image processor to the digital of digital video data of storing in the high-speed data memory interface circuit amplify, dwindle, enhancing and denoising;
E) the digital video image processor carries out brightness (brightness and contrast's adjustment) and colourity processing (color enhancing, colour temperature conversion, bandwidth expansion etc.) to the digital of digital video data of storing in the high-speed data memory interface circuit;
F) OSD produces and the image overlay device produces the wicket data or reads image data and they are sent to the high-speed data memory interface circuit from the SD card;
G) the digital video image processor is delivered to the output digital video signal converter to video data stored in the high-speed data memory controller output buffer;
H) output digital video signal converter digital video signal that the digital video image processor processing is crossed converts LVDS or TMDS format signal to;
I) LCD display is accepted LVDS format digital video signal, and shows the discernible image information of human eye;
J) according to the difference of experiment content, the experimenter observes different digital video signals with oscillograph at signal observer 1, signal observer 2, signal observer 3, signal observer 4, signal observer 5, signal observer 6 and signal observer 7.
The invention provides a kind of device and experimental technique of digital video experimental learning, help the digital video talent's cultivation; Make the digital video image processor circuit possess different functions by writing different FPGA programs, can realize different digital video experiments.
Description of drawings
Fig. 1 is an experimental provision structural representation of the present invention
Fig. 2 is fpga chip structured flowchart in the experimental provision of the present invention
Fig. 3 uses process flow diagram for experimental provision of the present invention
Fig. 4 is an experimental provision composite video signal CVBS decoded signal synoptic diagram of the present invention
Fig. 5 is YC filtering figure in the experimental provision CVBS signal decoding process of the present invention
Fig. 6 is an experimental provision ADC demoder block diagram of the present invention
Fig. 7 is experimental provision CVBS decoding experimentation figure of the present invention
Embodiment
Consult Fig. 1, experimental provision of the present invention is when carrying out concrete digital video, and peripheral PC, digital video signal source or simulation signal generator and the power supply of connecting constitutes an experimental system.
The effect of PC in system is bridge extraneous and the digital video experimental provision, deliver to microprocessor (MCU) through the experiment control command that the USB interface of PC is sent, be distributed to each functional circuit in the experimental provision (FPGA and ADC and HDMI) etc. after the MCU decoding, and the state of each several part turned back to PC, PC also is used for experimentation HDL programming (verilog or VHDL) simultaneously, and FPGA is set to different functional circuits; Hardware configuration code (software) burning of its generation is loaded into after powering in the programmable chip (FPGA) in the FPGA configuring chip automatically.
Analog to digital converter (ADC) comprises a Video Decoder, implements the conversion of analog video signal to digital video signal (RGBHsVs or YCbCr signal) under MCU control; It can support speed up to (1080p 60hz) analog rgb of high definition video signal line by line of 148.5MHz or the sampling of YPbPr.
The HDMI signal receiver is implemented the TMDS differential signal of external digital video signal source (computing machine or digital TV set-top box etc.) input is received and be decoded into digital rgb signal or YCbCr signal under MCU control; It can support the decoding of speed up to the signal of high-definition digital video line by line (1080p60hz) of 148.5MHz.
Programmable chip (FPGA) is finished video image and is dynamically reached static various processing, and final the demonstration is output in LCD or external display.
Digital video signal is the signal of CMOS (perhaps LVTTL) level compatibility, so that programmable chip (FPGA) can receive processing; It is by R[0:9], G[0:9], B[0:9], clock, Blanking, VS, 34 signals such as HS are formed.
Consult Fig. 2, experimental provision of the present invention is a core with (fpga chip), comprises that digital video image processor, SD card interface circuit, high-speed data memory interface circuit, OSD produce and image overlay device and output digital video signal converter.
The digital video image processor receives the digital video signal that analog to digital converter comprises Video Decoder (ADC) and the output of HDMI signal receiver, and digital video signal is sent to the high-speed data memory interface circuit; The digital video image processor to the digital of digital video data of storing in the high-speed data memory circuitry amplify, dwindle, processing such as enhancing, denoising; The digital of digital video data of storing in the high-speed data memory interface circuit is carried out brightness (brightness and contrast's adjustment) with the digital video image processor and colourity is handled (color enhancing, colour temperature conversion, bandwidth expansion etc.); OSD produces and the image overlay device produces the wicket data or read image data and they are sent to the high-speed data memory interface circuit from the SD card; The digital video image processor is delivered to the output digital video signal converter to the digital of digital video data of storing in the high-speed data memory controller output buffer; The digital video signal that the output digital video signal converter is crossed the digital video image processor processing converts LVDS or TMDS format signal to; LCD display is accepted LVDS format digital video signal, and shows the discernible image information of human eye; The TMDS format signal then can be shown in any commercial video display; According to the difference of experiment content, the experimenter can observe different digital video signals at signal observer 1, signal observer 2, signal observer 3, signal observer 4, signal observer 5, signal observer 6 and signal observer 7 with oscillograph.
Consult Fig. 3, apparatus of the present invention using method flow process: after system powered on, microprocessor (MCU) loaded initialize routine automatically, and entered holding state S0.
According to experiment content, the USB of microprocessor (MCU) receives the order of exterior PC, is distributed to each functional circuit in the experimental provision (ADC and HDMI) etc. after the MCU decoding, simultaneously configurating programmable preface FPGA; And the state of each several part turned back to PC; And the S1 that gets the hang of; This moment digital video signal can comprise Video Decoder (ADC) from digital to analog converter also can be from the HDMI signal receiver; Can observe analog video signal and digital video signal (RGB HsVs) by signal observer 1; Can observe TMDS vision signal and decoding back digital video signal (RGB HsVs) by signal observer 2.
The digital video image processor receives the digital video signal that analog to digital converter comprises Video Decoder (ADC) and the output of HDMI signal receiver, and digital video signal is sent to the high-speed data memory interface circuit; And the S2 that gets the hang of; Can observe the various signals (high-speed data, address and access control etc.) of image memory controller output this moment by signal observer 6.
The digital video image processor to the digital of digital video data of storing in the high-speed data memory interface circuit amplify, dwindle, processing such as enhancing, denoising; The digital of digital video data of storing in the high-speed data memory circuitry is carried out brightness (brightness and contrast's adjustment) with the digital video image processor and colourity is handled (color enhancing, colour temperature conversion, bandwidth expansion etc.); And the S3 that gets the hang of; Can observe the digital video signal of digital video image processor processing by signal observer 3 this moment, also can the tracking test process in program debug signal and processor working state.
OSD produces and the image overlay device produces the wicket data or read image data and they are sent to the high-speed data memory interface circuit from the SD card, and the S4 that gets the hang of; Can observe SD card accessing time sequence by signal observer 7 this moment; On display lcd, can see simultaneously the video image of stack.
The digital video image processor is delivered to the output digital video signal converter to the digital of digital video data of storing in the high-speed data memory controller output buffer, and the S5 that gets the hang of; Can observe output digital video signal sequence by signal observer 4 this moment.
The digital video signal that the output digital video signal converter is crossed the digital video image processor processing converts LVDS or TMDS format signal to, and LCD display is accepted LVDS format digital video signal, and shows the discernible image information of human eye; The TMDS format signal then can be shown in any commercial video display; And the S6 that gets the hang of; Can observe output digital video signal LVDS or TMDS sequential by signal observer 5 this moment.
Write down the experimental result of each observer.
Embodiment
With the decoding digital video experiment is example, is described in detail experimentation of the present invention:
1, experiment purpose
(1), understands vision signal decoding principle
(2), understand the vision signal decode procedure
(3), understand (the comb filter ﹠amp of crucial filtering algorithm in the vision signal decode procedure; Notch filter) effect
(4), the use of association's analog to digital converter (ADC comprises Video Decoder)
(5), observation signal waveform and understand in the CCIR-601 standard definition of relevant vision signal
(6), observation signal waveform and understand in the ITUT-656 standard definition of relevant vision signal
(7), behind the observation video signal digitization in the display result of LCD
2, experimental principle
(1), composite video signal (CVBS) decoding
The Vi deo terminal of receiver, video is Composite terminal (such as RF radio frequency interface and an AV interface), and the signal that it can receive is Composite Video Signal, i.e. mixed video signal (also claiming composite signal).The Composite signal has comprised brightness (Luminance, represent with alphabetical Y) and the signal of colourity/chroma (Chrominace) two aspects, the work that video circuit will be done is exactly that Y/C carries out separating treatment, this method be utilize carrier chrominance signal to transmit these characteristics in the subcarrier mode (the PAL-system subcarrier is 4.43MHz, the TSC-system subcarrier is 3.58MHz), with frequency selection circuit y/c signal is separated.Inside is made up of LC bandpass filter and trapper, is carrier chrominance signal arrowband (such as pal mode 4.43MHz frequency subcarriers) bandpass filter with vision signal by a centre frequency (fsc), takes out carrier chrominance signal.Be the colourity trapper of carrier chrominance signal subcarrier 4.43MHZ with luminance signal through a centre frequency again, absorb carrier chrominance signal, thus the luminance signal of obtaining.Decode procedure as shown in Figure 4.
(2), digital comb filter
Frequency separation method in the above-mentioned decode procedure exists some shortcomings: in luminance channel, the colourity trapper when absorbing carrier chrominance signal also with this frequency range in the component frequency component of luminance signal curbed, promptly the high fdrequency component of luminance signal is lost.Simultaneously, remaining carrier chrominance signal also may enter luminance channel and cause the colour contamination interference, and color definition chart occurring at screen usually is last two frequency bands dyeing phenomenon.
In chrominance channel, L.C chroma strip bandpass filter quality is not high, take out carrier chrominance signal, when suppressing luminance signal, also the luminance signal in this frequency range has been elected, high-frequency brightness signal is come out by demodulation (belonging to superfluous signal) through chrominance demodulator, and the colour that makes some thin grid or strip region flicker occur disturbs.As seen utilize traditional frequency separation method Y, C signal can not be made thorough separation, certainly existing: the interference of bright colour contamination, look cross luma, it is satisfactory that picture quality is difficult at all.Influence shown in Figure 5 can appear in the application of in fact this method in colour TV, and a is a luminance channel among the figure, and its dash area Y-signal is attenuated, and influences the brightness sharpness; B is a chrominance channel among the figure, and its dash area is that Y-signal also takes out, and causes the interference of luminance signal colour contamination.
Present comb filter is to solve the unique method that the vision signal light tone is scurried mutually under the situation that guarantees image detail, there are many passband and stopbands by certain frequency interval aligned identical its inside, only allow the signal of some particular frequency range pass through, because its family curve is as comb, old friends are referred to as comb filter (Comb Filtering).
It is according to the principle of video signal spectrum intersection and the broach frequency filtering transport property of comb filter, isolate luminance and chrominance information in the mode that frequency spectrum separates, it is relatively thoroughly cleaner that this new separation method separates y/c signal, thereby significantly improve image definition.Usually comb filter partly is made up of two horizontal delaies, totalizer, subtracter etc.To live image, comb filtering carries out in frame, i.e. two-dimensional comb filtering.Comb filter and bandpass filter cascade that high-grade digital television adopts row to postpone constitute the Y/C separation scheme and just can obtain satisfied picture quality.Use comb filter that picture quality is obviously improved.Interference luminous point, interference decorative pattern that look cross luma and bright colour contamination cause have been solved; Eliminate colourity quadrature component U, V colour difference signal and mixed the colour edging wriggling that repeatedly causes; Eliminated bright, look fringing, eliminated the color mistake and the gray-scale value of high-frequency signal and represented mistake.
For the NTSC-M standard, we suppose that the vision signal maintenance correlativity and the lag line of adjacent two row is lossless, Y-signal frequency spectrum and C signal spectrum (fH represents line frequency) alternately occur at interval with fH/2, subcarrier frequency fsc is 227.5fH, if design a comb filter circuit, make V signal time-delay delegation, add and subtract with the signal of not time-delay respectively again.Y-signal phase invariant before and after the time-delay, and the C signal phase is opposite.Time delayed signal and through connect signal obtain Y-signal after the addition in totalizer, i.e. (Y+C)+(Y-C)=2Y subtracts each other in subtracter and then obtains the C signal, i.e. (Y+C)-(Y-C)=2C.Analyze from the comb filter amplitude-versus-frequency curve, the Y frequency spectrum drops on totalizer family curve peak dot and subtracter family curve valley point, comes so luminance signal and carrier chrominance signal are separated from each other.
Common comb filter has the branch of 2D and 3D, and two row, triplex row, the five-element's branch is arranged again among the 2D.What analog to digital converter in the experiment (ADC comprises Video Decoder) was integrated is five-element's dressing wave filter.
(3), analog to digital converter (ADC comprises Video Decoder) brief introduction-TVP5147
TVP5147 is a high-performance analog to digital converter (ADC comprises Video Decoder) of supporting form such as NTSC/PAL/SECAM.It can receive 10 tunnel vision signal, by single-chip microcomputer I2C bus internal register is set, and can be configured to composite video signal (CVBS), S-Video signal or the independently combination of YPbPr.Can export the ITU-R BT.656 signal (synchronizing signal is embedded) of 10 4:2:2, and the ITU-R BT.601 signal of 10 or 20 4:2:2 (synchronizing signal is separated, pin output separately).The TVP5147 block diagram as shown in Figure 6.
After video decoding chip TVP5147 resets, correctly dispose the I2C register to it by MCU; Wherein the value of the I2C register configuration of a kind of TVP5147 is as shown in the table.
| Register address | Write data | Explanation |
| ??0x00 | ??0x02 | VI_1_C imports as cvbs |
| ??0x04 | ??0x3F | Support the automatic switchover of various standards |
| ??0x08 | ??0x00 | For NTSC and PAL selects optimized notch filter |
| Register address | Write data | Explanation |
| ??0x0E | ??0x04 | For the carrier chrominance signal of NTSC and PAL is selected optimized notch filter |
| ??0x33 | ??0x43 | Select output format to separate, separately the 10-bit 4:2:2 of pin output for synchronizing signal is arranged |
| ??0x34 | ??0x11 | Enable the output of YCbCr and clock |
| ??0x36 | ??0xAF | Enable to export capable field sync signal |
| Other | Default value | Initial value behind the Reset |
(4), experiment decode procedure
The decode procedure of TVP5147 as shown in Figure 7.
The clamp control circuit is partly controlled the clamp level of analog input signal, and a pair of electric capacity of analog input end is used for the maintenance and the filtering of clamping voltage.Internal digital clamp comparer produces goes up pincers and following pincers control signal.The clamp level quantized value of ADC passage is fixed as brightness (120) and colourity (256).Usually, the clamp time location is located at during the HCL of horizontal blanking back porch of vision signal.
Gain control circuit can analog channel be set to the static gain rank by the I2C bus, perhaps the automatic gain rank.The gain control of brightness is used for amplification CVBS/YC signal, to reach required voltage amplitude, satisfies the ADC input voltage range.Usually, automatic gain control position effective time is located at at the synchronous end of vision signal.
ADC by 11-bit obtains digital CVBS signal or y/c signal.10 composite video signals multiply by carrier signal and obtain producing colour difference signal U and V in quadrature demodulator.And U and V signal by low-pass filter to obtain required bandwidth.A kind of self-adaptation 5 line comb filter are separated the UV signal from Y-signal.Carrier chrominance signal by quadrature modulator after and wire delay produce composite video signal and subtract each other, thereby the luminance signal of obtaining.The form that Y/C separates in this is complementary fully, does not therefore have information dropout.
3, experimental procedure
(1), experimental provision powers on.
(2), PC display mode, the Video signal input interface from PC (the video card support is multi-output mode simultaneously) output Video signal (as the TSC-system formula) to system are set.
(3), PC be set be output as test Patern1 (composite video signal), with oscillograph by signal observer 1 observation ntsc television signal, record analysis observed result.
(4), send the I2c instruction to MCU (Stm32), correctly dispose the I2C control register value of chip on board Videodecoder TVP5147 and video AD CADV7341 by USB interface.And read the state value of TVP5147 and ADV7341, whether its value of check analysis is correct.Here 0x33 register value in address is 0x43, and promptly selecting output format is the 10-bit 4:2:2 of independent synchronizing signal output.By the 20bit YCbCr digital signal of signal observer 1 observation by TVP5147 decoding back output, it should be ITU-R BT-601 feature video signal, record analysis observed result with oscillograph.
(5), to reset address 0x33 register value be 0x40 (for default value behind the Reset), promptly selecting output format is the 10-bit 4:2:2 of independent synchronizing signal output.By the 10bit YCbCr digital signal of signal observer 1 observation by TVP5147 decoding back output, it should be TU-R BT-656 feature video signal, record analysis observed result with oscillograph.
(6), download mouthful, to FPGA download configuration program, correctly dispose FPGA by JTAG.Pass through digital R (0:7) G (0:7) B (0:7) signal, line synchronizing signal (Hsync), vertical synchronizing signal (Hsync), pixel useful signal Blanking and the picture number clock signal (DClock) of signal observer 4 observations after FPGA handles, record analysis observed result with oscillograph.
(7), the VGA of observation experiment system interface output displaying contents and pc machine testpattern1 on LCD display is just the same;
(8), according to the tabulation of the register of TVP5147 parameter handbook, upgrade the value of component register by USB interface, in output LCD demonstration, can see its effect in video decode; For example the light tone separating effect of Combfilter and Notch filter, noise filtering effect etc. during different value
(9), analyze experimental result:
A, experimental result is carried out time series analysis
B, experimental result is carried out theoretical analysis find the best register configuration value combination of video decode.
Claims (3)
1. digital video experimental provision is characterized in that this device comprises:
One digital video image processor is used for control and calculates with digital video;
One OSD produces and the image overlay device, and the stack that is used for custom menu and digital video image is synthetic;
One high-speed data storer and high-speed data memory controller circuit thereof are connected to the digital video image processor, are used to store input digit video data frame, superimposed image data frame and output digital video Frame;
One analog to digital converter ADC comprises Video Decoder, is used to realize the conversion of analog video signal to digital video signal RGBHsVs or YCbCr;
One HDMI signal receiving and decoding device receives and is decoded into digital rgb signal or YCbCr signal to the TMDS differential signal of external digital video signal source input;
One microprocessor MCU is connected to digital video image processor, digital to analog converter ADC and HDMI signal receiving and decoding device, produces the message exchange signal according to outside input trigger pip;
One SD card read-write controller is used to connect outside SD and snaps into the digital video image processor;
One SD card is used to store the static number vision signal;
One output digital video signal converter is used for the signal LVDS or the TMDS that become external display device to discern to the encoding digital video signals that the digital video image processor produces;
One LCD display is used for the digital video signal that the digital video image processor produces is converted into the directly information of perception of human eye;
One signal observer 1, the digital video signal after being used to observe analog video signal and passing through analog to digital converter ADC conversion;
One signal observer 2 is used for observing simulation TMDS differential signal and decoded digital rgb signal or YCbCr signal;
One signal observer 3 is used for observing the tracking of various digital video signal and experimentation program debug signal and states by the digital video image processor processing;
One signal observer 4 is used to observe the digital video signal after the digital video image processor processing;
One signal observer 5 is used to observe the LVDS behind output digital video signal converter coding or the digital video signal of TMDS form;
One signal observer 6 is used to observe the digital video signal of dynamic exchange between high-speed data storer and the digital video image processor;
One signal observer 7 is used to observe the digital video signal of dynamic exchange between SD card and the digital video image processor;
Described digital video image processor, OSD generation and image overlay device, SD card read-write controller and output digital video signal converter are loaded among a slice programmable device FPGA by coding.
2. experimental provision according to claim 1 is characterized in that described microprocessor MCU is connected in an external computer PC by USB.
3. a digital video experimental technique is characterized in that this method comprises the steps:
A) selected outer video signal source and be connected to experimental provision;
What b) microprocessor MCU read respectively that the value of the status register of analog to digital converter ADC and HDMI signal receiving and decoding device judges input is analog video signal or digital video signal, and detect the form of video, by the I2C serial line interface analog to digital converter ADC is set then and HDMI signal receiving and decoding device is done corresponding processing program;
C) the digital video image processor receives the digital video signal of analog to digital converter ADC and the output of HDMI signal receiving and decoding device, and digital video signal is sent into the high-speed data memory interface circuit;
D) the digital video image processor to the digital of digital video data of storing in the high-speed data memory interface circuit amplify, dwindle, enhancing and denoising;
E) the digital video image processor carries out brightness and colourity processing to the digital of digital video data of storing in the high-speed data memory interface circuit;
F) OSD produces and the image overlay device produces the wicket data or reads image data and they are sent to the high-speed data memory interface circuit from the SD card;
G) the digital video image processor is delivered to the output digital video signal converter to video data stored in the high-speed data memory controller output buffer;
H) output digital video signal converter digital video signal that the digital video image processor processing is crossed converts LVDS or TMDS format signal to;
I) LCD display is accepted LVDS format digital video signal, and shows the image information of human eye reading comprehension;
J) according to the difference of experiment content, the experimenter observes different digital video signals with oscillograph at signal observer 1, signal observer 2, signal observer 3, signal observer 4, signal observer 5, signal observer 6 and signal observer 7.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2010101696144A CN101866574B (en) | 2010-05-07 | 2010-05-07 | Digital video experiment device and experiment method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2010101696144A CN101866574B (en) | 2010-05-07 | 2010-05-07 | Digital video experiment device and experiment method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN101866574A true CN101866574A (en) | 2010-10-20 |
| CN101866574B CN101866574B (en) | 2011-08-24 |
Family
ID=42958280
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2010101696144A Expired - Fee Related CN101866574B (en) | 2010-05-07 | 2010-05-07 | Digital video experiment device and experiment method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN101866574B (en) |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102063393A (en) * | 2010-11-09 | 2011-05-18 | 福州瑞芯微电子有限公司 | Method and device for superposition processing of image data or audio data |
| CN102427514A (en) * | 2011-10-14 | 2012-04-25 | 天津天地伟业数码科技有限公司 | Network high-definition spherical camera and method of realizing OSD (On-screen Display) menu thereof |
| CN102685439A (en) * | 2012-05-28 | 2012-09-19 | 上海海事大学 | Device and method for realizing image data transmission control with field programmable gate array (FPGA) |
| CN104717408A (en) * | 2013-12-11 | 2015-06-17 | 廖彩姿 | Light control equipment of image acquisition mechanism |
| CN104796628A (en) * | 2015-04-17 | 2015-07-22 | 广州炫智电子科技有限公司 | Video signal recognition circuit |
| CN107181921A (en) * | 2017-05-06 | 2017-09-19 | 滨州学院 | One kind is directed to the enhanced processing unit of picture signal |
| TWI795410B (en) * | 2018-06-08 | 2023-03-11 | 圓剛科技股份有限公司 | Hdmi image processing system and method of color space quantization correction |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20070065800A1 (en) * | 2005-09-19 | 2007-03-22 | Delta Electronics, Inc. | Display apparatus and video wall having the same |
| CN201035823Y (en) * | 2007-05-09 | 2008-03-12 | 南京捷辉科技有限公司 | Digital television course experiment system |
| CN101237365A (en) * | 2008-01-28 | 2008-08-06 | 宁波大学 | EDA network testing system and testing method |
| CN201219902Y (en) * | 2008-04-30 | 2009-04-15 | 汕头超声仪器研究所有限公司 | Graph-synthesizing device of whole digital b-ultrasound instrument |
| CN201383233Y (en) * | 2009-03-24 | 2010-01-13 | 庄辉 | Digital exploration test system |
-
2010
- 2010-05-07 CN CN2010101696144A patent/CN101866574B/en not_active Expired - Fee Related
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20070065800A1 (en) * | 2005-09-19 | 2007-03-22 | Delta Electronics, Inc. | Display apparatus and video wall having the same |
| CN201035823Y (en) * | 2007-05-09 | 2008-03-12 | 南京捷辉科技有限公司 | Digital television course experiment system |
| CN101237365A (en) * | 2008-01-28 | 2008-08-06 | 宁波大学 | EDA network testing system and testing method |
| CN201219902Y (en) * | 2008-04-30 | 2009-04-15 | 汕头超声仪器研究所有限公司 | Graph-synthesizing device of whole digital b-ultrasound instrument |
| CN201383233Y (en) * | 2009-03-24 | 2010-01-13 | 庄辉 | Digital exploration test system |
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102063393A (en) * | 2010-11-09 | 2011-05-18 | 福州瑞芯微电子有限公司 | Method and device for superposition processing of image data or audio data |
| CN102063393B (en) * | 2010-11-09 | 2013-02-27 | 福州瑞芯微电子有限公司 | Method and device for superposition processing of image data or audio data |
| CN102427514A (en) * | 2011-10-14 | 2012-04-25 | 天津天地伟业数码科技有限公司 | Network high-definition spherical camera and method of realizing OSD (On-screen Display) menu thereof |
| CN102685439A (en) * | 2012-05-28 | 2012-09-19 | 上海海事大学 | Device and method for realizing image data transmission control with field programmable gate array (FPGA) |
| CN104717408A (en) * | 2013-12-11 | 2015-06-17 | 廖彩姿 | Light control equipment of image acquisition mechanism |
| CN104717408B (en) * | 2013-12-11 | 2019-09-17 | 廖彩姿 | Light control equipment of image acquisition mechanism |
| CN104796628A (en) * | 2015-04-17 | 2015-07-22 | 广州炫智电子科技有限公司 | Video signal recognition circuit |
| CN107181921A (en) * | 2017-05-06 | 2017-09-19 | 滨州学院 | One kind is directed to the enhanced processing unit of picture signal |
| TWI795410B (en) * | 2018-06-08 | 2023-03-11 | 圓剛科技股份有限公司 | Hdmi image processing system and method of color space quantization correction |
Also Published As
| Publication number | Publication date |
|---|---|
| CN101866574B (en) | 2011-08-24 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN101866574B (en) | Digital video experiment device and experiment method | |
| CN102547179B (en) | Synchronous display method for hand-held device and television | |
| CN101617286A (en) | The picture adjustment methods and the device that are used for image display | |
| US10805680B2 (en) | Method and device for configuring image mode | |
| CN104023182A (en) | Character superimposition device and superposition method based on FPGA | |
| CN108391166A (en) | Ultra high-definition TV and its display methods and computer readable storage medium | |
| US20080297531A1 (en) | Color gamut component analysis apparatus, method of analyzing color gamut component, and color gamut component analysis program | |
| JPH11146349A (en) | Image converter and image conversion method | |
| US9020044B2 (en) | Method and apparatus for writing video data in raster order and reading video data in macroblock order | |
| TWI326189B (en) | Method and apparatus for suppressing cross-color in a video display device | |
| CN104378575B (en) | The method of image signal transmission and device | |
| CN1980400A (en) | Image capture apparatus and method, recording medium for memorizing program executing the method | |
| CN106296614A (en) | Image processing apparatus and image processing method | |
| CN100543827C (en) | LCD and image edge enhancement method thereof | |
| CN101729884B (en) | Image acquiring device and image preprocessing method | |
| CN104410884A (en) | Synchronous and asynchronous playing player for LED and LCD display screens | |
| CN100493171C (en) | Method for converting video-frequency signal format | |
| CN112235521B (en) | Method, device and equipment for realizing subtitle conversion | |
| CN201774614U (en) | Hardware circuit of composite video conversion interface | |
| CN102025936A (en) | Video aspect ratio conversion method and device | |
| CN105898178A (en) | Signal processing method and signal processor | |
| CN102054460A (en) | Display equipment | |
| CN101090473A (en) | Method for raising high clear video image display quality using linear deinterleaving process | |
| CN104602101B (en) | television system | |
| CN104410904A (en) | Video playing method and video playing device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| C17 | Cessation of patent right | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20110824 Termination date: 20140507 |