CN101860372B - Wireless communication receiver and signal processing method - Google Patents
Wireless communication receiver and signal processing method Download PDFInfo
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- CN101860372B CN101860372B CN2010100000179A CN201010000017A CN101860372B CN 101860372 B CN101860372 B CN 101860372B CN 2010100000179 A CN2010100000179 A CN 2010100000179A CN 201010000017 A CN201010000017 A CN 201010000017A CN 101860372 B CN101860372 B CN 101860372B
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
- H04L1/0056—Systems characterized by the type of code used
- H04L1/0071—Use of interleaving
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/25—Error detection or forward error correction by signal space coding, i.e. adding redundancy in the signal constellation, e.g. Trellis Coded Modulation [TCM]
- H03M13/253—Error detection or forward error correction by signal space coding, i.e. adding redundancy in the signal constellation, e.g. Trellis Coded Modulation [TCM] with concatenated codes
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/25—Error detection or forward error correction by signal space coding, i.e. adding redundancy in the signal constellation, e.g. Trellis Coded Modulation [TCM]
- H03M13/255—Error detection or forward error correction by signal space coding, i.e. adding redundancy in the signal constellation, e.g. Trellis Coded Modulation [TCM] with Low Density Parity Check [LDPC] codes
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/27—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes using interleaving techniques
- H03M13/2732—Convolutional interleaver; Interleavers using shift-registers or delay lines like, e.g. Ramsey type interleaver
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
- H04L1/0045—Arrangements at the receiver end
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
- H04L1/0056—Systems characterized by the type of code used
- H04L1/0064—Concatenated codes
- H04L1/0065—Serial concatenated codes
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
- H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
- H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
- H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
- H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
- H03M13/13—Linear codes
- H03M13/15—Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem [BCH] codes
- H03M13/151—Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem [BCH] codes using error location or error correction polynomials
- H03M13/152—Bose-Chaudhuri-Hocquenghem [BCH] codes
Abstract
The invention provides a wireless communication receiver and a signal processing method. The wireless communication receiver includes a first signal processing module, a second signal processing module, and a de-interleaver, wherein the first signal processing module is arranged for receiving a wireless communication signal and processing the wireless communication signal to generate a first output; the de-interleaver is coupled between the first signal processing module and the second signal processing module and includes a plurality of branches implemented for de-interleaving the first output to generate a second output; the de-interleaver starts outputting the second output to the second signal processing module for further signal processing before all buffers included in the branches are full and informs the second signal processing module of data derived from one or more buffers included in the branches, so as to shorten the decoding time.
Description
Technical field
The present invention is relevant for a kind of wireless communication receiver and signal processing method.
Background technology
Known interleaving/de-interleaving (interleaving/de-interleaving) is used in various communication systems usually.Fig. 1 is the schematic diagram of known interweave framework and the framework that deinterleaves.The known interleaver 10 that is positioned at the transmitting terminal of channel 30 comprise index respectively be 0,1,2, the B bar branch of 3......B-1.In addition, the branch of known interleaver 10 has different buffer lengths.For example, branch 0 is not for having the direct connection of buffer, branch 1,2,3 and B-1 have respectively buffer 14,15,16 and 17, in order to 1xM, 2xM, 3xM and (B-1) buffer length of xM to be provided respectively.The known deinterleaver 20 that is positioned at the receiving terminal of channel 30 comprises the B bar branch of indexing respectively as 0......B-4, B-3, B-2 and B-1.In addition, the branch of known deinterleaver 20 has different buffer lengths.For example, the B-1 of branch is not for having the direct connection of buffer, the B-2 of branch, B-3, B-4 and 0 have respectively buffer 24,25,26 and 27, as seen from the figure, the 0......B-4 of branch, B-3, B-2 and the B-1 of known deinterleaver 20 have and the B-1...... of branch, 3,2 of known interleaver 10,1 and 0 identical buffer length.By using switch 11,12, the 21 and 22 known interleaver 10 of operation and known deinterleavers 20, in order to sequentially and circularly to select these a plurality of branches.Because the details of operation of known interleaver 10 and known deinterleaver 20 is known by the person of ordinary skill in the field, for succinctly repeating no more.
According to known design, known deinterleaver 20 can not launched acquisition and process level (for example decoder) from data bit or symbol to the signal of back of branch, until known deinterleaver 20 full (be that buffer in branch is full, for example buffer 24-27 is full), in specific communication system, this will cause the serious delay that deinterleaves.In other words, the signal of back is processed the necessary input data of waiting for from known deinterleaver 20 of level.For example, the buffer 27 with the longest buffer length less than but have under the full situation of other buffers of shorter buffer length, known deinterleaver 20 directly abandons acquisition from any data bit or the symbol of these branches because all branches of known deinterleaver 20 also less than.Full at the buffer 27 with the longest buffer length, mean under another full situation of all buffers of branch of known deinterleaver 20, allow known deinterleaver 20 beginnings orders and circularly the output acquisition process level from data bit or symbol to the signal of back of these branches.
From the above, deinterleave and postpone to depend on the value of B and M.More particularly, deinterleave and postpone to equal M* (B-1) * B.For particular communications system, due to the delay that deinterleaves, the capture time of receiver may be quite long.With digital ground multimedia broadcast (Digital Terrestrial Multimedia Broadcasting, DTMB) receiver is example, if use pattern 1 (B=52 and M=240), when pseudorandom (pseudo-random) noise sequence of each signal frame had 945 symbols (being PN=945), deinterleaving postponed to be substantially equal to 106.25ms.If use pattern 2 (B=52 and M=720), when PN=945, deinterleaving postpones to be substantially equal to 318.75ms.Therefore, need the mechanism of a kind of novelty of design to remove to reduce the required time of known deinterleaver of flowing through, thereby improve the overall performance of receiving terminal.
Summary of the invention
In view of this, the invention provides a kind of wireless communication receiver and signal processing method to address the above problem.
The invention provides a kind of wireless communication receiver, comprising: the first signal processing module, in order to receiving wireless communication signals, and this wireless communication signals is processed, to produce the first output; The secondary signal processing module; And deinterleaver, be coupled between this first signal processing module and this secondary signal processing module, this deinterleaver comprises a plurality of branches, in order to this first output is deinterleaved to produce the second output, wherein, before all buffers of these a plurality of branches have been expired, for further signal processing, this deinterleaver begins to export this and second exports this secondary signal processing module to, and this deinterleaver further will capture data notification from one or more non-full buffers of this a plurality of branches to this secondary signal processing module.
The present invention separately provides a kind of signal processing method, comprising: receive wireless communication signals, and this wireless communication signals is processed, to produce the first output; According to a plurality of branches, this first output is deinterleaved to produce the second output; Before all buffers of these a plurality of branches have been expired, begin to export this second signal that exports the back to and process level; And will capture from the data notification of one or more non-full buffers of this a plurality of branches and process grade to the signal of this back.
Utilize wireless communication receiver provided by the invention and signal processing method, when all buffers of the branch of deinterleaver are not all completely the time, the output that can deinterleave in advance, thereby minimizing decoding required time.
Description of drawings
Fig. 1 is the schematic diagram of known interweave framework and the framework that deinterleaves;
Fig. 2 is the block schematic diagram according to the first embodiment of wireless communication receiver of the present invention;
Fig. 3 is the block schematic diagram according to the second embodiment of wireless communication receiver of the present invention;
Fig. 4 is the flow chart according to the general signal processing method of one embodiment of the invention.
Embodiment
Used some vocabulary to censure specific components in the middle of specification and claim.The person of ordinary skill in the field should understand, and same assembly may be called with different nouns by manufacturer.This specification and claims not with the difference of title as the mode of distinguishing assembly, but with assembly the difference on function as distinguishing criterion.In specification and claim, be open language mentioned " comprising " in the whole text, therefore should be construed to " comprise but be not limited to ".In addition, " couple " word and comprise any means that indirectly are electrically connected that directly reach at this.By the narration of following preferred embodiment and coordinate Fig. 2 to Fig. 4 in full that the present invention is described, but the device in following narration, assembly and method, step are to explain the present invention, and should not be used for limiting the present invention.
For simplified characterization, the present invention proposes to take full advantage of error-detecting and the error correction ability of decoder, thereby reaches the purpose that generation is exported in advance.For example, decoder is low-density checksum (low-density parity check, LDPC) decoder, the bit and judge according to the parity check result whether decode results is errorless of can righting the wrong.Therefore, before all buffers of deinterleaver had been expired, perhaps the data that cushioned in buffer can arrive sufficient data volume to allow ldpc decoder to have errorless decoding output.Based on above-mentioned observation, a kind of output mechanism that deinterleaves is in advance proposed.For example, the output mechanism that deinterleaves in advance may be implemented in wireless communication receiver (for example DTMB receiver), in order to improve scan channel speed and/or channel switch speed.In order more clearly to understand technical characterictic of the present invention, next preferred embodiment of the present invention will be described.
Fig. 2 is the block schematic diagram according to the first embodiment of wireless communication receiver of the present invention.Wireless communication receiver 200 comprises first signal processing module 202, deinterleaver 204 and secondary signal processing module 206.In the present embodiment, first signal processing module 202 is embodied as to receive wireless communication signals S_IN, and S_IN processes to this wireless communication signals, in order to produce the first output S1; Deinterleaver 204 is coupled between first signal processing module 202 and secondary signal processing module 206, comprises a plurality of branches, in order to the first output S1 is deinterleaved to produce the second output S2; Secondary signal processing module 206 is embodied as in order to this second output S2 is processed to produce the receiver output S_OUT corresponding to wireless communication signals S_IN.For example, deinterleaver 204 has the internal hardware configuration identical with known deinterleaver 20 shown in Figure 1.Yet special design deinterleaver 204 of the present invention began to export the second output S2 to secondary signal processing module 206 before all buffers of branch have been expired, was used for further signal and processed.In addition, deinterleaver 204 of the present invention is also to secondary signal processing module 206 notification datas, wherein this data acquisition in branch one or more less than buffer.Under this mode, although the second output S2 can comprise invalid data bit or unblind, secondary signal processing module 206 still can properly be processed the second output S2.In addition, when deinterleaver begins to export when deinterleaving as a result, this moment less than the number of buffers height depend on the disposal ability of the secondary signal processing module 206 of back.For example, when secondary signal processing module 206 can be dealt carefully with the second output S2 with more invalid data bits by deinterleaver 204 notices or unblind, allowed it to produce in advance the second output S2 to secondary signal processing module 206 before deinterleaver 204 is full.In order more clearly to describe technical characterictic of the present invention, next the DTMB receiver as the preferred embodiment of wireless communication receiver 200 will be described.Yet only for giving an example, the present invention is not as limit.Due to all buffers full after deinterleaver just export the result that deinterleaves delays that cause deinterleaving, other wireless communication receivers of the hardship of delay so the concept of the output mechanism that deinterleaves in advance proposed by the invention can be applicable to be deinterleaved.These optionally design and without prejudice to spirit of the present invention, all belong to the scope that the present invention advocates.
When wireless communication receiver 200 is the DTMB receiver, therefore first signal processing module 202 comprises, but be not limited to, tuner 212, automatic gain are controlled (automatic gain control, AGC) unit 214, analog to digital converter (analog-to-digital converter, ADC) 216, filtering/synchronous circuit 218 and channel estimating (channel estimation, CE)/balanced (equalization, EQ)/channel condition information (channel state information, CSI) treatment circuit 220.And secondary signal processing module 206 includes but not limited to, de-mapping device 222, ldpc decoder 224, female (Bose-Chaudhuri-Hocquenghem, the BCH) decoder 226 of Bo Si-Cha Dehuli-Huo Kun lattice and descrambler (descrambler) 228.For clearer, next operation and the function of above every part will be described simply.
212 couples of wireless communication signals S_IN of tuner (i.e. DTMB signal) carry out down-conversion and channel is selected, and wherein, this wireless communication signals S_IN is received by wireless communication receiver 200.Then, AGC unit 214 execution automatic gains controls are regulated in order to adaptability and being applied to the gain of tuner 212 outputs, thereby make the amplitude of the input signal that inputs to ADC 216 be reduced to special range.Filtering/synchronous circuit 218 is embodied as in order to executive signal filtering and simultaneous operation.Can use channel estimator, equalizer (for example OFDM (orthogonal frequency-division-multiplexing, OFDM) equalizer) and CSI generator to implement CE/EQ/CSI treatment circuit 220.Therefore, produce the first output S1 to deinterleaver 204, wherein, the first output S1 comprises equalizer output S_EQ and CSI output S_CSI.204 couples of equalizer output S_EQ of deinterleaver and CSI output S_CSI deinterleave, to produce the second output S2, wherein, the CSI output S_CSI ' that the second output S2 comprises the equalizer output S_EQ ' that has deinterleaved and deinterleaved.Then, CSI output S_CSI ' the generation solution mapping result S_SB that de-mapping device 222 is exported S_EQ ' according to the equalizer that has deinterleaved and deinterleaved wherein, separates mapping result S_SB and comprises a plurality of soft bits (soft bit).Ldpc decoder 224 and BCH decoder 226 are carried out ISN (inner-code) decoding (being LDPC decoding) and outer code (outer-code) decoding (being BCH decoding) to separating mapping result S_SB in order.At last, the decoding output signal that 228 pairs of descrambler result from BCH decoder 226 carries out descrambling, to produce receiver output S_OUT.
Main concept of the present invention is to make deinterleaver 204 have the output that deinterleaves in advance for secondary signal processing module 206.Because data bit or symbol from the non-full buffer of the branch that is contained in deinterleaver 204 are invalid, deinterleaver 204 must these are invalid data bit or the information of symbol be sent to secondary signal processing module 206, in order to allow secondary signal processing module 206 properly process second output S2.Consider receiver structure shown in Figure 2, next describe specific exemplary embodiment, process level in order to invalid data bit or symbol are notified to the signal of back.
In the first exemplary embodiment, deinterleaver 204 produces the respective indicator that is used for each unblind, wherein this unblind captures a self-contained non-full buffer in the branch of deinterleaver 204, and exports this respective indicator to de-mapping device 222.De-mapping device 222 is according to each unblind of respective indicator identification the second output S2, and produce solution mapping result S_SB to ldpc decoder 224 according to the second output S2, wherein this each unblind captures a non-full buffer from deinterleaver 204, and the second output S2 comprises that the equalizer output S_EQ ' that has deinterleaved and the CSI that has deinterleaved export S_CSI '.In addition, for acquisition each unblind from a non-full buffer of deinterleaver 204, configuration de-mapping device 222 is so that equal default value (for example " 0 ") corresponding to each soft bit of unblind.Because each invalid soft bit can be made as " 0 " by de-mapping device 222, the invalid soft bit that therefore inputs to the ldpc decoder 224 of the back operation of ldpc decoder 224 of can not degenerating.Under this mode, before all buffers of deinterleaver 204 had been expired, ldpc decoder 224 can carry out optimal decoding to separating mapping result S_SB.Should be noted, aforesaidly can be implemented by extra designator SI_1 from the designator of the unblind of a corresponding non-full buffer of deinterleaver 204 for acquisition, wherein this extra designator SI_1 is provided by deinterleaver 204 or CSI value.For example, when the buffer of the branch of deinterleaver 204 less than the time, output will be attended by the designator SI_1 of a logical value (for example " 1 ") from the symbol of this branch.On the other hand, completely the time, output will be attended by the designator SI_1 of another logical value (for example " 0 ") from the symbol of this branch when the buffer of the branch of deinterleaver 204.Under this mode, the de-mapping device 222 of back knows which symbol is effective and which symbol is invalid.Invalid as designator in order to a special symbol of indicating the second output S2 when using the CSI value, configuration deinterleaver 204 use default values (for example " 0 ") upgrade the original CSI value that is used for unblind, and this default value shows that corresponding symbol is effectively ungenuine.Specifically, the CSI value represents signal to noise ratio (signal-to-noise ratio, SNR).When the CSI value that is used for special symbol is " 0 ", show that the reliability of this special symbol is on duty mutually.
In the second exemplary embodiment, deinterleaver 204 produces corresponding the first designator that is used for each unblind, wherein this unblind captures a self-contained corresponding non-full buffer in the branch of deinterleaver 204, and should export de-mapping device 222 to by corresponding the first designator.For example, this first designator can be extra designator SI_1 or the CSI value that is set to " 0 ".De-mapping device 222 is identified each unblind according to corresponding the first designator, and produce solution mapping result S_SB according to the second output S2, wherein, this each unblind acquisition is from a corresponding non-full buffer of deinterleaver 204, and the second output S2 comprises that the equalizer output S_EQ ' that has deinterleaved and the CSI that has deinterleaved export S_CSI '.In addition, each unblind that corresponding the first designator that provides for previous deinterleaver 204 is identified, de-mapping device 222 corresponding the second designator SI_2 of output, be used for mutually should unblind a plurality of invalid soft bit.For example, a plurality of invalid soft bit that is used for a unblind will be attended by the corresponding second designator SI_2 of a logical value (for example " 1 "), and wherein these a plurality of invalid soft bit outputs are from de-mapping device 222.On the other hand, a plurality of effective soft bit that is used for a significant character will be attended by the first designator SI_1 of another logical value (for example " 0 "), and wherein these a plurality of effective soft bit outputs are from de-mapping device 222.Under this mode, the ldpc decoder 224 of back knows which soft bit is effective and which soft bit is invalid.Therefore, at first ldpc decoder 224 according to corresponding the second designator SI_2 identification acquisition each invalid soft bit from a unblind, then begins to carry out decoding to separating mapping result S_SB.In this exemplary embodiment, for acquisition each invalid soft bit from a unblind, ldpc decoder 224 makes invalid soft bit equal default value (for example " 0 ").Due to before by LDPC decoding actual treatment, each invalid soft bit is set to " 0 " by ldpc decoder 224, so the operation that invalid soft bit can not degenerated and be carried out by ldpc decoder 224.Under this mode, before all buffers of deinterleaver 204 had been expired, ldpc decoder 224 can carry out optimal decoding to the second output S2.Should be noted, aforesaid corresponding the second designator SI_2 for invalid soft bit can be substituted by the CSI value.Therefore, when to use the CSI value be invalid as corresponding the second designator SI_2 in order to the respective soft bit of indicating unblind, de-mapping device 222 makes the original CSI value corresponding to this invalid soft bit become default value (for example " 0 "), and this default value is effectively ungenuine in order to represent corresponding soft bit.
About the 3rd exemplary embodiment, before deinterleaver 204 begins the first output S1 is deinterleaved, initialization deinterleaver 204, thereby make each bit of all buffers in the branch of deinterleaver 204 become predetermined value (for example " 0 "), this predetermined value is in order to the data of the non-full buffer of expression acquisition in branch.Specifically, before the beginning that deinterleaves, all the CSI values in deinterleaver 204 all are initialized as predetermined value, then after the beginning that deinterleaves, upgrade the CSI value.Yet acquisition still has initial default value (i.e. " 0 ") from the corresponding CSI value of the unblind of non-full buffer.Therefore, have the CSI value of predetermined value when use as the aforesaid designator of acquisition from each symbol of a corresponding non-full buffer, after the beginning that deinterleaves, deinterleaver 204 need not the CSI value is changed.
In addition, because ldpc decoder 224 is decoder based on module (block), deinterleaver 204 more produces frame synchronization (frame sync), and this frame synchronization is synchronizeed with the module border (block boundary) that will be carried out by the decoder (being ldpc decoder 224) based on module the data of decoding.In other words, deinterleaver 204 produces frame synchronization, and in order to representing the initiating terminal of a frame, thereby ldpc decoder 224 knows the initial bits of a character code is at which.For example, a frame can be the integral multiple of LDPC module, and perhaps two frames that continue comprise one or more (for example five) LDPC module.Therefore, the frame synchronization that shows frame boundaries can help ldpc decoder 224 correct identification LDPC module border, thereby promotes the LDPC decoded operation.
Fig. 3 is the block schematic diagram according to the second embodiment of wireless communication receiver of the present invention.Wireless communication receiver 300 comprises first signal processing module 302, deinterleaver 304 and secondary signal processing module 306.In the present embodiment, first signal processing module 302 is configured to receive wireless communication signals S_IN, and S_IN processes to this wireless communication signals, in order to produce the first output S1 '; Deinterleaver 304 is coupled between first signal processing module 302 and secondary signal processing module 306, comprises a plurality of branches, in order to the first output S1 ' is deinterleaved to produce the second output S2 '; 306 couples of this second output S2 ' of secondary signal processing module process to produce the receiver output S_OUT corresponding to wireless communication signals S_IN.In one embodiment, deinterleaver 304 has the internal hardware configuration identical with known deinterleaver 20 shown in Figure 1.Yet special design deinterleaver 304 of the present invention began to export the second output S2 ' to secondary signal processing module 306 before all buffers of branch have been expired, was used for further signal and processed.In addition, deinterleaver 304 of the present invention is also to secondary signal processing module 306 notification datas, wherein this data acquisition in branch one or more less than buffer.Under this mode, although the second output S2 ' comprises invalid data, secondary signal processing module 306 still can properly be processed the second output S2 '.
Difference between the second embodiment shown in Figure 3 and the first embodiment shown in Figure 2 is that deinterleaver 304 is positioned between de-mapping device 308 and ldpc decoder 310.Therefore de-mapping device 308 produces the first output S1 ' according to equalizer output S_EQ and CSI output S_CSI, and wherein, equalizer output S_EQ and CSI output S_CSI produce from previous CE/EQ/CSI processing unit 220.Specifically, by the solution mapping output that merges equalizer output (for example constellation symbol) S_EQ and CSI output S_CSI, de-mapping device 308 produces the first output S1 ' (that is the solution mapping result that, comprises soft bit).For example, by equalizer output S_EQ is separated mapping, de-mapping device 308 produces a plurality of soft bits, then further these soft bits be multiply by CSI output S_CSI, in order to obtain the first output S1 '.
Be invalid due to acquisition from the data (soft bit) of the non-full buffer of deinterleaver 304, deinterleaver 304 must these are invalid the information of data (soft bit) be sent to secondary signal processing module 306, correctly process the second output S2 ' in order to allow secondary signal processing module 306.Consider receiver structure shown in Figure 3, next describe specific exemplary embodiment, in order to invalid data notification is processed level to the signal of back.
In the first exemplary embodiment, deinterleaver 304 produces the respective indicator SI_3 that is used for a plurality of soft bits, wherein the self-contained non-full buffer in the branch of deinterleaver 304 of this a plurality of soft bit acquisition.For example, when a buffer of the branch of deinterleaver 304 less than the time, output will be attended by the designator SI_3 of a logical value (for example " 1 ") from a plurality of soft bit of this branch.On the other hand, completely the time, output will be attended by the designator SI_3 of a logical value (for example " 0 ") from a plurality of soft bit of this branch when a buffer of the branch of deinterleaver 304.Under this mode, the ldpc decoder 310 of back knows which soft bit is effective and which soft bit is invalid.At first, ldpc decoder 310 is according to each soft bit of respective indicator SI_3 identification, and wherein, this each soft bit acquisition is from the corresponding non-full buffer of the branch of deinterleaver 304, and then, ldpc decoder 310 begins the second output S2 ' is carried out decoding.In addition, for acquisition each soft bit from the corresponding non-full buffer of this branch, ldpc decoder 310 makes this each soft bit equal default value (for example " 0 ").Before by LDPC decoding actual treatment, each invalid soft bit is set to " 0 " by ldpc decoder 310, so the operation that invalid soft bit can not degenerated and be carried out by ldpc decoder 310.Under this mode, before all buffers of deinterleaver 304 had been expired, ldpc decoder 310 can carry out optimal decoding to the second output S2 '.
In the second exemplary embodiment, for a plurality of invalid soft bit of acquisition from a non-full buffer of the branch of deinterleaver 304, deinterleaver 304 makes each invalid soft bit setting equal predetermined value (for example " 0 ").In other words, each the invalid soft bit that inputs to ldpc decoder 310 is set to " 0 ".Because invalid soft bit is " 0 ", the operation that therefore can not degenerate and be carried out by ldpc decoder 310, before all buffers of deinterleaver 304 had been expired, ldpc decoder 310 can carry out optimal decoding to the second output S2 '.
About the 3rd exemplary embodiment, before deinterleaver 304 begins the first output S1 ' is deinterleaved, initialization deinterleaver 304, thereby make each bit of all buffers in the branch of deinterleaver 304 become predetermined value (for example " 0 "), this predetermined value is in order to the data of the non-full buffer of expression acquisition in branch.In particular, before the beginning that deinterleaves, the soft bit of all in deinterleaver 304 all is initialized as " 0 ", then after the beginning that deinterleaves, will upgrade one or more soft bits.About acquisition each invalid soft bit from non-full buffer, this invalid soft bit still has initial default value (i.e. " 0 ").Therefore, need not to produce the extra designator from deinterleaver 304, in addition, after the beginning that deinterleaves, deinterleaver 304 need not this soft bit is changed.
In Fig. 2 and embodiment shown in Figure 3, ldpc decoder 224 or ldpc decoder 310 have this decode results correct ability whether of knowing.That is to say, the parity check of ldpc decoder will help to check whether decode results is correct.If parity check is correct, decode results is that correct probability is very high.In addition, the BCH decoder 226 of back also can help to check whether ldpc decoder output is correct.
In particular, BCH decoder 226 can operate in the error-detecting pattern of the holotype of replacement error-more, so BCH decoder 226 can help the location of mistakes in ldpc decoder output.
Note that the assembly that comprises in first signal processing module 202/302 and secondary signal processing module 206/306 can be used for implementing the DTMB receiver.Yet when using the output mechanism that deinterleaves in advance of the present invention in other wireless communication receivers, first signal processing module 202/302 and secondary signal processing module 206/306 must correspondingly be revised.For example, the decoder immediately following deinterleaver 204/304 back is not limited to ldpc decoder.More particularly, change the signal processing level of deinterleaver 204/304 back according to the design needs of wireless communication receiver structure.
In view of above-mentioned exemplary embodiment, the signal processing method that wireless communication receiver 200/300 uses can carry out simple summary by step shown in Figure 4, Fig. 4 is the flow chart according to the general signal processing method of one embodiment of the invention, and wherein this signal processing method is used by wireless communication receiver.
Step 402: use first signal processing module 202/302 to receive wireless communication signals (for example, the DTMB signal), then this wireless communication signals is processed, in order to produce the first output S1.
Step 404: deinterleaver 204/304 is in order to deinterleave to the first output S1 according to a plurality of branches that implement in the inner, to produce the second output S2.
Step 406: before all buffers of this a plurality of branches are full, use deinterleaver 204/304 to begin to export the second output S2 and process level (for example, the secondary signal processing module 206/306) to the signal of back.
Step 408: will capture from the data notification of one or more non-full buffers of this a plurality of branches of deinterleaver 204/304 and process level to the signal of back.
Should be noted, if result is roughly the same, need not to carry out according to step shown in Figure 4.In addition, any person of ordinary skill in the field can know the details of operation of each step, for succinctly repeating no more after reading above-mentioned paragraph relevant for wireless communication receiver 200 and wireless communication receiver 300 operations.
In sum, the present invention proposes when all buffers of the branch of deinterleaver have not been expired fully, decoding (for example LDPC decoding) to be carried out in the deinterleaver output in early stage.Therefore, the TV signal that receives that uses the output mechanism that deinterleaves in advance can reduce the DTMB receiver carries out the required time of decoding.Owing in advance decoding being carried out in deinterleaver output, selected the capture time of TV channel to reduce, scan channel time and/or switch to the required time of another TV channel from a TV channel and also effectively reduce.
The above embodiments only are used for enumerating embodiments of the present invention, and explain technical characterictic of the present invention, are not to limit category of the present invention.Any person of ordinary skill in the field is according to spirit of the present invention and unlabored change or isotropism arrangement all belong to the scope that the present invention advocates, interest field of the present invention should be as the criterion with claim.
Claims (23)
1. wireless communication receiver comprises:
The first signal processing module in order to receiving wireless communication signals, and is processed this wireless communication signals, to produce the first output;
The secondary signal processing module; And
Deinterleaver, be coupled between this first signal processing module and this secondary signal processing module, this deinterleaver comprises a plurality of branches, in order to this first output is deinterleaved to produce the second output, wherein, before all buffers of these a plurality of branches have been expired, this deinterleaver begins to export this and second exports this secondary signal processing module to so that further signal is processed, and this deinterleaver further will capture data notification from one or more non-full buffers of these a plurality of branches to this secondary signal processing module.
2. wireless communication receiver as claimed in claim 1, it is characterized in that, this deinterleaver produces the respective indicator that is used for each unblind, this each unblind acquisition is from the corresponding non-full buffer of these a plurality of branches, and this deinterleaver exports this respective indicator to this secondary signal processing module; This secondary signal processing module comprises:
Decoder; And
De-mapping device, be coupled between this deinterleaver and this decoder, in order to according to this respective indicator identification each unblind corresponding to corresponding non-full buffer, and this de-mapping device produces a plurality of soft bits to this decoder according to this second output, wherein, this de-mapping device makes each the invalid soft bit corresponding to this each unblind equal default value.
3. wireless communication receiver as claimed in claim 2, is characterized in that, this decoder is the low density parity check coding device, and this default value is 0.
4. wireless communication receiver as claimed in claim 2, is characterized in that, this decoder is based on the module decoder, and this deinterleaver further produces frame synchronization, this frame synchronization with will be synchronizeed by this module border based on the data of module decoder for decoding.
5. wireless communication receiver as claimed in claim 2, is characterized in that, this respective indicator channel condition information value that this deinterleaver is regulated of serving as reasons.
6. wireless communication receiver as claimed in claim 1, it is characterized in that, this deinterleaver produces corresponding the first designator that is used for each unblind, this each unblind acquisition is from the corresponding non-full buffer of these a plurality of branches, and this deinterleaver should export this secondary signal processing module to by corresponding the first designator; This secondary signal processing module comprises:
De-mapping device, couple this deinterleaver, in order to this corresponding first designator identification of foundation each unblind corresponding to corresponding non-full buffer, and this de-mapping device produces a plurality of soft bits according to this second output, wherein, corresponding the second designator of this de-mapping device output is used for a plurality of invalid soft bit corresponding to this each unblind; And
Decoder couples this de-mapping device, and in order to these a plurality of invalid soft bits of identification, and this decoder carries out decoding to these a plurality of soft bits, and wherein this decoder makes these a plurality of invalid soft bits equal default value.
7. wireless communication receiver as claimed in claim 6, is characterized in that, this corresponding first designator channel condition information value that this deinterleaver is regulated of serving as reasons.
8. wireless communication receiver as claimed in claim 6, is characterized in that, this corresponding second designator channel condition information value that this de-mapping device arranges of serving as reasons.
9. wireless communication receiver as claimed in claim 1, is characterized in that, this first signal processing module comprises de-mapping device, comprises this first output of a plurality of soft bits in order to generation; This deinterleaver produces respective indicator and is used for a plurality of invalid soft bits, and wherein these a plurality of invalid soft bit acquisitions are from the corresponding non-full buffer of these a plurality of branches; And this secondary signal processing module comprises decoder, couple this deinterleaver, in order to according to these a plurality of invalid soft bits of this respective indicator identification, this decoder carries out decoding to this second output that comprises a plurality of soft bits, wherein, this decoder makes these a plurality of invalid soft bits equal default value.
10. wireless communication receiver as claimed in claim 1, is characterized in that, this first signal processing module comprises de-mapping device, comprises this first output of a plurality of soft bits in order to generation; This deinterleaver makes acquisition equal default value from each invalid soft bit of the corresponding non-full buffer of these a plurality of branches; And this secondary signal processing module comprises decoder, couples this deinterleaver, in order to decoding is carried out in this second output that comprises a plurality of soft bits.
11. wireless communication receiver as claimed in claim 1, it is characterized in that, before this deinterleaver begins this first output is deinterleaved, each bit of all buffers of these a plurality of branches is initialized to default value, in order to will capture data notification from the non-full buffer of these a plurality of branches to this secondary signal processing module.
12. wireless communication receiver as claimed in claim 1 is characterized in that, this wireless communication receiver is the digital ground multimedia broadcast receiver.
13. a signal processing method comprises:
Receive wireless communication signals, and this wireless communication signals is processed, to produce the first output;
According to a plurality of branches, this first output is deinterleaved to produce the second output;
Before all buffers of these a plurality of branches have been expired, begin to export this second signal that exports the back to and process level; And
Process level for the signal of this back from the data notification of one or more non-full buffers of these a plurality of branches acquisition.
14. signal processing method as claimed in claim 13, it is characterized in that, notify the step of the signal processing level of this back to comprise: to produce the respective indicator that is used for each unblind, this each unblind acquisition is the corresponding non-full buffer of these a plurality of branches certainly, and this respective indicator is exported to the signal processing level of this back; And the operation that the signal of this back is processed level comprises:
Carry out and separate map operation, in order to according to this respective indicator identification each unblind corresponding to corresponding non-full buffer, and produce a plurality of soft bits according to this second output, wherein, this solution map operation makes each the invalid soft bit corresponding to this each unblind equal default value, and these a plurality of soft bits are carried out decoded operation.
15. signal processing method as claimed in claim 14 is characterized in that, this decoded operation is the low density parity check coding operation, and this default value is 0.
16. signal processing method as claimed in claim 14 is characterized in that, this decoded operation is based on the module decoded operation, and the step that this first output is deinterleaved further comprises:
Produce frame synchronization, this frame synchronization with will be synchronizeed by this module border based on the data of module decoded operation decoding.
17. signal processing method as claimed in claim 14 is characterized in that, the step that produces this respective indicator comprises: regulate channel condition information, in order to produce this respective indicator.
18. signal processing method as claimed in claim 13, it is characterized in that, notify the step of the signal processing level of this back to comprise: to produce corresponding the first designator that is used for each unblind, this each unblind acquisition is from the corresponding non-full buffer of this a plurality of branches, and will this corresponding first designator exports the signal processing grade of this back to; The operation that the signal of this back is processed level comprises:
Carry out and separate map operation, in order to this corresponding first designator identification of foundation each unblind corresponding to corresponding non-full buffer, and produce a plurality of soft bits according to this second output, wherein, this separates corresponding the second designator of map operation output for a plurality of invalid soft bit corresponding to this each unblind; And
Carry out decoded operation, in order to these a plurality of invalid soft bits of identification, and these a plurality of soft bits that produce from this solution map operation are carried out decoding, wherein this decoded operation makes these a plurality of invalid soft bits equal default value.
19. signal processing method as claimed in claim 18 is characterized in that, the step that produces this corresponding the first designator comprises: regulate channel condition information, in order to produce this corresponding first designator.
20. signal processing method as claimed in claim 18 is characterized in that, this corresponding second designator channel condition information value that this solution map operation arranges of serving as reasons.
21. signal processing method as claimed in claim 13 is characterized in that, this wireless communication signals is processed to produce this first step of exporting comprise: carry out and separate map operation, comprise this first output of a plurality of soft bits in order to generation; Notify the step of the signal processing level of this back to comprise: produce respective indicator and be used for a plurality of invalid soft bits, wherein these a plurality of invalid soft bits capture the corresponding non-full buffer of these a plurality of branches certainly; And the operation that the signal of this back is processed level comprises:
Carry out decoded operation according to this respective indicator, in order to these a plurality of invalid soft bits of identification, decoding is carried out in this second output that comprises a plurality of soft bits, wherein, this decoded operation makes these a plurality of invalid soft bits equal default value.
22. signal processing method as claimed in claim 13 is characterized in that, this wireless communication signals is processed to produce this first step of exporting comprise: carry out and separate map operation, comprise this first output of a plurality of soft bits in order to generation; The step that this first output is deinterleaved further comprises: make acquisition equal default value from each invalid soft bit of the corresponding non-full buffer of these a plurality of branches; And the operation that the signal of this back is processed level comprises: carry out decoded operation, in order to decoding is carried out in this second output that comprises a plurality of soft bits.
23. signal processing method as claimed in claim 13 further comprises:
Before beginning this first output is deinterleaved, each bit of all buffers of initialization this a plurality of branches is default value, in order to will capture from the data notification of the non-full buffer of these a plurality of branches the signal processing to this back grade.
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| US12/419,312 | 2009-04-07 | ||
| US12/419,312 US8284873B2 (en) | 2009-04-07 | 2009-04-07 | Wireless communication receiver having de-interlever and related signal processing method thereof |
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| CN101860372A CN101860372A (en) | 2010-10-13 |
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| US8473820B2 (en) * | 2009-05-19 | 2013-06-25 | Electronics And Telecommunications Research Institute | Apparatus and method for transmitting and receiving data |
| TWI470980B (en) * | 2012-12-26 | 2015-01-21 | Mstar Semiconductor Inc | Decoding method and multimedia displaying system |
| CN103916717B (en) * | 2013-01-06 | 2017-04-19 | 晨星软件研发(深圳)有限公司 | Decoding method and multimedia playing system |
| US10879936B2 (en) * | 2018-08-23 | 2020-12-29 | Keysight Technologies, Inc. | Methods, systems, and computer readable media for de-interleaving data in a communication system |
Citations (2)
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| CN1954531A (en) * | 2004-05-18 | 2007-04-25 | 皇家飞利浦电子股份有限公司 | Transport channel decoding management in a UMTS mobile receiver |
| CN101212431A (en) * | 2006-12-27 | 2008-07-02 | 鼎芯通讯（上海）有限公司 | Baseband decoder circuit and streamline operation method |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US5483541A (en) * | 1993-09-13 | 1996-01-09 | Trw Inc. | Permuted interleaver |
| US5771081A (en) * | 1994-02-28 | 1998-06-23 | Korea Telecommunication Authority | Bit system for transmitting digital video data |
| US5719875A (en) * | 1996-06-11 | 1998-02-17 | Lucent Technologies Inc. | Systematic convolution interleavers and deinterleavers |
| US7770010B2 (en) * | 2000-09-18 | 2010-08-03 | Wideband Semiconductors Inc. | Dynamically configurable interleaver scheme using at least one dynamically changeable interleaving parameter |
| KR20060004198A (en) * | 2004-07-08 | 2006-01-12 | 삼성전자주식회사 | Method and device for management buffer of block deinterleaver in mobile communication system |
| US7787848B2 (en) * | 2007-09-19 | 2010-08-31 | Mediatek Inc. | Automatic gain control method for receiver and apparatus thereof |
| JP4577350B2 (en) * | 2007-11-27 | 2010-11-10 | ソニー株式会社 | Reception device, communication system, reception method, and program |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN1954531A (en) * | 2004-05-18 | 2007-04-25 | 皇家飞利浦电子股份有限公司 | Transport channel decoding management in a UMTS mobile receiver |
| CN101212431A (en) * | 2006-12-27 | 2008-07-02 | 鼎芯通讯（上海）有限公司 | Baseband decoder circuit and streamline operation method |
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| US20100254493A1 (en) | 2010-10-07 |
| CN101860372A (en) | 2010-10-13 |
| TW201037980A (en) | 2010-10-16 |
| US8284873B2 (en) | 2012-10-09 |
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