CN101860323A - Device, system and method for correcting direct current offset - Google Patents
Device, system and method for correcting direct current offset Download PDFInfo
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- CN101860323A CN101860323A CN 201010170213 CN201010170213A CN101860323A CN 101860323 A CN101860323 A CN 101860323A CN 201010170213 CN201010170213 CN 201010170213 CN 201010170213 A CN201010170213 A CN 201010170213A CN 101860323 A CN101860323 A CN 101860323A
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- direct current
- integrator
- current offset
- correction apparatus
- drift correction
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Abstract
The invention discloses a device, a system, and a method for correcting direct current offset. The device for correcting direct current offset comprises a low-pass filter unit, an amplification unit and a direct current offset correcting unit, wherein the output end of the low-pass filter unit is connected with the input end of the amplification unit; and the direct current offset correcting unit comprises an integrator which provides two kinds of time constants and performs integration on output signals of the amplification unit and feeds back the integrated signals to the input end of the low-pass filter unit. In the technical scheme provided by the invention, direct current offset of a direct down-conversion receiver can be directly corrected by using the integrator with changeable time constants, so that the technical scheme ensures that the direct current offset can be corrected to an expected value in short time when the integrator is in a small time constant model; and the integrator is regulated to a large time constant model after the correctness is finished and relatively low corner frequency is formed to avoid the distortion of the output signal.
Description
Technical field
The present invention relates to technical field, particularly relate to a kind of DC drift correction apparatus, system and method.
Background technology
Wireless receiver mainly comprises super-heterodyne architecture receiver and two types of direct down-conversion receivers at present, wherein, and super-heterodyne architecture receiver structure complexity, exist the mirror image to disturb, need high Q value, bulky IF filter simultaneously, therefore make complex system, integrated difficulty.And directly the local oscillator of down-conversion receiver equates with carrier frequency, directly radiofrequency signal is transformed to base band, does not therefore exist mirror image to disturb, and does not need the mirror image interference suppression filter.The saving of ifd module is simplified system greatly, helps the integrated of monolithic system.The amplification of synchronous signal and filtering are all mainly carried out in base band, have reduced energy consumption.Therefore directly the down-conversion receiver has been subjected to extensive concern at wireless communication field.
For direct down-conversion receiver, the most serious problem is exactly the problem of direct current offset at present.Direct current offset mainly is that the self-mixing owing to local oscillation signal produces in downconversion process.Direct current offset makes the signal to noise ratio variation on the one hand, also may cause the amplifiers at different levels behind the frequency mixer saturated on the other hand, can't amplify useful signal, if direct current offset enters digital baseband, can produce further influence to the performance of whole receiver system.
In the prior art, can be by detecting the carrier wave leakage signal power of delivery outlet, feed back to input then and bring in the leakage of inhibition local oscillation signal, thereby realize the correction of direct current offset, but this method not only circuit realizes complicated, correction rate is also very slow, can't be applicable to the system that the response time is had higher requirements.Another kind of mode is to handle by digital form, do not carry out the correction of direct current offset behind signal process filter and the amplifying circuit, but by handling in the digital circuit territory behind the analog-digital converter, but this mode has limited the dynamic change scope of filter and amplifier to a great extent, and treatment effeciency is very low.
Summary of the invention
For solving the problems of the technologies described above, the invention provides a kind of DC drift correction apparatus, system and method, to realize the quick correction to direct current offset, technical scheme is as follows:
A kind of DC drift correction apparatus comprises low-pass filter unit, amplifying unit and direct current offset correcting unit,
The output of described low-pass filter unit is connected with the input of described amplifying unit;
Described direct current offset correcting unit comprises that one can provide the integrator of two kinds of time constants, and described direct current offset correcting unit is carried out integration to the output signal of described amplifying unit, and with the input of the signal feedback behind the integration to described low-pass filter unit.
Preferably, the input voltage of described integrator selects circuit to be connected to the input of operational amplifier through resistance; Described resistance selects circuit to be made of selector switch and a plurality of resistance, is used to realize the path of two kinds of different resistances;
Wherein, the corresponding large time constant pattern with described integrator of high value path, the corresponding and described integrator of low resistance path hour between the constant pattern.
Preferably, described amplifying unit is a variable gain amplifier.
Preferably, corresponding to the every kind of yield value that is provided of described variable gain amplifier, described resistance selects circuit that the path of two kinds of different resistances is provided respectively.
A kind of DC offset correction method is used above-mentioned DC drift correction apparatus, and this method comprises:
When described device entering signal receiving mode, constant pattern between described integrator is adjusted to hour;
When direct current offset satisfies the reception demand, described integrator is adjusted to the large time constant pattern.
A kind of direct current offset correction systems comprises two above-mentioned DC drift correction apparatus, and wherein, the output of first DC drift correction apparatus is connected with the input of second DC drift correction apparatus.
A kind of DC offset correction method is characterized in that, uses above-mentioned direct current offset correction systems, and this method comprises:
When described system entering signal receiving mode, constant pattern between the integrator of described first DC drift correction apparatus and second DC drift correction apparatus is adjusted to hour simultaneously;
When direct current offset satisfies the reception demand, the integrator of described first DC drift correction apparatus is adjusted to the large time constant pattern; After the loop stability that described DC drift correction apparatus constitutes, the integrator of described second DC drift correction apparatus is adjusted to the large time constant pattern.
Technical scheme provided by the present invention, the variable integrator of constant service time is proofreaied and correct the direct current offset of direct down-conversion receiver, during the constant pattern, can guarantee at short notice direct current to be proofreaied and correct to desired value between integrator is in hour.After correction is finished, integrator is adjusted to the large time constant pattern, have lower corner frequency this moment, to avoid output signal generation distortion.
Description of drawings
In order to be illustrated more clearly in the embodiment of the invention or technical scheme of the prior art, to do simple the introduction to the accompanying drawing of required use in embodiment or the description of the Prior Art below, apparently, accompanying drawing in describing below only is some embodiments of the present invention, for those of ordinary skills, under the prerequisite of not paying creative work, can also obtain other accompanying drawing according to these accompanying drawings.
Fig. 1 is the structural representation of a kind of direct down-conversion receiver provided by the present invention;
Fig. 2 is the structural representation of DC drift correction apparatus provided by the present invention;
Fig. 3 is the flow chart of a kind of DC offset correction method provided by the present invention;
Fig. 4 is the structural representation of the direct down-conversion receiver of another kind provided by the present invention
Fig. 5 is the flow chart of another kind of DC offset correction method provided by the present invention.
Embodiment
Below in conjunction with the accompanying drawing in the embodiment of the invention, the technical scheme in the embodiment of the invention is clearly and completely described, obviously, described embodiment only is the present invention's part embodiment, rather than whole embodiment.Based on the embodiment among the present invention, those of ordinary skills belong to the scope of protection of the invention not making the every other embodiment that is obtained under the creative work prerequisite.
Figure 1 shows that the structural representation of down-conversion receiver provided by the present invention, comprise reception antenna, low noise amplifier, frequency mixer, low-pass filter unit, amplifying unit, direct current offset correcting unit, equalizer and analog-digital converter.
The effect of low noise amplifier is to amplify the wireless signal that antenna receives, and the effect of frequency mixer is the signal that amplified through low noise amplifier, and with the local oscillation signal mixing that produces from the chip internal phase-locked loop, mixing goes out the low frequency useful signal; The signal of Lin Dao and local oscillation signal can be mixed to low frequency too, and the frequency of sort signal is positioned near 2 times of useful signal bandwidth, and the effect of low-pass filter unit is the filtering sort signal; Amplifying unit amplifies filtered signal; The effect of direct current offset correcting unit is the direct current offset that suppresses mixed frequency signal; The effect of equalizer is the group delay of compensating filter, improves the EVM (Error Vector Magnitude, error vector magnitude) of system.The effect of analog to digital converter is that analog signal conversion is become digital signal, delivers to digital baseband then and handles.
Below will the DC drift correction apparatus that this three part of low-pass filter unit, amplifying unit and direct current offset correcting unit in the down-conversion receiver provided by the present invention is constituted be described in further detail, referring to shown in Figure 2:
The output of low-pass filter unit 201 is connected with the input of amplifying unit 202;
Direct current offset correcting unit 203 is mainly realized by integrator, is used for the output signal of amplifying unit 202 is carried out integration, and with the input of the signal feedback behind the integration to described low-pass filter unit 201.
Wherein, the effect of resistance R 5 is that the output voltage of integrator is converted to electric current because integrator constitutes negative feedback in this device, therefore, the electric current by resistance R 6 will with the current subtraction of passing through resistance R 5, thereby reduce direct current offset.
For integrator, its reaction time (being the frequency response time) is decided by the size of its time constant (timeconstant), and big more its required reaction time of time constant will be of a specified duration more, and more little its required reaction time of time constant will be short more.
As seen,, will influence the speed of DC offset correction, and then influence the W-response time of receiver system if the time constant of integrator is excessive.But in actual applications, less time constant also has higher corner frequency (corner frequency), and this may cause output signal generation distortion, thereby influences the EVM of whole system.
For addressing the above problem, can realize by the adjustable integrator of constant service time.Because time constant equals the resistance value of integrating circuit and the product of capacitance, therefore, can realize adjustment by adjusting resistance value and/or capacitance to time constant.
In the embodiment of the invention, so that being adjusted into example, resistance describes, referring to shown in Figure 2, the integrator in the direct current offset correcting unit 203 comprises a resistance selection circuit, and the input voltage of integrator selects circuit to be connected to the input of operational amplifier through resistance; This described resistance selects circuit to be made of selector switch and a plurality of resistance, is used to realize the path of at least two kinds of different resistances.
In actual applications, amplifying unit 202 often adopts variable gain amplifier to realize, in this case, corresponding to the every kind of yield value that is provided of variable gain amplifier, resistance selects circuit to provide the path of two kinds of different resistances respectively.
Describe with situation shown in Figure 3, the variable gain amplifier in the amplifying unit 202 provides two kinds of yield values, realizes by diverter switch 3a and 4a.And corresponding to these two kinds of yield values, resistance selects circuit to provide the path of two kinds of different resistances respectively.Switch 3a among Fig. 3 and 3b, 4a and 4b link respectively, after yield value is determined, use switch 1 and 2 to switch the path of two kinds of different resistances:
When switch 3a/3b closure, when switch 4a/4b opens:
Switch 1 closure, switch 2 is opened, and this moment, the path resistance was R1;
Switch 2 closures, switch 1 is opened, and this moment, the path resistance was R1+R2+R3;
When switch 3a/3b opens, when switch 4a/4b is closed:
Switch 1 closure, switch 2 is opened, and this moment, the path resistance was R1+R2;
Switch 2 closures, switch 1 is opened, and this moment, the path resistance was R1+R2+R3+R4.
For convenience of description, below hypothesis amplifier fixed gain earlier, suppose that promptly switch 3 is closed always.When switch 1 and switch 3 closures, when switch 2 and switch 4 were opened, the resistance that integrator is used was R1, claim that the state of this moment is a state 1, and when switch 2 and switch 3 closures, when switch 1 and switch 4 were opened, integrating resistor was R1+R2+R3, and the state of this moment is a state 2.Obviously under the constant situation of electric capacity, the time constant of state 2 is bigger than the time constant of state 1, thus title state 2 be large time constant pattern, title state 1 be hour between the constant pattern, 2 response times of state are greater than the response time of state 1.
The corresponding above-mentioned DC drift correction apparatus that provides, the embodiment of the invention also provides a kind of DC offset correction method, and referring to shown in Figure 3, this method may further comprise the steps:
S301, when the entering signal receiving mode, constant pattern between integrator is adjusted to hour;
S302 when direct current offset satisfies the reception demand, is adjusted to the large time constant pattern with integrator.
When receiver enters receiving mode, behind the low-pass filter unit input mixed frequency signal, with switch 2 open, switch 1 closure, this moment integrator be in hour between the constant pattern, have the reaction time faster.But,, therefore,, in the time of can satisfying system's reception demand, switch 2 closures, switch 1 are opened when direct current is corrected to smaller value because less time constant also has higher corner frequency.This moment, integrator was in the large time constant pattern, had lower corner frequency, thus can reduce distorted signals, and then alleviate influence to receiving system EVM.
In the application process of reality, the another one problem that may exist is: direct current offset is amplified by variable gain amplifier step by step through behind the low pass filter, and promptly variable gain amplifier has also amplified direct current offset in amplifying signal.The gain of variable gain amplifier generally all will be accomplished 60dB-70dB, and the direct current offset of several microvolts of frequency mixer output can be amplified to saturated, thereby has blocked useful signal.So DC offset correction circuit needs the compensate for variable gain amplifier to amplify the variation of direct current offset that the back causes.
If if the gain of variable gain amplifier is very high in circuit, may not guarantee direct current to be corrected to the value of expectation at the transmitting-receiving time slot by a loop, in a preferred embodiment of the invention, can adopt two DC offset correction loops to come correcting DC offset, as shown in Figure 4, the output of the first DC offset correction loop 401 is connected with the input of the second DC offset correction loop 402.
But, the problem of using two cor-rection loop to run into is: when two integration loops switch to low high pass corner frequency by high low pass corner frequency simultaneously, system may produce unsettled phenomenon, especially under filter Q value condition with higher.
Therefore, the work that need cooperatively interact of two loops, system is stable when guaranteeing that circuit switches.Referring to shown in Figure 5, the corresponding above-mentioned receiver that provides, DC offset correction method provided by the present invention may further comprise the steps:
S501, when the entering signal receiving mode, constant pattern between the integrator of the first DC offset correction loop and the second DC offset correction loop is adjusted to hour simultaneously.
S502, when direct current offset satisfies the reception demand, the integrator of the first DC offset correction loop is adjusted to the large time constant pattern, through after a while, after treating the first DC offset correction loop stability, the integrator of the second DC offset correction loop is adjusted to the large time constant pattern.
When receiver enters receiving mode, behind the low-pass filter unit input mixed frequency signal, constant pattern between the integrator of the integrator of the first DC offset correction loop 401 and the second DC offset correction loop 401 switched to hour simultaneously can guarantee at short notice direct current to be corrected to desired value like this.When treating that the direct current correction can be satisfied system's reception demand, at first the integrator with first cor-rection loop switches to the large time constant pattern, wait for a period of time then (general several microseconds get final product), after treating that first cor-rection loop is stable, again the second cor-rection loop integrator is switched to the large time constant pattern, can guarantee stable realization switching like this, do not cause circuit to be shaken, can guarantee that again receiving system is operated under the low corner frequency, avoid the deterioration of the EVM of system.
In sum, technical scheme provided by the present invention, the variable integrator of constant service time is proofreaied and correct the direct current offset of direct down-conversion receiver, during the constant pattern, can guarantee at short notice direct current to be proofreaied and correct to desired value between integrator is in hour.After correction is finished, integrator is adjusted to the large time constant pattern, have lower corner frequency this moment, to avoid output signal generation distortion.
Be understandable that technical solution of the present invention is applicable to the various wireless communication systems that the response time is had higher requirements.For example, TD-SCDMA system communication standard code: the wireless receiving and dispatching each has only the time interval of 10uS-30uS every time slot (time slot), and in the transmit receive separation time slot, only allows to calibrate with the direct current offset that the very short time carries out after gain is reseted.Use technical solution of the present invention, by setting suitable time constant value, can be implemented in and carry out DC offset correction in the short time fast, and after correction is finished, by integrator being adjusted to the large time constant pattern, can continue the stable operation of the system that guarantees.
The above only is the specific embodiment of the present invention; should be pointed out that for those skilled in the art, under the prerequisite that does not break away from the principle of the invention; can also make some improvements and modifications, these improvements and modifications also should be considered as protection scope of the present invention.
Claims (7)
1. a DC drift correction apparatus is characterized in that, comprises low-pass filter unit, amplifying unit and direct current offset correcting unit,
The output of described low-pass filter unit is connected with the input of described amplifying unit;
Described direct current offset correcting unit comprises that one can provide the integrator of two kinds of time constants, and described direct current offset correcting unit is carried out integration to the output signal of described amplifying unit, and with the input of the signal feedback behind the integration to described low-pass filter unit.
2. device according to claim 1 is characterized in that, the input voltage of described integrator selects circuit to be connected to the input of operational amplifier through resistance; Described resistance selects circuit to be made of selector switch and a plurality of resistance, is used to realize the path of two kinds of different resistances;
Wherein, the corresponding large time constant pattern with described integrator of high value path, the corresponding and described integrator of low resistance path hour between the constant pattern.
3. device according to claim 1 is characterized in that, described amplifying unit is a variable gain amplifier.
4. device according to claim 3 is characterized in that, corresponding to the every kind of yield value that is provided of described variable gain amplifier, described resistance selects circuit that the path of two kinds of different resistances is provided respectively.
5. a DC offset correction method is characterized in that, uses as each described DC drift correction apparatus of claim 1-4, and this method comprises:
When described device entering signal receiving mode, constant pattern between described integrator is adjusted to hour;
When direct current offset satisfies the reception demand, described integrator is adjusted to the large time constant pattern.
6. a direct current offset correction systems is characterized in that, comprises two as each described DC drift correction apparatus of claim 1-4, and wherein, the output of first DC drift correction apparatus is connected with the input of second DC drift correction apparatus.
7. a DC offset correction method is characterized in that, uses direct current offset correction systems as claimed in claim 6, and this method comprises:
When described system entering signal receiving mode, constant pattern between the integrator of described first DC drift correction apparatus and second DC drift correction apparatus is adjusted to hour simultaneously;
When direct current offset satisfies the reception demand, the integrator of described first DC drift correction apparatus is adjusted to the large time constant pattern; After the loop stability that described DC drift correction apparatus constitutes, the integrator of described second DC drift correction apparatus is adjusted to the large time constant pattern.
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| CN 201010170213 CN101860323B (en) | 2010-05-11 | 2010-05-11 | Device, system and method for correcting direct current offset |
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| CN 201010170213 CN101860323B (en) | 2010-05-11 | 2010-05-11 | Device, system and method for correcting direct current offset |
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| CN101860323B CN101860323B (en) | 2013-09-18 |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102355438A (en) * | 2011-06-23 | 2012-02-15 | 上海中科高等研究院 | Direct quadrature up-conversion transceiver and estimation method of local oscillator leakage of transmitter thereof |
| CN103546404A (en) * | 2012-07-12 | 2014-01-29 | 创杰科技股份有限公司 | Direct conversion transceiver for compensating DC offset and operation method thereof |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20050110550A1 (en) * | 2003-11-24 | 2005-05-26 | Qian Shi | DC offset cancellation in a direct-conversion receiver |
| CN101115038A (en) * | 2006-07-13 | 2008-01-30 | 联发科技股份有限公司 | Apparatus and method for enhancing DC offset correction speed of a radio device |
| CN101179543A (en) * | 2006-11-09 | 2008-05-14 | 财团法人工业技术研究院 | DC offset cancellation circuit |
| US7403760B1 (en) * | 2003-12-31 | 2008-07-22 | Conexant Systems, Inc. | DC offset correction for direct-conversion receiver |
| CN101257466A (en) * | 2008-03-28 | 2008-09-03 | 华为技术有限公司 | Apparatus and method for performing attenuation to direct current offset of equipment output |
-
2010
- 2010-05-11 CN CN 201010170213 patent/CN101860323B/en not_active Expired - Fee Related
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20050110550A1 (en) * | 2003-11-24 | 2005-05-26 | Qian Shi | DC offset cancellation in a direct-conversion receiver |
| US7403760B1 (en) * | 2003-12-31 | 2008-07-22 | Conexant Systems, Inc. | DC offset correction for direct-conversion receiver |
| CN101115038A (en) * | 2006-07-13 | 2008-01-30 | 联发科技股份有限公司 | Apparatus and method for enhancing DC offset correction speed of a radio device |
| CN101179543A (en) * | 2006-11-09 | 2008-05-14 | 财团法人工业技术研究院 | DC offset cancellation circuit |
| CN101257466A (en) * | 2008-03-28 | 2008-09-03 | 华为技术有限公司 | Apparatus and method for performing attenuation to direct current offset of equipment output |
Non-Patent Citations (2)
| Title |
|---|
| 《IEEE Asian Solid-State Circuits Conference》 20081105 Fei Song, Huailin Liao, Jiang Chen, Le Ye, Huaizhou Yang等 A 1.8-V CMOS Direct-Conversion Tuner for Mobile DTV Applications IEEE 354,355 , 2 * |
| 《IEEE JOURNAL OF SOLID-STATE CIRCUITS》 20080331 Ickjin Kwon等 A Single-Chip CMOS Transceiver for UHF Mobile RFID Reader IEEE 731,733 第43卷, 第3期 2 * |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102355438A (en) * | 2011-06-23 | 2012-02-15 | 上海中科高等研究院 | Direct quadrature up-conversion transceiver and estimation method of local oscillator leakage of transmitter thereof |
| CN102355438B (en) * | 2011-06-23 | 2014-03-12 | 中国科学院上海高等研究院 | Direct quadrature up-conversion transceiver and estimation method of local oscillator leakage of transmitter thereof |
| CN103546404A (en) * | 2012-07-12 | 2014-01-29 | 创杰科技股份有限公司 | Direct conversion transceiver for compensating DC offset and operation method thereof |
| CN103546404B (en) * | 2012-07-12 | 2016-09-07 | 密克罗奇普技术公司 | Direct conversion transceiver for compensating DC offset and operation method thereof |
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