CN101854321B - Method for reducing power consumption of synchronous module of OFDM system - Google Patents

Abstract

The invention discloses a method for reducing the power consumption of the synchronous module of an OFDM system. The method comprises the following steps: step 101: performing swept frequency correlation operation to the sign bits of the received synchronization sequence and the local known sequence in the time domain to obtain the estimated value of integer carrier frequency offset; and step 102: performing correlation operation to the received sign bits corrected by frequency offset in the time domain to obtain the precise position of the FFT window. By using the method of the invention, the synchronous property of the system can be ensured while the working power of the synchronous module of the system can be reduced.

Description

Reduce the method for ofdm system power consumption of synchronous module

Technical field

The present invention relates to band receiver of base algorithm and very lagre scale integrated circuit (VLSIC) (VLSI) design field, relate in particular to the method for a kind of reduction OFDM (OFDM) system synchronization module dissipation.

Background technology

The matter of utmost importance that communication system faces is guarantee time point and Frequency point synchronous.In addition, because the non-ideal effects of wireless channel and analog radio frequency device, the signal and the primary signal that receive at receiving terminal have very big distorton, how to compensate these non-ideal factors the ofdm system performance is had very large influence; The more important thing is for towards the design of the baseband chip of mobile multimedia the very big challenge especially of synchronization performance and low power dissipation design.

Therefore before ofdm signal carries out demodulation, must finish two synchronous workings (Wang Yumin, OFDM key technology and application, China Machine Press, 2007.) at least earlier.At first, the border of OFDM symbol and best sampling instant be must find, intersymbol interference (ISI) and inter-carrier interference (ICI) minimum made.Moreover, must correctly estimate carrier shift, because any carrier shift all will produce ICI.

In sum, in ofdm system, formed by series of steps shown in Figure 1 synchronously, comprise time synchronized, sample-synchronous and carrier synchronization.Time synchronized is to seek the position of windowing of FFT, in practice this step often by synchronously thick and essence synchronously or more multistep finish suddenly.Sample-synchronous is in order to proofread and correct by D/A and the inconsistent deviation that causes of A/D sampling.Carrier synchronization then is for the carrier frequency offset between correct transmission machine and the receiver, according to the relation between subcarrier spacing and the frequency deviation, can be divided into integer frequency bias, decimal frequency bias and residual frequency departure and proofread and correct respectively.

China Mobile multimedia broadcasting (CMMB) standard based on ofdm system is that SARFT(The State Administration of Radio and Television) is in the industry standard of formal China's Mobile Multimedia Broadcasting (mobile TV) of promulgating on October 24th, 2006, this standard determined to adopt China's independent research Mobile Multimedia Broadcasting transmission technical standard star ground interactive many service systems framework (Satellite-Terrestrial InteractiveMulti-service Infrastructure, STiMi).In the design of CMMB system base band demodulating chip, fully take into account it towards the application of mobile handheld terminal, so synchronization performance and low power dissipation design will become difficult point and key in the baseband chip design.

Summary of the invention

(1) technical problem that will solve

In view of this, main purpose of the present invention is to provide a kind of method that reduces the ofdm system power consumption of synchronous module, with in the safeguards system net synchronization capability, reduces the work power consumption of system synchronization module.

(2) technical scheme

For achieving the above object, the invention provides a kind of method that reduces the ofdm system power consumption of synchronous module, this method comprises:

Step 101: on time-domain, the sign bit of the synchronizing sequence that receives and the sign bit of local known array are carried out the frequency sweep related operation, obtain the estimated value of integer frequency offset;

Step 102: on the time-domain sign bit of the synchronizing sequence behind the correcting frequency deviation that receives and the sign bit of local known array being carried out related operation, obtain the exact position that FFT windows.

In the such scheme, described step 101 comprises:

The sign bit of the synchronizing sequence that A1, calculating receive;

The sign bit of A2, the local known array of calculating;

A3, the sign bit of the synchronizing sequence that receives and the sign bit of local known array are carried out the frequency sweep related operation.

In the such scheme, described steps A 1 comprises:

Suppose that ofdm system slightly finishes synchronously, and finish the fractional part of frequency offset compensation that find transmitting terminal to send the approximate location of known array, at this moment, the sign bit of the synchronizing sequence of reception can be expressed as:

$r^{\&prime;}\left(k\right)=z\left(k\right)e^{-\mathrm{<figure-callout\; id="2"\; label="j"\; filenames="H200910081096801E00022.png,H200910081096801E00023.png"\; state="\{\{state\}\}">j</figure-callout>}2\mathrm{\&pi;}{\mathrm{\&Delta;f}}_{\mathrm{int}}{f}_{\mathrm{carrier}}{\mathrm{kT}}_s}$

Wherein, z (k) expression transmitting terminal sends signal; Δ f _IntBe the integer frequency deviator, be positive negative integer; f _CarrierBe ofdm system intercarrier distance; T _sBe the ofdm system sampling period.

In the such scheme, described steps A 2 comprises:

Suppose that ofdm system comprises local known array c (k), then the frequency sweep sequence can be expressed as:

$b\left(i\right)=c\left(k\right)e^{-\mathrm{<figure-callout\; id="2"\; label="j"\; filenames="H200910081096801E00022.png,H200910081096801E00023.png"\; state="\{\{state\}\}">j</figure-callout>}2\mathrm{\&pi;}{f}_{\mathrm{carrier}}{\mathrm{kT}}_{s}i}$

In the present invention, c (k) gets sign bit, and following formula can be expressed as:

$b\left(i\right)=\mathrm{sign}\left(c\left(k\right)\right)e^{-\mathrm{<figure-callout\; id="2"\; label="j"\; filenames="H200910081096801E00022.png,H200910081096801E00023.png"\; state="\{\{state\}\}">j</figure-callout>}2\mathrm{\&pi;}{f}_{\mathrm{carrier}}{\mathrm{kT}}_{s}i}$

Wherein sign () can be expressed as

$\mathrm{real}\_r=\left\{\begin{array}{cc}1& \mathrm{real}\left(r\right)>0\\ 0& \mathrm{real}\left(r\right)<0\end{array}\right.$

$\mathrm{imag}\_r=\left\{\begin{array}{cc}1& \mathrm{imag}\left(r\right)>0\\ 0& \mathrm{imag}\left(r\right)<0\end{array}\right..$

sign(r)＝real_r+j□imag_r

In the such scheme, described steps A 3 comprises:

Utilization receives the sign bit of data, and can get according to maximum likelihood principle:

$M\left(i\right)=\arg \underset{i}{\max }\underset{k=0}{\overset{L-1}{\mathrm{\&Sigma;}}}{\left|\mathrm{sign}\left(r^{\&prime;}\left(k\right)\right)\mathrm{conj}\left(b\left(i\right)\right)\right|}^2---\left(5\right)$

I ∈ [k wherein _Max, k _Max], k _MaxBe the patient maximum integer frequency deviation value of system, make formula (5) at [k like this _Max, k _Max] to reach peaked i in the scope be exactly integer frequency bias.

In the such scheme, among described steps A 2～A3 the signal of the known synchronizing sequence in this locality and reception is got sign bit and carry out the frequency sweep related operation, needed hardware comprises:

2048 * 2 RAM are used for storing real part and the imaginary part of the synchronizing signal of receiving, wherein each 1 bit wide of I, Q and being stored in the same address in hardware designs;

2048 * 2 ROM are used for storing known synchronizing sequence real part and imaginary part, wherein each 1 bit wide of I, Q and being stored in the same address in hardware designs;

Value adopts the mode of look-up table in this modular design, store with ROM

M=-k _Max..k _Max, because

Value smaller, so need more bit wide to store, real part and imaginary part are represented with 22bit respectively, k in the design _Max=30, therefore need DROM64 * 44; And

Two 1 * 1 multiplier and two s' 22 * 22 multiplier calculates real part and imaginary part respectively.

In the such scheme, described step 102 comprises:

B1, finish synchronously smart by the relevant algorithm of sliding window;

B2, passing threshold judgement in the relevant result of sliding window, the exact position of finding FFT to window;

B3, utilize the sign bit computing to finish sliding window related operation.

In the such scheme, described step B1 comprises: smart synchronous algorithm will be by seeking first directly the position of multipath, the exact position of finding FFT to window, this algorithm are that finish data behind the compensate of frequency deviation and the local known array that utilize to receive carry out matched filtering and finish; Algorithm is seen formula (9):

$\mathrm{Corr}\left(n\right)=\underset{k=0}{\overset{L-1}{\mathrm{\&Sigma;}}}r(k+n)\&CenterDot;\mathrm{conj}\left(c\left(k\right)\right),n=-l,...l---\left(9\right)$

L is the length that transmitting terminal sends known array in the formula, and r is the signal after the compensating through carrier wave frequency deviation of receiving, and c (k) is local known signal, and l is the hunting zone; Through type (9) passing threshold in the hunting zone judges that the n value that finds is thick synchronous deviate.

In the such scheme, described step B2 comprises: the hunting zone is decided to be [l, l], the window front and back l subcarrier of position of the thick FFT that determines synchronously of i.e. search, what all were tried to achieve in this scope adding up and being averaging, draw mean value mean after, judge as threshold value with α * mean, α obtains by ofdm system emulation, the exact position that can find FFT to window.

In the such scheme, on the time-domain sign bit of the synchronizing sequence behind the correcting frequency deviation that receives and the sign bit of local known array being carried out related operation, obtain the exact position that FFT windows among described step B1～B3, needed hardware comprises:

2272 * 2 RAM, after being used for finishing little several times and integer frequency offset compensation, to use real part and the imaginary part of 2248 * 26 data in thick front and back, the synchronizing sequence positions 100 subcarrier scopes of estimating synchronously of storage, I, each 1 bit wide of Q symbolization position in hardware designs, this sequence is the computing of window and local known array perfect (10) with 2048 after the storage;

224 * 24 RAM are used for the value of 201 Corr (n) after memory-type (10) computing, average and judge smart sync bit being used for, and correlated results is represented with 24 bit wides in hardware designs;

A ROM, DROM2048 * 2 are used for storing the sign bit of local known synchronizing sequence, each 1 bit wide of local known synchronizing sequence I, Q in the hardware designs; And

Two 1 * 1 multiplier is used for finishing complex multiplication operation.

In the such scheme, the hardware that described step 101 and step 102 need jointly comprises:

One of 2272 * 2 single port RAM;

One of 2048 * 2 single port ROM;

One of 64 * 44 single port ROM;

One of 224 * 24 single port RAM;

Two of 1 * 1 multipliers; And

Two of 22 * 22 multipliers.

(3) beneficial effect

From technique scheme as can be seen, the present invention has following beneficial effect:

1, the method for this reduction ofdm system power consumption of synchronous module provided by the invention, when not reducing the system synchronization performance, significantly reduced the bit wide of memory and multiplier in the related operation, thereby reduced the power consumption of system synchronization, be highly suitable for the design of hand-held mobile terminal device chip.

2, the method for this reduction ofdm system power consumption of synchronous module provided by the invention is applied to can effectively reduce the power consumption of synchronous module of this system's base band demodulator in China Mobile multimedia broadcasting (CMMB) system.

3, the method for this reduction ofdm system power consumption of synchronous module provided by the invention, the method for sign bit computing also is applicable to the low power dissipation design of other each key modules of OFDM band receiver of base.

Description of drawings

The present invention is further described below in conjunction with drawings and Examples:

Fig. 1 is the inter-sync schematic diagram of ofdm system;

Fig. 2 is the method realization flow figure of reduction ofdm system power consumption of synchronous module provided by the invention;

Fig. 3 is that the CMMB system estimates analogous diagram based on the integer frequency offset of synchronizing sequence frequency sweep among the embodiment provided by the invention; This figure is the exemplary dynamic multipath, 5dB white Gaussian noise, 40ppm carrier wave frequency deviation, 100Hz Doppler frequency deviation;

Fig. 4 is the pie graph of CMMB system beacon among the embodiment provided by the invention;

Fig. 5 is that integer frequency offset is estimated hardware block diagram among the embodiment provided by the invention;

Fig. 6 is the hardware block diagram that essence provided by the invention is used the computing of matched filter sign bit synchronously;

Fig. 7 is the smart synchronization simulation figure of CMMB system among the embodiment provided by the invention; This figure is the exemplary dynamic multipath, 10dB white Gaussian noise, thick 2 subcarriers of synchronism deviation.

Embodiment

For making the purpose, technical solutions and advantages of the present invention clearer, below in conjunction with specific embodiment, and with reference to accompanying drawing, the present invention is described in more detail.

The method of reduction ofdm system power consumption of synchronous module provided by the invention, be based on that the synchronization module low power consumption design method of China Mobile multimedia broadcasting (CMMB) system and emulation proposes, by to the emulation of sign bit related operation on the time-domain with to the extraction of formula (8) related operation common factor, can optimize the circuit design of synchronization module, reduce the bit wide of memory and multiplier in the computing, thereby effectively reduce the power consumption of system synchronization module.

As shown in Figure 2, Fig. 2 is the method realization flow figure of reduction ofdm system power consumption of synchronous module provided by the invention, and this method comprises:

Step 101: on time-domain, the sign bit of the synchronizing sequence that receives and the sign bit of local known array are carried out the frequency sweep related operation, obtain the estimated value of integer frequency offset;

Step 102: on the time-domain sign bit of the synchronizing sequence behind the correcting frequency deviation that receives and the sign bit of local known array being carried out related operation, obtain the exact position that FFT windows.

Above-mentioned steps 101 specifically comprises:

The sign bit of the synchronizing sequence that A1, calculating receive.Suppose that ofdm system slightly finishes synchronously, and finish the fractional part of frequency offset compensation that find transmitting terminal to send the approximate location of known array, at this moment, the sign bit of the synchronizing sequence of reception can be expressed as:

$r^{\&prime;}\left(k\right)=z\left(k\right)e^{-\mathrm{<figure-callout\; id="2"\; label="j"\; filenames="H200910081096801E00022.png,H200910081096801E00023.png"\; state="\{\{state\}\}">j</figure-callout>}2\mathrm{\&pi;\&Delta;}{f}_{\mathrm{int}}{f}_{\mathrm{carrier}}{\mathrm{kT}}_s}---\left(1\right)$

Wherein, z (k) expression transmitting terminal sends signal; Δ f _IntBe the integer frequency deviator, be positive negative integer; f _CarrierBe ofdm system intercarrier distance; T _sBe the ofdm system sampling period.

The sign bit of A2, the local known array of calculating.Suppose that ofdm system comprises local known array c (k), then the frequency sweep sequence can be expressed as:

$b\left(i\right)=c\left(k\right)e^{-\mathrm{<figure-callout\; id="2"\; label="j"\; filenames="H200910081096801E00022.png,H200910081096801E00023.png"\; state="\{\{state\}\}">j</figure-callout>}2\mathrm{\&pi;}{f}_{\mathrm{carrier}}{\mathrm{kT}}_{s}i}---\left(2\right)$

In the present invention, c (k) gets sign bit, and following formula can be expressed as:

$b\left(i\right)=\mathrm{sign}\left(c\left(k\right)\right)e^{-\mathrm{<figure-callout\; id="2"\; label="j"\; filenames="H200910081096801E00022.png,H200910081096801E00023.png"\; state="\{\{state\}\}">j</figure-callout>}2\mathrm{\&pi;}{f}_{\mathrm{carrier}}{\mathrm{kT}}_{s}i}---\left(3\right)$

Wherein sign () can be expressed as

$\mathrm{real}\_r=\left\{\begin{array}{cc}1& \mathrm{real}\left(r\right)>0\\ 0& \mathrm{real}\left(r\right)<0\end{array}\right.$

$\mathrm{imag}\_r=\left\{\begin{array}{cc}1& \mathrm{imag}\left(r\right)>0\\ 0& \mathrm{imag}\left(r\right)<0\end{array}\right.---\left(4\right)$

sign(r)＝real_r+j□imag_r

A3, the sign bit of the synchronizing sequence that receives and the sign bit of local known array are carried out the frequency sweep related operation.Utilization receives the sign bit of data, and can get according to maximum likelihood principle:

$M\left(i\right)=\arg \underset{i}{\max }\underset{k=0}{\overset{L-1}{\mathrm{\&Sigma;}}}{\left|\mathrm{sign}\left(r^{\&prime;}\left(k\right)\right)\mathrm{conj}\left(b\left(i\right)\right)\right|}^2---\left(5\right)$

I ∈ [k wherein _Max, k _Max], k _MaxBe the patient maximum integer frequency deviation value of system.

Like this, make formula (5) at [k _Max, k _Max] to reach peaked i in the scope be exactly integer frequency bias.

The integer frequency offset of CMMB system estimates just to be based on the integer frequency deviation estimation algorithm of synchronizing sequence frequency sweep, and this algorithm is at k _Max=100 o'clock simulation result is seen shown in Figure 3, can be clear that in frequency deviation be under the 40ppm, after finishing fractional part of frequency offset estimation and compensation, carries out the integer frequency deviation estimation algorithm of synchronizing sequence frequency sweep, and there is obvious peak value at the place at subcarrier-43.

A4, based on the specific design of CMMB band receiver of base, the hardware of this method is realized.

The algorithm that steps A 1-A3 of the present invention introduces is applied in the design of CMMB system.The beginning of each time slot of CMMB system comprises a beacon, and beacon is made up of structure shown in Figure 4.

Two synchronizing signals are that identical length is 2048 sequence.Integer frequency offset is estimated to finish the main application of synchronized sequence of its algorithm in time domain in the CMMB system:

${\mathrm{sync}}_{I,m}\left(k\right)=\mathrm{sync}\left(k\right)\&CenterDot;e^{-\mathrm{<figure-callout\; id="2"\; label="j"\; filenames="H200910081096801E00022.png,H200910081096801E00023.png"\; state="\{\{state\}\}">j</figure-callout>}2\mathrm{\&pi;m}{f}_{\mathrm{carrier}}k},$ k＝0，1，...，2047，m＝-k _max，..k _max (6)

k _MaxBe the integer frequency offset swept frequency range, sync (k) is synchronizing sequence;

$\mathrm{Corr}\left(m\right)=\underset{k=0}{\overset{2047}{\mathrm{\&Sigma;}}}{r}_I\left(k\right)\&CenterDot;\mathrm{conj}\left({\mathrm{sync}}_{I,m}\left(k\right)\right)---\left(7\right)$

But in actual hardware designs, need to calculate

Two variable m and k are arranged in this formula, and this will bring very big design complexities to hardware designs, and especially k changes in 0-2048, so whenever finishes the calculating of a m, need to calculate Totally 2048 times, need expend a large amount of power consumptions and time, when the present invention designs this hardware module, computing formula is opened, suppose that at first m fixes:

$\mathrm{Corr}\left(m\right)=\underset{k=0}{\overset{2047}{\mathrm{\&Sigma;}}}{r}_I\left(k\right)\&CenterDot;\mathrm{conj}\left({\mathrm{sync}}_{I,m}\left(k\right)\right)=$

$=\underset{k=0}{\overset{2047}{\mathrm{\&Sigma;}}}{r}_I\left(k\right)\&CenterDot;{\mathrm{sync}}^{*}\left(k\right)\&CenterDot;{\mathrm{<figure-callout\; id="2"\; label="e\; j"\; filenames="H200910081096801E00022.png,H200910081096801E00023.png"\; state="\{\{state\}\}">e</figure-callout>}}^j$

$=r_I\left(0\right)\&CenterDot;{\mathrm{sync}}^{*}\left(0\right)\&CenterDot;1+r_I\left(1\right)\&CenterDot;{\mathrm{sync}}^{*}\left(1\right)\&CenterDot;{\mathrm{<figure-callout\; id="2"\; label="e\; j"\; filenames="H200910081096801E00022.png,H200910081096801E00023.png"\; state="\{\{state\}\}">e</figure-callout>}}^j+...$

$=r_I\left(0\right)\&CenterDot;{\mathrm{sync}}^{*}\left(0\right)\&CenterDot;1+{\mathrm{<figure-callout\; id="2"\; label="e\; j"\; filenames="H200910081096801E00022.png,H200910081096801E00023.png"\; state="\{\{state\}\}">e</figure-callout>}}^j\&CenterDot;[r_I\left(1\right)\&CenterDot;{\mathrm{sync}}^{*}\left(1\right)+{\mathrm{<figure-callout\; id="2"\; label="e\; j"\; filenames="H200910081096801E00022.png,H200910081096801E00023.png"\; state="\{\{state\}\}">e</figure-callout>}}^j\&CenterDot;[r_I\left(2\right)\&CenterDot;{\mathrm{sync}}^{*}\left(2\right)+...$

Can find that like this index unique in the formula is

And no longer changed along with the variation of k, so just can use the method for look-up table to calculate

The core concept of this modular design that Here it is.

According to the method for steps A 2-A3, the signal of local known synchronizing sequence and reception is got sign bit and is participated in computing, can draw needed hardware like this from formula:

1. 2048 * 2 RAM are used for storing the real part of the synchronizing signal of receiving and imaginary part (in hardware designs each 1 bit wide of I, Q and be stored in the same address);

2. 2048 * 2 ROM are used for storing known synchronizing sequence real part and imaginary part (in hardware designs each 1 bit wide of I, Q and be stored in the same address);

3. Value adopts the mode of look-up table in this modular design, store with ROM M=-k _Max..k _Max, because

Value smaller, so need more bit wide to store, real part and imaginary part are represented with 22bit respectively, k in this modular design _MaxTherefore=30, needing DROM64 * 44, (ROM address, integrated circuit technology storehouse can only be 2 ⁿ, this DROM can extension storage to-32～32 swept frequency ranges);

4. also need the expense multiplier in addition: two 1 * 1 multiplier and two s' 22 * 22 multiplier calculates real part and imaginary part respectively;

Hardware configuration as shown in Figure 5.

In hardware designs shown in Figure 5, insert two registers, carry out two-stage pipeline structure, i.e. 1 * 1 complex multiplier and 22 * 22 complex multiplier flowing water computings, thus accelerate the speed of integer frequency offset estimation and reduce the hardware power consumption;

Above-mentioned steps 102 specifically comprises:

B1, finish synchronously smart by the relevant algorithm of sliding window.The system that finished thick synchronously after, find the approximate location that the FFT data begin after, need carry out the smart synchronized algorithm of symbol, with the exact position of finding FFT to window.

Smart synchronous algorithm will be by seeking first directly the position of multipath, the exact position of finding FFT to window.This algorithm is that finish data behind the compensate of frequency deviation and the local known array that utilize to receive carry out matched filtering and finish.

Algorithm is seen formula (9):

$\mathrm{Corr}\left(n\right)=\underset{k=0}{\overset{L-1}{\mathrm{\&Sigma;}}}r(k+n)\&CenterDot;\mathrm{conj}\left(c\left(k\right)\right),n=-l,...l---\left(9\right)$

L is the length that transmitting terminal sends known array in the formula, and r is the signal after the compensating through carrier wave frequency deviation of receiving, and c (k) is local known signal, and l is the hunting zone.

Through type (9) passing threshold in the hunting zone judges that the n value that finds is thick synchronous deviate.

B2, passing threshold judgement in the relevant result of sliding window, the exact position of finding FFT to window.When algorithm of the present invention and hardware are realized the hunting zone is decided to be [l, l], the window front and back l subcarrier of position of the thick FFT that determines synchronously of i.e. search, what all were tried to achieve in this scope adding up and being averaging, after drawing mean value mean, judge the exact position that (α obtains by ofdm system emulation) can find FFT to window with α * mean as threshold value.

B3, utilize the sign bit computing to finish sliding window related operation.Step B1 Chinese style of the present invention (9) can be carried out computing in the symbolization position, and the matched filter hardware configuration as shown in Figure 6.

Algorithm is seen formula (10):

$\mathrm{Corr}\left(n\right)=\underset{k=0}{\overset{L-1}{\mathrm{\&Sigma;}}}\mathrm{sign}\left(r(k+n)\right)\&CenterDot;\mathrm{conj}\left(\mathrm{sign}\left(c\left(k\right)\right)\right),n=-l,...l---\left(10\right)$

B4, in the practical application of CMMB base band demodulating chip synchronization module.The algorithm that step B1-B3 of the present invention introduces is applied in the design of CMMB system.Local known array among Fig. 6 still adopts the synchronizing sequence in Fig. 4 beacon.If l=100, site error is 2 after supposing slightly to finish synchronously, and namely sync bit is offset two subcarriers of physical location, and simulated environment is the exemplary dynamic multipath channel, utilizes the matched filtering algorithm can obtain peak value shown in Figure 7.

From Fig. 7, can clearly be seen that the relation of position between multipath, when this paper algorithm and hardware are realized the hunting zone is decided to be [100,100], window 100 subcarriers in front and back (l=100) of position of the thick FFT that determines synchronously of i.e. search, what all were tried to achieve in this scope adding up and being averaging, draw mean value mean after, judge as threshold value with 64 * mean, can find out multipath first footpath is the peak value at 2 places, position, thus the exact position of finding FFT to window.

On hardware designs, because this module and integer frequency deviation estimation algorithm all need to carry out related calculation with local known array, so in hardware designs, can share a hardware module, two block RAMs are arranged in this module:

1. 2272 * 2 RAM:

After finishing little several times and integer frequency offset compensation, to use real part and the imaginary part (I, each 1 bit wide of Q symbolization position in hardware designs) of 2248 * 26 data in thick front and back, the synchronizing sequence positions 100 subcarrier scopes of estimating synchronously of storage, this sequence is the computing of window and local known array perfect (10) with 2048 after the storage.

2. 224 * 24 RAM:

This RAM is used for the value of 201 Corr (n) after memory-type (10) computing, averages and judges smart sync bit (correlated results is represented with 24 bit wides in hardware designs) being used for.

Also have a ROM in addition in the module, DROM2048 * 2 are used for storing the sign bit (each 1 bit wide of local known synchronizing sequence I, Q in the hardware designs) of local known synchronizing sequence; Also need two 1 * 1 multiplier to finish complex multiplication operation.

In addition, step 101 and step 102 comprise the main hardware expense altogether:

One of 2272 * 2 single port RAM; One of 2048 * 2 single port ROM; One of 64 * 44 single port ROM; One of 224 * 24 single port RAM; Two of 1 * 1 multipliers; Two of 22 * 22 multipliers.

It is comprehensive that Design Compiler is carried out in employing 0.13 μ m SMIC storehouse after the RTL design of intact back, and work clock is 80MHz, and synthesis result is as shown in table 1.The sign bit computing will reduce about half than the power consumption of traditional bit wide computing (receiving data, each 13 bit wide of local known array I, Q).

RASP2272X2M16	0.9460mW
		DROM64X44M8	3.631e-5mW
DROM2048X2M8	0.7514mW

Multss_short (multiplier, number: 2, figure place: 1 * 1)	5.689e-03×2＝1.1378e-02mW
		Multss (multiplier, number: 2, figure place: 22 * 22)	0.0752×2＝0.1504mW
RASP224X24M16	4.169e-4mW
		Cell internal power	3.2054mW
Net switching power	23.3920uW

Table 1 sign bit computing DC synthesis result

In addition, step 101 also comprises: the compensate of frequency deviation circuit, this circuit is mainly finished by cordic algorithm, finishes in CMMB system design adopted 15 stage pipeline structure.

The method of the described reduction ofdm system power consumption of synchronous module based on the CMMB system of step 101 and step 102 in addition, the bit wide size of the memory in the described hardware designs and multiplier can change (address size and data I, Q represent bit wide) according to side circuit design and integrated circuit technology storehouse.

Above-described specific embodiment; purpose of the present invention, technical scheme and beneficial effect are further described; institute is understood that; the above only is specific embodiments of the invention; be not limited to the present invention; within the spirit and principles in the present invention all, any modification of making, be equal to replacement, improvement etc., all should be included within protection scope of the present invention.

Claims (7)

1. a method that reduces the ofdm system power consumption of synchronous module is characterized in that, this method comprises:

Step 101: on time-domain, the sign bit of the synchronizing sequence that receives and the sign bit of local known array are carried out the frequency sweep related operation, obtain the estimated value of integer frequency offset;

Step 102: on the time-domain sign bit of the synchronizing sequence behind the correcting frequency deviation that receives and the sign bit of local known array being carried out related operation, obtain the exact position that FFT windows;

It is characterized in that described step 101 comprises:

The sign bit of the synchronizing sequence that steps A 1, calculating receive comprises:

Suppose that ofdm system slightly finishes synchronously, and finish the fractional part of frequency offset compensation that find transmitting terminal to send the approximate location of known array, at this moment, the sign bit of the synchronizing sequence of reception can be expressed as:

$r^{\&prime;}\left(k\right)=z\left(k\right)e^{-j2\mathrm{\&pi;\&Delta;}{f}_{\mathrm{int}}{f}_{\mathrm{carrier}}k{T}_s}$

Wherein, r ' is the sign bit of the synchronizing sequence of reception (k), and k is the integer frequency offset swept frequency range, and k0,1 ..., 2047, z (k) expression transmitting terminal sends signal; Δ f _IntBe the integer frequency deviator, be positive negative integer; f _CarrierBe ofdm system intercarrier distance; T _sBe the ofdm system sampling period;

The sign bit of steps A 2, the local known array of calculating comprises:

Suppose that ofdm system comprises local known array c (k), then the frequency sweep sequence can be expressed as:

$b\left(i\right)=c\left(k\right)e^{-j2\mathrm{\&pi;}{f}_{\mathrm{carrier}}k{T}_{s}i}$

In the present invention, c (k) gets sign bit, and following formula can be expressed as:

$b\left(i\right)=\mathrm{sign}\left(c\left(k\right)\right)e^{-j2\mathrm{\&pi;}{f}_{\mathrm{carrier}}k{T}_{s}i}$

Wherein sign () can be expressed as

$\mathrm{real}\_r=\left\{\begin{array}{cc}1& \mathrm{real}\left(r\right)>0\\ 0& \mathrm{real}\left(r\right)<0\end{array}\right.$

$\mathrm{imag}\_r=\left\{\begin{array}{cc}1& \mathrm{imag}\left(r\right)>0\\ 0& \mathrm{imag}\left(r\right)<0\end{array}\right.;$

sign(r)＝real_r+j·imag_r

Steps A 3, the sign bit of the synchronizing sequence that receives and the sign bit of local known array are carried out the frequency sweep related operation, comprising:

Utilization receives the sign bit of data, and can get according to maximum likelihood principle:

$M\left(i\right)=\arg \underset{i}{\max }\underset{k=0}{\overset{L-1}{\mathrm{\&Sigma;}}}{\left|\mathrm{sign}\left(r^{\&prime;}\left(k\right)\right)\mathrm{conj}\left(b\left(i\right)\right)\right|}^2---\left(5\right)$

I ∈ [k wherein _Max, k _Max], k _MaxBe the patient maximum integer frequency deviation value of system, make formula (5) at [k like this _Max, k _Max] reaching the estimated value that peaked i is exactly integer frequency offset in the scope, j is the complex representation method; B (i) is the frequency sweep sequence; M (i) is the correlation maximum in the i span; The synchronizing sequence length of L for receiving.

2. the method for reduction ofdm system power consumption of synchronous module according to claim 1 is characterized in that, among described steps A 2～A3 the synchronizing sequence of the known synchronizing sequence in this locality and reception is got sign bit and carries out the frequency sweep related operation, and needed hardware comprises:

2048 * 2 RAM are used for storing real part and the imaginary part of the synchronizing sequence of reception, wherein each 1 bit wide of I, Q and being stored in the same address in hardware designs;

2048 * 2 ROM, the real part and the imaginary part that are used for storing known synchronizing sequence, wherein each 1 bit wide of I, Q and being stored in the same address in hardware designs;

Value adopts the mode of look-up table in this modular design, store with ROM

M=-k _Max..k _Max, because

Value smaller, so need more bit wide to store, real part and imaginary part are represented with 22bit respectively, k in the design _Max=30, therefore need DROM64 * 44; And

Two 1 * 1 multiplier and two s' 22 * 22 multiplier calculates real part and imaginary part respectively.

3. the method for reduction ofdm system power consumption of synchronous module according to claim 1 is characterized in that, described step 102 comprises:

Step B1, finish synchronously smart by the relevant algorithm of sliding window;

Step B2, passing threshold judgement in the relevant result of sliding window, the exact position of finding FFT to window;

Step B3, utilize the sign bit computing to finish sliding window related operation.

4. the method for reduction ofdm system power consumption of synchronous module according to claim 3 is characterized in that, described step B1 comprises:

Smart synchronous algorithm is the position in first footpath by seeking multipath, the exact position of finding FFT to window, and this algorithm is to utilize finish data behind the compensate of frequency deviation and the local known array of reception to carry out matched filtering and finish; Algorithm is seen formula (9):

$\mathrm{Corr}\left(n\right)=\underset{k=0}{\overset{L-1}{\mathrm{\&Sigma;}}}r(k+n)\&CenterDot;\mathrm{conj}\left(c\left(k\right)\right),n=-l,...l---\left(9\right)$

L is the length that transmitting terminal sends known array in the formula, and r is the signal after the compensating through carrier wave frequency deviation of receiving, and c (k) is local known signal, and l is the hunting zone; Through type (9) passing threshold in the hunting zone judges that the n value find is thick synchronous deviate, and corr (n) is for utilizing data and the local known array matched filtering calculated value behind the compensate of frequency deviation finished of reception.

5. the method for reduction ofdm system power consumption of synchronous module according to claim 3 is characterized in that, described step B2 comprises:

The hunting zone is decided to be [l, l] i.e. the window front and back l subcarrier of position of the thick FFT that determines synchronously of search, what all were tried to achieve in this scope adding up and being averaging, after drawing mean value mean, judge the exact position that to find FFT to window as threshold value with α * mean; Wherein α obtains by ofdm system emulation.

6. the method for reduction ofdm system power consumption of synchronous module according to claim 3, it is characterized in that, on the time-domain sign bit of the synchronizing sequence behind the correcting frequency deviation that receives and the sign bit of local known array are being carried out related operation among described step B1～B3, obtain the exact position that FFT windows, needed hardware comprises:

2272 * 2 RAM, after being used for finishing little several times and integer frequency offset compensation, to use real part and the imaginary part of 2248 * 26 data in thick front and back, the synchronizing sequence positions 100 subcarrier scopes of estimating synchronously of storage, I, each 1 bit wide of Q symbolization position in hardware designs, this sequence is the computing of window and local known array perfect (10) with 2048 after the storage; Wherein, formula (10) is $\mathrm{Corr}\left(n\right)=\underset{k=0}{\overset{L-1}{\mathrm{\&Sigma;}}}\mathrm{sign}\left(r(k+n)\right)\&CenterDot;\mathrm{conj}\left(\mathrm{sign}\left(c\left(k\right)\right)\right),n=-l,...l,$ Wherein L is the length that transmitting terminal sends known array, r is the signal after the compensating through carrier wave frequency deviation of receiving, c (k) is local known signal, and l is the hunting zone, finish data and the local known array matched filtering calculated value compensate of frequency deviation after of corr (n) for utilize receiving;

224 * 24 RAM are used for the value of 201 Corr (n) after memory-type (10) computing, average and judge smart sync bit being used for, and correlated results is represented with 24 bit wides in hardware designs;

A ROM, DROM2048 * 2 are used for storing the sign bit of local known synchronizing sequence, each 1 bit wide of local known synchronizing sequence I, Q in the hardware designs; And

Two 1 * 1 multiplier is used for finishing complex multiplication operation.

7. according to the method for claim 2 or 6 described reduction ofdm system power consumption of synchronous module, it is characterized in that the hardware that described step 101 and step 102 need jointly comprises:

One of 2272 * 2 single port RAM;

One of 2048 * 2 single port ROM;

One of 64 * 44 single port ROM;

One of 224 * 24 single port RAM;

Two of 1 * 1 multipliers; And

Two of 22 * 22 multipliers.

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