CN101854156A - Clock generator, clock generation method and mobile communication device - Google Patents
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Abstract
The invention provides a clock generator, a clock generation method and a mobile communication device, adopting a clock generation technology. The clock generator comprises an accumulator, an oscillation signal generating circuit and a frequency correction circuit. The oscillation signal generating circuit generates an oscillation signal and adjusts the frequency of the oscillation signal according to a overflow output signal of the accumulator, and the frequency correction circuit generates a frequency control value according to the oscillation signal and a reference oscillation signal. The accumulator takes the oscillation signal as a control signal to accumulate the frequency control value and generate the overflow output signal.
Description
Technical field
The invention relates to a kind of clock generator; Be particularly in the mobile device, be used for the clock generator under the low power consuming pattern.
Background technology
Employed clock signal needs very high accuracy usually in field of mobile communication, can guarantee that just communication is normal.Quartz (controlled) oscillator is a kind of common clock generator.
Usually the oscillator signal that needs at least two kinds of frequencies in the device for mobile communication: one does communication uses, and one is used for reaching the time clock feature in the device for mobile communication.With code division multiple access (Code Division Multip1eAccess, CDMA) communication is an example, the used frequency of communication is 19.2MHz, than, the used clock signal of time clock feature only needs 32.768KHz usually, far below the required clock frequency of CDMA communication.Therefore, need usually in the device for mobile communication at least two quartz (controlled) oscillators are installed, one are used to provide the used high-frequency oscillation signal of communication, and one are used to provide the used oscillating signal of clock.
Yet the running of two quartz (controlled) oscillators needs sizable electric energy usually.Even especially device for mobile communication is under energy-conservation pattern, for example: deep sleep mode (deep sleep mode) or real-time clock pattern (RTC mode), provide the quartz (controlled) oscillator of oscillating signal to operate, still can show the correct time after just making device for mobile communication return to operating mode.The low frequency quartz (controlled) oscillator that this must operate always can continue consumed power, and makes the stand-by time of device for mobile communication shorten.
In addition, the quartz (controlled) oscillator cost is quite expensive.Therefore, it is accurate that the present technique field needs a kind of while can keep time of device for mobile communication, again can be energy-conservation and the clock apparatus that reduces production cost.
Summary of the invention
The invention provides a kind of technology, make device for mobile communication special-purpose quartz (controlled) oscillator is set for time clock feature.The present invention produces circuit (for example oscillation device of electric current/electric capacity oscillator or RC oscillator or other non-quartz (controlled) oscillator) with lower-cost oscillator signal, and replacing the higher quartz (controlled) oscillator of cost provides clock used oscillator signal with generation.
In one embodiment, disclose a kind of clock generator, produce a circuit and a deaccentuator comprising one first accumulator, an oscillator signal.This first accumulator comprises a first input end, one second input, one first control end, one first summation output and one first overflow output, and this second input couples this first summation output.This oscillator signal produces the non-quartz (controlled) oscillator of circuit, can adopt electric current/electric capacity oscillator or RC oscillator.This oscillator signal produces circuit and produces one first oscillator signal, and adjusts the frequency of this first oscillator signal according to one first overflow output signal of this first overflow output of this first accumulator.This deaccentuator is in order to produce a frequency control value according to this first oscillator signal and an oscillating reference signal.Wherein, this first input end of this first accumulator receives this frequency control value, and this first control end receives this first oscillator signal and makes this first accumulator this frequency control value that adds up according to this, and produces this first overflow output signal.
Above-mentioned clock generator can be installed in the mobile device.This device for mobile communication can be done the communication transmission according to a high-frequency oscillation signal, and the oscillating signal gate time that uses this clock generator to provide.
In one embodiment, this device for mobile communication can also comprise a quartz (controlled) oscillator and a reference signal generation circuit except above-mentioned clock generator.This quartz (controlled) oscillator is used to provide above-mentioned high-frequency oscillation signal, and this reference signal generation circuit produces this oscillating reference signal according to this high-frequency oscillation signal that this quartz (controlled) oscillator provided.
In addition, about the disclosed clock generation method of the present invention, its a kind of execution mode comprises: produce circuit by an oscillator signal and produce one first oscillator signal; Produce a frequency control value according to this first oscillator signal and an oscillating reference signal; According to this first oscillator signal this frequency control value that adds up, indicate to produce one first overflow; And the frequency that indicates this first oscillator signal of adjustment according to this first overflow.
Below enumerate several execution modes of the present invention and correlative type.
Description of drawings
Fig. 1 produces a kind of execution mode of circuit for oscillator signal;
Fig. 2 is a kind of execution mode of clock generation circuit that the present invention discloses;
A kind of execution mode of Fig. 3 diagram deaccentuator of the present invention;
A kind of execution mode of Fig. 4 diagram Fig. 3 frequency comparator 306;
A kind of execution mode of Fig. 5 diagram oscillating reference signal generator of the present invention;
Fig. 6 illustrates the operation of non-integer frequency eliminator 502 with oscillogram;
Fig. 7 is with a kind of execution mode of block diagram illustration device for mobile communication of the present invention; And
Fig. 8 is with a kind of execution mode of flow chart narration oscillating signal generating routine of the present invention.
[main element label declaration]
100～oscillator signal produces circuit; 102～arithmetic logic unit;
200～clock generation circuit; 202～accumulator;
204～buffer; 206～oscillator signal produces circuit;
300～deaccentuator; 302,304～frequency eliminator;
306～frequency comparator; 308～accumulator;
The summation output of 310～accumulator 308;
402～phase frequency transducer; 404～XOR gate;
406,408～D flip-flop; 410～D flip-flop control signal;
500～oscillating reference signal generator;
502～non-integer frequency eliminator; 504～accumulator;
506～frequency elimination controlling value;
508～quartz (controlled) oscillator;
700～device for mobile communication; 702～control unit;
A[N-1:0]～numerical value of the summation output of accumulator 202;
A[N]～output of the overflow of accumulator 202;
B[P-1:0]～numerical value of the summation output of accumulator 504;
B[P]～output of the overflow of accumulator 504;
C～electric capacity; Cmp1, Cmp2～comparator;
CS～control signal;
DN～following number signal;
FH～high-frequency oscillation signal;
FL～oscillating signal; Oscillating signal behind fL '～frequency elimination;
Fref～oscillating reference signal; Oscillating reference signal behind fref '～frequency elimination;
I1, I2～current source;
Two integer multiples that K, K+1～non-integer frequency eliminator 502 provides are selected for use when its frequency elimination;
The signal that S1...S4～arithmetic logic unit 102 is produced;
SW1, SW2～switch;
The cycle of oscillation of TH～high-frequency oscillation signal fH;
The cycle of oscillation of TL～oscillating signal fL;
UP～upward several signals;
V1, V2～reference signal; Vout～output signal.
Embodiment
Be different from conventional art and produce oscillator signal with quartz (controlled) oscillator, the disclosed clock generator of the present invention adopt electric current/electric capacity oscillator (I/C osci1lator) or other non-quartz (controlled) oscillator (and even can be made as circuit, with design at chip internal) oscillation device realize the function of signal oscillating.The present invention improves on those non-quartz (controlled) oscillators, and the frequency of oscillation that makes its output signal is adjustable, below is referred to as oscillator signal and produces circuit.
Fig. 1 is a kind of execution mode of oscillator signal generation circuit of the present invention, wherein adopts electric current/electric capacity oscillator to make output signal Vout vibration.Oscillator signal produces circuit 100 and has current source I1 and I2, switch SW 1 and SW2, capacitor C, comparator C mp1 and Cmp2 and arithmetic logic unit 102.Output signal Vout can export the input of comparator C mp1 and Cmp2 to, and respectively with two reference signal V1 of non-equivalence and V2 relatively.According to the output of comparator C mp1 and Cmp2, arithmetic logic unit 102 produces the conducting state of signal S1 and S2 difference control switch SW1 and SW2, and capacitor C can be discharged by current source I1 charging or by current source I2.Therefore, the current potential of output signal Vout can vibrate up and down.For example, reference potential V1 and V2 can be respectively the vibration upper limit and the lower limit of output signal Vout, and arithmetic logic unit 102 may command output signal Vout vibrate between vibration upper limit V1 and vibration lower limit V2.
Because various factorss such as ambient temperature or process variation all might make output signal Vout vibrate with ideal frequency, oscillator signal of the present invention produces circuit 100 more provides " frequency adjustment function " to overcome it.As shown in the figure, oscillator signal produces the frequency of oscillation that circuit 100 can determine output signal Vout according to a control signal CS.Arithmetic logic unit 102 can be adjusted the size of current that current source I1 and I2 are provided respectively according to control signal CS generation signal S3 and S4, and then changes the speed that discharges and recharges of capacitor C, with the frequency of oscillation of control output signal Vout.For example, control signal CS can represent the information of one (one bit).When control signal CS is a logic ' 1 ', signal S3 and S4 that logical operation circuit 102 is provided can increase the electric current that current source I1 and I2 are provided, and promote the frequency of oscillation of output signal Vout.When control signal CS is a logic ' 0 ', signal S3 and S4 that logical operation circuit 102 is provided can reduce the electric current that current source I1 and I2 are provided, and then reduce the frequency of oscillation (also can use opposite logic rules in other embodiment) of output signal Vout.In an embodiment, the design of supposing original (do not have consider control signal CS value) oscillator signal generation circuit 100 makes that the frequency of oscillation of output signal Vout is fo, control signal CS can make output signal Vout change the vibration with frequency 1.5*fo at the most when being logic ' 1 ', and control signal CS can make output signal Vout that minimum changing with frequency 0.5*fo vibrated when being logic ' 0 '.
Fig. 2 is a kind of execution mode of clock generation circuit that the present invention discloses.Clock generation circuit 200 comprises: an accumulator 202, a buffer 204 and an oscillator signal that does not have a quartz (controlled) oscillator produce circuit 206 (oscillator signal that can be Fig. 1 produces circuit 100), can be used to produce an oscillating signal fL device of powering and realize time clock feature.In execution mode shown in Figure 2, oscillator signal produces the signal A[N that circuit 206 is received] and the oscillating signal fL that the is exported oscillator signal that can distinguish corresponding diagram 1 produce circuit 100 control signal CS that is received and the output signal Vout that is supplied.Accumulator 202 provides N bit arithmetic, A[N-1:0] be accumulation result, and A[N] be that overflow is exported.Buffer 204 is in order to provide a frequency control value to accumulator 202 operation that adds up.Accumulator 202 can add up this frequency control value repeatedly with oscillating signal fL as control frequency, and with the overflow output A[N that produces] offer oscillator signal generation circuit 206 to adjust the frequency of oscillating signal fL.
By structure shown in Figure 2 as can be known, buffer 204 frequency control value of being kept in can be used to determine total body frequency (long-time long-term sight frequency) of oscillating signal fL.
For setting aforementioned frequency control value, the present invention also discloses a deaccentuator, in order to seek out buffer 204 storages that optimized frequency control value is transferred to Fig. 2 according to an above-mentioned oscillating signal fL and an oscillating reference signal (claiming fref).A kind of execution mode of Fig. 3 diagram deaccentuator.Deaccentuator 300 comprises two frequency eliminators 302 and 304, one frequency comparator 306 and an accumulator 308.Frequency eliminator 302 and 304 is to be used for guaranteeing that the operation of deaccentuator 300 can restrain, and the figure place (N) of the frequency elimination multiple that frequency eliminator 302 and 304 is provided and the accumulator 202 of clock generation circuit 200 is relevant.For example, frequency eliminator 302 and 304 can a multiple 2
M(M is the integer greater than N) obtains oscillating reference signal fref ' behind low frequency oscillation signal fL ' and the frequency elimination behind the frequency elimination to oscillating signal fL and oscillating reference signal fref frequency elimination respectively, and deaccentuator 300 can be proofreaied and correct oscillating signal fL to oscillating reference signal fref really.
Above-mentioned oscillating signal fL and oscillating reference signal fref are coupled to frequency comparator 306 through frequency eliminator 302 and 304 respectively, transfer to the relatively size of its frequency of frequency comparator 306.If the frequency of oscillating signal fL is greater than the frequency of oscillating reference signal fref, frequency comparator 306 output frequency comparative results 1; If the frequency of oscillating signal fL equals the frequency of oscillating reference signal f ref, frequency comparator 306 output frequency comparative results 0; If the frequency of oscillating signal fL is less than the frequency of oscillating reference signal fref, frequency comparator 306 output frequency comparative results-1.The said frequencies comparative result of frequency comparator 306 outputs can be imported accumulator 308, makes the signal on accumulator 308 fine-tuning its summation outputs 310, is stored in the buffer 204 of clock generation circuit 200 as said frequencies control numerical value.
Fig. 3 more discloses a kind of execution mode of accumulator 308.As shown in the figure, two inputs of accumulator 308 receive the signal of self summation output 310 and the frequency comparative result that frequency comparator 306 transmits respectively.Oscillating reference signal fref can be coupled to the control end of accumulator 308 through frequency eliminator 304, as the control frequency of accumulator 308.
Fig. 4 discloses a kind of execution mode of the frequency comparator 306 of Fig. 3, comprising phase frequency transducer 402, XOR gate 404 and two D flip-flops 406 and 408.Oscillating reference signal fref ' behind oscillating signal fL ' behind the frequency elimination and the frequency elimination stems from oscillating signal fL and oscillating reference signal fref respectively; 402 receptions of phase frequency transducer, and in the frequency of oscillating signal fL number signal UP in the activation one during greater than the frequency of oscillating reference signal fref, and in the frequency of oscillating signal fL during less than the frequency of oscillating reference signal fref activation count signal DN once.XOR gate 404 produces a D flip-flop control signal 410 according to the above-mentioned number signal UP that goes up with following number signal DN.First D flip-flop 406 receives goes up number signal UP, and according to these D flip-flop control signal 410 operations, to provide frequency comparative result 1 during greater than the frequency of oscillating reference signal fref in the frequency of oscillating signal fL.Second D flip-flop 408 receives number signal DN down, and according to these D flip-flop control signal 410 operations, to provide frequency comparative result-1 during less than the frequency of oscillating reference signal fref in the frequency of oscillating signal fL.If the frequency of oscillating signal fL equals the frequency of oscillating reference signal fref, D flip-flop 406 and 408 all can output frequency comparative result 0; At this moment, the fine setting of 300 pairs of frequency control value of deaccentuator of Fig. 3 convergence, correction program has found its optimum value.What note is, the invention is not restricted to use D flip-flop, also can use other trigger-as toggle flip-flop-to reach same effect in other embodiments.
About the oscillating reference signal fref that Fig. 3 deaccentuator 300 is received, the present invention also discloses an oscillating reference signal generator it is provided.Fig. 5 shows a kind of execution mode of oscillating reference signal generator.Oscillating reference signal generator 500 comprises: a non-integer frequency eliminator 502 and an accumulator 504.Non-integer frequency eliminator 502 receives a high-frequency oscillation signal fH, and dynamically exports B[P according to an overflow of accumulator 504] with multiple this high-frequency oscillation signal of multiple frequency elimination fH, to form above-mentioned oscillating reference signal fref.As shown in the figure, accumulator 504 is the P bit accumulator, in order to operation that a frequency elimination controlling value 506 is added up to produce accumulation result B[P-1:0] with overflow output B[P], wherein accumulator 504 with oscillating reference signal fref as control frequency.As overflow output B[P] when be logic ' 0 ', non-integer frequency eliminator 502 is understood with one first this high-frequency oscillation signal of integer (as integer K) frequency elimination fH.As overflow output B[P] when be logic ' 1 ', non-integer frequency eliminator 502 is understood with one second integer (as integer K+1) this high-frequency oscillation signal of frequency elimination fH.(long-term) of long-time sight, oscillating reference signal fref is the non-integer frequency elimination result of high-frequency oscillation signal fH.
Fig. 6 illustrates the operation of non-integer frequency eliminator 502 with oscillogram, for convenience of description, supposes that the K value is 1, and above-mentioned first integer and second integer are respectively ' 1 ' and ' 2 '.The once vibration TH consuming time that shows high-frequency oscillation signal fH among the figure.If this overflow output B[P] between logic ' 1 ' and ' 0 ', switch repeatedly, when overflow is exported B[P] when being logic ' 1 ', with ' 2 ' frequency elimination, the cycle that obtains oscillating reference signal fref is 2TH with high-frequency oscillation signal fH; As overflow output B[P] when being logic ' 0 ', with ' 1 ' frequency elimination, the cycle that obtains oscillating reference signal fref is 1TH with high-frequency oscillation signal fH.So repeatedly to high-frequency oscillation signal fH with ' 2 ' and ' 1 ' frequency elimination, then can figure in the waveform of oscillating reference signal fref.Long-time sight, the period T L of oscillating reference signal fref is that 1.5TH is (because of (2TH+1TH)/2=1.5TH).The frequency of high-frequency oscillation signal fH is formed oscillating reference signal fref by one non-integer-1.5-frequency elimination.
The high-frequency oscillation signal fH that oscillating reference signal generator 500 received can be provided by a quartz (controlled) oscillator 508.With the CDMA communication system is example, and quartz (controlled) oscillator 508 designs provide the high-frequency oscillation signal fH of 19.2MHz, and in one embodiment of the invention, accumulator 504 can be the accumulator of 4 (P=4), and frequency elimination controlling value 506 can be set at binary number ' 1111 '.As overflow output B[P] be logic " 1 ' time, non-integer frequency eliminator 502 with high-frequency oscillation signal fH with ' 586 ' frequency elimination; As overflow output B[P] when being logic ' 0 ', non-integer frequency eliminator 502 with high-frequency oscillation signal fH with ' 585 ' frequency elimination.Thus, descend the frequency of oscillating reference signal fref can be accurate 32.768KHz for a long time, but incoming frequency correcting circuit 300 use.
The circuit of above-mentioned each figure can be incorporated in the device for mobile communication.Fig. 7 shows its application in device for mobile communication with calcspar.In this embodiment, device for mobile communication 700 comprises a control unit 702, quartz (controlled) oscillator shown in Figure 5 508 and oscillating reference signal generator 500, deaccentuator 300 shown in Figure 3 and clock generation circuit 200 shown in Figure 2.Quartz (controlled) oscillator 508, oscillating reference signal generator 500 need not to open with deaccentuator 300 always, and its enabled status can be by control unit 702 controls.
Device for mobile communication 700 is operable in a communication mode or a low power consuming pattern.Under communication mode, control unit 702 activation quartz (controlled) oscillators 508 are with the high-frequency oscillation signal fH that provides communication to use.In addition, during quartz (controlled) oscillator 508 activations, but control unit 702 activation oscillating reference signal generators 500 and deaccentuators 300, to set the stored frequency control value of buffer in the clock generation circuit 200 204.Under the low power consuming pattern, control unit 702 is with quartz (controlled) oscillator 508, oscillating reference signal generator 500 and deaccentuator 300 decapacitation, to save electric energy.Yet.The required clock signal of time clock feature can be provided based on the frequency control value that stores in its buffer 204 constantly by clock generation circuit 200 under the low power consuming pattern, wherein, oscillator signal in the clock generation circuit 200 produces circuit 206 (oscillator signal that can be Fig. 1 produces circuit 100) can shoulder the function that produces oscillator signal, and need not to use any quartz (controlled) oscillator.Above-mentioned design makes device for mobile communication 700 dispose exclusive quartz (controlled) oscillator for time clock feature, just can provide the oscillating signal (fL) of high accuracy to use for time clock feature.Use device for mobile communication of the present invention not only can reach less electricity consumption, more can reduce production costs.
What must state is that aforementioned oscillator signal produces circuit 206 and non-limiting employing electric current/electric capacity oscillation technology shown in Figure 1.The oscillation device of every non-quartz (controlled) oscillator, no matter be electric current/electric capacity oscillator (I/C oscillator) or RC oscillator (RC oscillator) or other known oscillating circuit, all can do distortion slightly and be used for realizing that oscillator signal produces circuit 206, make it can adjust the frequency of oscillation of output signal according to the control signal (the control signal CS of corresponding diagram 1 embodiment) of single position.In some embodiments, oscillator signal produces circuit 206 can be made in chip internal, provides the purpose of oscillator signal to implement low cost.
In addition, above-mentioned technology does not limit entirely and realizes with hardware mode, can part realize in the firmware mode yet.
Fig. 8 is with a kind of execution mode of flow chart narration oscillating signal generating routine of the present invention.S802 discloses as step, wherein produces a high-frequency oscillation signal fH with a quartz (controlled) oscillator 508, and produces an oscillating reference signal fref according to this high-frequency oscillation signal fH.Step S804 comprises: produce an oscillating signal fL with electric current/electric capacity oscillator or RC oscillator, and adjust the frequency of this oscillating signal fL according to a frequency control value, and compare above-mentioned oscillating reference signal fref and oscillating signal fL with this frequency control value of optimization.Step S806, whether determination frequency control numerical value optimization? if determination frequency control numerical value is optimization not, flow process will be got back to step S804, continue to adjust with the frequency control value of dynamic change the frequency of oscillating signal.Otherwise,, then carry out subsequent step S808 if step S806 determination frequency is controlled numerical value optimization.Step S808 is temporary in a buffer with the frequency control value after the optimization, and when the low power consuming pattern the above-mentioned quartz (controlled) oscillator of decapacitation, avoid this quartz (controlled) oscillator to continue consumed power.Step S810 when the low power consuming pattern, adjusts the frequency of this oscillating signal according to the stored frequency control value of buffer, and the frequency that makes this oscillating signal is an optimum value.
The described flow process of Fig. 8 successfully overcomes common frequency of oscillation offset problem in electric current/electric capacity oscillator or the RC oscillator.Disclosed oscillating signal producing method can be applicable in the various electronic installations.
Aforementioned numerous embodiments is with helping understand the present invention, is not to be used for limiting claim scope of the present invention.Claim scope of the present invention is asked for an interview the aforesaid right claimed range.
Claims (14)
1. clock generator comprises:
First accumulator comprises first input end, second input, first control end, the first summation output and the first overflow output, and this second input couples this first summation output;
Oscillator signal produces circuit, produces first oscillator signal, and adjusts the frequency of this first oscillator signal according to first overflow output signal of this first overflow output of this first accumulator; And
Deaccentuator, in order to producing frequency control value according to this first oscillator signal and an oscillating reference signal,
Wherein, this first input end of this first accumulator receives this frequency control value, and this first control end receives this first oscillator signal and makes this first accumulator this frequency control value that adds up according to this, and produces this first overflow output signal.
2. clock generator according to claim 1, wherein this deaccentuator also comprises:
Frequency comparator is used for relatively the frequency of this first oscillator signal and the frequency of this oscillating reference signal, and produces the frequency comparative result; And
Second accumulator, comprise the 3rd input, four-input terminal, second control end and the second summation output, this four-input terminal couples this second summation output, the 3rd input of this second accumulator receives this frequency comparative result that this frequency comparator is exported, this second control end couples this oscillating reference signal and makes this second accumulator this frequency comparative result that adds up according to this, and this second summation output of this second accumulator provides this frequency control value.
3. clock generator according to claim 2, wherein:
When the frequency of this first oscillator signal during greater than the frequency of this oscillating reference signal, this frequency comparative result that this frequency comparator produces is 1;
When the frequency of this first oscillator signal equaled the frequency of this oscillating reference signal, this frequency comparative result that this frequency comparator produces was 0; And
When the frequency of this first oscillator signal during less than the frequency of this oscillating reference signal, this frequency comparative result that this frequency comparator produces is-1.
4. clock generator according to claim 2, wherein this deaccentuator also comprises:
First frequency eliminator couples this oscillator signal and produces circuit and this frequency comparator, is used for this first oscillator signal with 2
MProvide behind the frequency elimination to this frequency comparator; And
Second frequency eliminator, with this oscillating reference signal with 2
MThis second control end to this frequency comparator and this second accumulator is provided behind the frequency elimination,
Wherein M is the integer greater than the figure place of this first accumulator.
5. clock generator according to claim 1 also comprises the oscillating reference signal generator, comprising:
The 3rd accumulator, comprise the 5th input, the 6th input, the 3rd control end, the 3rd summation output and the second overflow output, wherein, the 6th input couples the 3rd summation output, the 5th input receives the frequency elimination controlling value, the 3rd control end receives this oscillating reference signal and makes the 3rd accumulator this frequency elimination controlling value that adds up according to this, and produces second overflow output signal and by this second overflow output output; And
The non-integer frequency eliminator, receive second oscillator signal, and according to this second overflow output signal of the 3rd accumulator with this second oscillator signal of multiple integer multiple frequency elimination, to produce this oscillating reference signal, wherein, the frequency of this second oscillator signal is greater than the frequency of this first oscillator signal.
6. clock generator according to claim 5, wherein this second oscillator signal is provided by quartz (controlled) oscillator.
7. clock generator according to claim 1 also comprises buffer, in order to temporary this frequency control value.
8. clock generator according to claim 1, wherein this oscillator signal produces circuit and comprises following one: electric current/electric capacity oscillator and RC oscillator.
9. device for mobile communication comprises:
Quartz (controlled) oscillator provides high-frequency oscillation signal;
Clock generator provides oscillating signal, and this clock generator comprises:
First accumulator comprises first input end, second input, first control end, the first summation output and the first overflow output, and this second input couples this first summation output;
Oscillator signal produces circuit, produces this oscillating signal, and adjusts the frequency of this oscillating signal according to first overflow output signal of this first overflow output of this first accumulator; And
Deaccentuator, in order to producing frequency control value according to this oscillating signal and an oscillating reference signal,
Wherein, this first input end of this first accumulator receives this frequency control value, and this first control end receives this oscillating signal and makes this first accumulator this frequency control value that adds up according to this, and produces this first overflow output signal; And
Oscillating reference signal produces circuit, produces this oscillating reference signal according to this high-frequency oscillation signal that this quartz (controlled) oscillator provided.
10. clock generation method comprises:
Produce circuit by oscillator signal and produce first oscillator signal;
Produce frequency control value according to this first oscillator signal and an oscillating reference signal;
According to this first oscillator signal this frequency control value that adds up, indicate to produce first overflow; And
Indicate the frequency of adjusting this first oscillator signal according to this first overflow.
11. clock generation method according to claim 10 also comprises:
The frequency of this first oscillator signal and this oscillating reference signal relatively is to produce the frequency comparative result; And
Add up this frequency comparative result of this first oscillator signal and this oscillating reference signal, obtaining this frequency control value,
Wherein:
When the frequency of this first oscillator signal during greater than the frequency of this oscillating reference signal, this frequency comparative result of generation is 1;
When the frequency of this first oscillator signal equaled the frequency of this oscillating reference signal, this frequency comparative result of generation was 0; And
When the frequency of this first oscillator signal during less than the frequency of this oscillating reference signal, this frequency comparative result of generation is-1.
12. clock generation method according to claim 11 also comprises:
Before the frequency of relatively this first oscillator signal and this oscillating reference signal, with this first oscillator signal and this oscillating reference signal with 2
MFrequency elimination,
Wherein M is the integer greater than the figure place of first accumulator, and this first accumulator is used to carry out the step of said frequencies control numerical value of adding up.
13. clock generation method according to claim 10 also comprises:
Add up a frequency elimination controlling value to produce second overflow sign according to this oscillating reference signal; And
Indicate second oscillator signal that produces with multiple integer multiple frequency elimination quartz (controlled) oscillator according to this second overflow, to produce this oscillating reference signal, wherein the frequency of this second oscillator signal is greater than the frequency of this first oscillator signal.
14. clock generation method according to claim 13 also comprises:
Provide buffer to keep in this frequency control value, when this quartz (controlled) oscillator forbidden energy, this frequency control value that is temporary in this buffer that adds up indicates to produce this first overflow.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210449559.3A CN102983843B (en) | 2010-04-22 | 2010-04-22 | Clock generator and mobile communication device |
| CN2010101679632A CN101854156B (en) | 2010-04-22 | 2010-04-22 | Clock generator, clock generation method and mobile communication device |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2010101679632A CN101854156B (en) | 2010-04-22 | 2010-04-22 | Clock generator, clock generation method and mobile communication device |
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| CN201210449559.3A Division CN102983843B (en) | 2010-04-22 | 2010-04-22 | Clock generator and mobile communication device |
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| CN101854156A true CN101854156A (en) | 2010-10-06 |
| CN101854156B CN101854156B (en) | 2013-01-02 |
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|---|---|---|---|
| CN201210449559.3A Expired - Fee Related CN102983843B (en) | 2010-04-22 | 2010-04-22 | Clock generator and mobile communication device |
| CN2010101679632A Expired - Fee Related CN101854156B (en) | 2010-04-22 | 2010-04-22 | Clock generator, clock generation method and mobile communication device |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201210449559.3A Expired - Fee Related CN102983843B (en) | 2010-04-22 | 2010-04-22 | Clock generator and mobile communication device |
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| Country | Link |
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| CN (2) | CN102983843B (en) |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3380651B2 (en) * | 1995-04-12 | 2003-02-24 | 川崎マイクロエレクトロニクス株式会社 | Variable frequency divider |
| CN1797955A (en) * | 2004-12-29 | 2006-07-05 | 泰拉丁公司 | Multi-stage digital counting oscillator |
| CN1815886A (en) * | 2005-02-04 | 2006-08-09 | 联发科技股份有限公司 | Clock generator circuit and related method for generating output clock signal |
| US7215167B1 (en) * | 2006-04-28 | 2007-05-08 | Giga-Tronics, Inc. | Low noise microwave frequency synthesizer having fast switching |
| CN101272142A (en) * | 2008-05-20 | 2008-09-24 | 曹秀娟 | Frequency synthesizer |
-
2010
- 2010-04-22 CN CN201210449559.3A patent/CN102983843B/en not_active Expired - Fee Related
- 2010-04-22 CN CN2010101679632A patent/CN101854156B/en not_active Expired - Fee Related
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3380651B2 (en) * | 1995-04-12 | 2003-02-24 | 川崎マイクロエレクトロニクス株式会社 | Variable frequency divider |
| CN1797955A (en) * | 2004-12-29 | 2006-07-05 | 泰拉丁公司 | Multi-stage digital counting oscillator |
| CN1815886A (en) * | 2005-02-04 | 2006-08-09 | 联发科技股份有限公司 | Clock generator circuit and related method for generating output clock signal |
| US7215167B1 (en) * | 2006-04-28 | 2007-05-08 | Giga-Tronics, Inc. | Low noise microwave frequency synthesizer having fast switching |
| CN101272142A (en) * | 2008-05-20 | 2008-09-24 | 曹秀娟 | Frequency synthesizer |
Also Published As
| Publication number | Publication date |
|---|---|
| CN102983843A (en) | 2013-03-20 |
| CN101854156B (en) | 2013-01-02 |
| CN102983843B (en) | 2015-07-01 |
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