CN101853855B - Manufacturing method of silicon wafer with perforating holes - Google Patents
Manufacturing method of silicon wafer with perforating holes Download PDFInfo
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- CN101853855B CN101853855B CN2009101311416A CN200910131141A CN101853855B CN 101853855 B CN101853855 B CN 101853855B CN 2009101311416 A CN2009101311416 A CN 2009101311416A CN 200910131141 A CN200910131141 A CN 200910131141A CN 101853855 B CN101853855 B CN 101853855B
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- silicon substrate
- perforating holes
- insulating barrier
- perforation
- perforating
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Abstract
The invention discloses a method for producing a silicon wafer with perforating holes, comprising: providing the silicon wafer including a silicon substrate, at least one electric element and at least one perforating hole, wherein the silicon substrate has a first surface and a second surface, the electric element is arranged in the silicon substrate and is exposed out of the second surface of the silicon substrate, the perforating hole is arranged in the silicon substrate and is composed of an insulating layer, a conductor, a first end and a second end connecting the electric element; removing part of the silicon substrate from the first surface of the silicon substrate to expose the first end of the perforating hole; forming the insulating layer for covering the first end of the exposed perforating hole, the insulating layer having a surface; and removing part of the insulating layer to expose the first end of the perforating hole on the surface of the insulating layer. Thus when a rerouting layer is formed on the surface of the insulating layer, the rerouting layer comes into no contact with the silicon substrate to avoid the problem of electric short circuit, thus the process with lower resolution can be used while the manufacturing cost is lowered and the processing step is simplified.
Description
Technical field
The present invention relates to a kind of silicon wafer and manufacturing approach thereof, particularly relate to a kind of silicon wafer and manufacturing approach thereof with perforating holes.
Background technology
With reference to figure 1 and Fig. 2, show known generalized section and partial enlarged drawing thereof with silicon wafer of perforating holes.This known silicon wafer 1 with perforating holes has silicon substrate 11, at least one electrical components 12, at least one perforating holes 13, insulating barrier 14 and rerouting layer 15.This silicon substrate 11 has first surface 111, second surface 112 and bores a hole 113.This electrical components 12 is positioned at this silicon substrate 11, and is revealed in the second surface 112 of this silicon substrate 11.This perforating holes 13 runs through this silicon substrate 11, and this perforating holes 13 comprises barrier layer 133 and electric conductor 134, and this barrier layer 133 is positioned at the sidewall of this perforation 113, and this electric conductor 134 is positioned at this barrier layer 133.This perforating holes 13 has first end 131 and second end 132, and this first end 131 is revealed in the first surface 111 of this silicon substrate 11, and this second end 132 connects this electrical components 12.This insulating barrier 14 is positioned at the first surface 111 of this silicon substrate 11, and this insulating barrier 14 has surface 141 and at least one opening 142, and this opening 142 appears first end 131 of this perforating holes 13.This rerouting layer 15 is positioned at the surface 141 and the opening 142 of this insulating barrier 14, and this rerouting layer 15 has at least one electric connection zone 151, in order to connect first end 131 of this perforating holes 13.
This is known, and to have the shortcoming of silicon wafer 1 of perforating holes following.The diameter D of the opening 142 of this insulating barrier 14
1Must be less than the aperture D of the perforation 113 of this silicon substrate 11
2, otherwise the electric connection of this rerouting layer 15 zone 151 can directly contact this silicon substrate 11, causes electrical short circuit.Yet this insulating barrier more than 14 carries out patterning with gold-tinted technology, and the resolution of gold-tinted technology is lower, is difficult to make precision and pattern accurately, and makes the diameter D of the opening 142 of this insulating barrier 14 easily
1Aperture D greater than the perforation 113 of this silicon substrate 11
2, make the electric connection zone 151 of this rerouting layer 15 directly contact this silicon substrate 11, cause electrical short circuit.Otherwise if this insulating barrier 14 carries out patterning with the technology of high-res, its follow-up needs are multiplex's skill more, causes processing step complicated, and manufacturing cost improves.
Therefore, be necessary to provide a kind of silicon wafer and manufacturing approach thereof, to address the above problem with perforating holes.
Summary of the invention
The present invention provides a kind of silicon wafer with perforating holes.This silicon wafer comprises silicon substrate, insulating barrier, at least one electrical components and at least one perforating holes.This silicon substrate has first surface and second surface.This insulating barrier is positioned at the first surface of this silicon substrate, and this insulating barrier has the surface.This electrical components is positioned at this silicon substrate, and is revealed in the second surface of this silicon substrate.This perforating holes runs through this silicon substrate and this insulating barrier, and this perforating holes comprises barrier layer and electric conductor, and has first end and second end, and this first end is revealed in the surface of this insulating barrier, and this second end connects this electrical components.
The present invention also provides a kind of manufacturing approach with silicon wafer of perforating holes.This manufacturing approach may further comprise the steps: silicon wafer (a) is provided, and this silicon wafer comprises silicon substrate, at least one electrical components and at least one perforating holes, and this silicon substrate has first surface and second surface; This electrical components is positioned at this silicon substrate; And be revealed in the second surface of this silicon substrate, this perforating holes is positioned at this silicon substrate, and this perforating holes comprises barrier layer and electric conductor; And have first end and second end, and this second end connects this electrical components; (b) first surface from this silicon substrate removes this silicon substrate of part, to appear first end of this perforating holes; (c) form insulating barrier, first end of the perforating holes that appears with covering, this insulating barrier has the surface; And (d) remove this insulating barrier of part, make first end of this perforating holes be revealed in the surface of this insulating barrier.
Thus; In the present invention, because first end of this perforating holes is revealed in the surface of this insulating barrier, when forming the rerouting layer in this insulating barrier surperficial; This rerouting layer can not contact this silicon substrate; Thereby can avoid electrical problem of short-circuit, so can use technology, reduce manufacturing cost simultaneously and simplify processing step than low-res.
Description of drawings
Fig. 1 shows known generalized section with silicon wafer of perforating holes;
The partial enlarged drawing of Fig. 2 displayed map 1;
Fig. 3 to Fig. 7 shows that the present invention has the sketch map of manufacturing approach of the silicon wafer of perforating holes; And
The partial enlarged drawing of Fig. 8 displayed map 7.
Description of reference numerals
1 known silicon wafer with perforating holes
The 2A silicon wafer
2B the present invention has the silicon wafer of perforating holes
11 silicon substrates, 12 electrical components
13 perforating holes, 14 look edge layers
15 rerouting layers
21 silicon substrates, 22 electrical components
23 perforating holes, 24 insulating barriers
25 rerouting layers
111 first surfaces, 112 second surfaces
113 perforation, 131 first ends
132 second ends, 133 barrier layers
134 electric conductors, 141 surfaces
142 openings 151 electrically connect the zone
211 first surfaces, 212 second surfaces
213 first perforation, 231 first ends
232 second ends, 233 barrier layers
234 electric conductors, 241 surfaces
242 second perforation 251 electrically connect the zone
Embodiment
To Fig. 7, show that the present invention has the sketch map of manufacturing approach of the silicon wafer of perforating holes with reference to figure 3.With reference to figure 3, silicon wafer 2A is provided, this silicon wafer 2A comprises silicon substrate 21, at least one electrical components 22 and at least one perforating holes 23.This silicon substrate 21 has first surface 211 and second surface 212.In the present embodiment, this silicon substrate 21 also has first perforation 213.This electrical components 22 is positioned at this silicon substrate 21, and is revealed in the second surface 212 of this silicon substrate 21.In the present embodiment, this electrical components 22 be complementary metal-oxide layer-semiconductor (ComplementaryMetal-Oxide-Semiconductor, CMOS).This perforating holes 23 is positioned at this silicon substrate 21; This perforating holes 23 comprises barrier layer 233 and electric conductor 234; And have first end 231 and second end 232; And this second end 232 connects this electrical components 22, and this perforating holes 23 does not run through this silicon substrate 21, that is first end 231 of this perforating holes 23 is not revealed in the first surface 211 of this silicon substrate 21.In the present embodiment, this barrier layer 233 is positioned at the sidewall of this first perforation 213, and this electric conductor 234 is positioned at this barrier layer 233, and the material of the electric conductor 234 of this perforating holes 23 is a copper.
With reference to figure 4, remove this silicon substrate 21 of part from the first surface 211 of this silicon substrate 21, to appear first end 231 of this perforating holes 23.In the present embodiment, (Chemical-Mechanical Polishing, CMP) method removes this silicon substrate 21 of part from the first surface 211 of this silicon substrate 21 to utilize etching, grinding or chemico-mechanical polishing.
With reference to figure 5, form insulating barrier 24, first end 231 of the perforating holes 23 that appears with covering, this insulating barrier 24 has surface 241.In the present embodiment, this insulating barrier 24 is for having the polymer (Low K Polymer) of low-k, for example polyimides (PI) or benzocyclobutene (Benzocyclobutance, BCB).Preferably, the dielectric constant of this insulating barrier 24 is less than 4.With reference to figure 6, remove this insulating barrier 24 of part, make first end 231 of this perforating holes 23 be revealed in the surface 241 of this insulating barrier 24.In the present embodiment, utilize etching or Ginding process to remove this insulating barrier 24 of part.In the present embodiment; This silicon substrate 21 has this first perforation 213; This insulating barrier 24 has second perforation 242; The aperture of this first perforation 213 and this second perforation 242 is identical, and this first perforation 213 and this second perforation 242 are connected, and this perforating holes 23 is positioned at this first perforation 213 and this second perforation 242.
With reference to figure 7, in the present embodiment, (Redistribution Layer RDL) in the surface 241 of this insulating barrier 24, forms the silicon wafer 2B that the present invention has perforating holes simultaneously also to form rerouting layer 25.This rerouting layer 25 has at least one electric connection zone 251, in order to connect first end 231 of this perforating holes 23.Preferably, the area in the electric connection of this rerouting layer 25 zone 251 is greater than the area of first end 231 of this perforating holes 23.Perhaps, the electric connection of this rerouting layer 25 zone 251 covers first end 231 of this perforating holes 23 fully.
Fig. 7 and Fig. 8 show that the present invention has the generalized section and the partial enlarged drawing thereof of the silicon wafer of perforating holes.With reference to figure 7 and Fig. 8, this silicon wafer 2B with perforating holes comprises silicon substrate 21, insulating barrier 24, at least one electrical components 22 and at least one perforating holes 23 again.In the present embodiment, this silicon wafer 2B with perforating holes also comprises rerouting layer 25.
This silicon substrate 21 has first surface 211 and second surface 212.This insulating barrier 24 is positioned at the first surface 211 of this silicon substrate 21, and this insulating barrier 24 has surface 241.In the present embodiment, this insulating barrier 24 is for having the polymer (Low K Polymer) of low-k, for example polyimides (PI) or benzocyclobutene (Benzocyclobutance, BCB).Preferably, the dielectric constant of this insulating barrier 24 is less than 4.
This electrical components 22 is positioned at this silicon substrate 21, and is revealed in the second surface 212 of this silicon substrate 21.In the present embodiment, this electrical components 22 be complementary metal-oxide layer-semiconductor (Complementary Metal-Oxide-Semiconductor, CMOS).
This perforating holes 23 runs through this silicon substrate 21 and this insulating barrier 24; This perforating holes 23 comprises barrier layer 233 and electric conductor 234; And have first end 231 and second end 232, this first end 231 is revealed in the surface 241 of this insulating barrier 24, and this second end 232 connects this electrical components 22.In the present embodiment, the material of the electric conductor 234 of this perforating holes 23 is a copper.In the present embodiment, this silicon substrate 21 has first perforation 213, and this insulating barrier 24 has second perforation 242, and the aperture of this first perforation 213 and this second perforation 242 is identical, and this first perforation 213 and this second perforation 242 are connected.This perforating holes 23 is positioned at this first perforation 213 and this second perforation 242, and this barrier layer 233 is positioned at this first perforation 213 and this second perforation, sidewall of 242, and this electric conductor 234 is positioned at this barrier layer 233.
In the present embodiment, this rerouting layer 25 is positioned at the surface 241 of this insulating barrier 24, and this rerouting layer 25 has at least one electric connection zone 251, in order to connect first end 231 of this perforating holes 23.Preferably, the area in the electric connection of this rerouting layer 25 zone 251 is greater than the area of first end 231 of this perforating holes 23.Perhaps, the electric connection of this rerouting layer 25 zone 251 covers first end 231 of this perforating holes 23 fully.
Thus, have among the silicon wafer 2B of perforating holes at this, because first end 231 of this perforating holes 23 is revealed in the surface 241 of this insulating barrier 24, the diameter D when the electric connection zone 251 of this rerouting layer 25
3Diameter D greater than first end 231 of this perforating holes 23
4The time, the electric connection zone 251 of this rerouting layer 25 only can contact this insulating barrier 24, and can not contact this silicon substrate 21, thereby can avoid electrical problem of short-circuit, so can use the technology than low-res, reduces manufacturing cost simultaneously and simplifies processing step.
The foregoing description is merely explanation principle of the present invention and effect thereof, but not in order to restriction the present invention.Therefore, persons skilled in the art are made amendment to the foregoing description and are changed and still do not take off spirit of the present invention.Interest field of the present invention should be liked claim enclosed and define.
Claims (8)
1. manufacturing approach with silicon wafer of perforating holes comprises:
(a) silicon wafer is provided, this silicon wafer comprises silicon substrate, at least one electrical components and at least one perforating holes, and this silicon substrate has first surface and second surface; This electrical components is positioned at this silicon substrate; And be revealed in the second surface of this silicon substrate, this perforating holes is positioned at this silicon substrate, and this perforating holes comprises barrier layer and electric conductor; And have first end and second end, this second end connects this electrical components;
(b) first surface from this silicon substrate removes this silicon substrate of part, to appear first end of this perforating holes;
(c) form insulating barrier, first end of the perforating holes that appears with covering, this insulating barrier has a surface; And
(d) remove this insulating barrier of part, make first end of this perforating holes be revealed in the surface of this insulating barrier.
2. method as claimed in claim 1, wherein in this step (a), this electrical components is complementary metal-oxide layer-semiconductor.
3. method as claimed in claim 1, wherein in this step (c), this insulating barrier is an advanced low-k materials, its dielectric constant is less than 4.
4. method as claimed in claim 1, wherein in this step (d), this silicon substrate has first perforation, and this insulating barrier has second perforation, and the aperture of this first perforation and this second perforation is identical, and this perforating holes is positioned at this first perforation and this second perforation.
5. method as claimed in claim 4, wherein this first perforation and this second perforation are connected.
6. method as claimed in claim 1, wherein this step (d) also comprises forming the rerouting layer in the step on the surface of this insulating barrier afterwards, this rerouting layer has at least one electric connection zone, in order to connect first end of this perforating holes.
7. method as claimed in claim 6, wherein the area in the electric connection of this rerouting layer zone is greater than the area of first end of this perforating holes.
8. method as claimed in claim 6, wherein the electric connection zone of this rerouting layer covers first end of this perforating holes fully.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
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| CN2009101311416A CN101853855B (en) | 2009-04-03 | 2009-04-03 | Manufacturing method of silicon wafer with perforating holes |
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|---|---|---|---|
| CN2009101311416A CN101853855B (en) | 2009-04-03 | 2009-04-03 | Manufacturing method of silicon wafer with perforating holes |
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| CN101853855A CN101853855A (en) | 2010-10-06 |
| CN101853855B true CN101853855B (en) | 2012-03-14 |
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Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20080119046A1 (en) * | 2006-11-21 | 2008-05-22 | Sparks Terry G | Method of making a contact on a backside of a die |
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- 2009-04-03 CN CN2009101311416A patent/CN101853855B/en active Active
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20080119046A1 (en) * | 2006-11-21 | 2008-05-22 | Sparks Terry G | Method of making a contact on a backside of a die |
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