CN101853804B - Method for manufacturing semiconductor device - Google Patents
Method for manufacturing semiconductor device Download PDFInfo
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- CN101853804B CN101853804B CN2009101305769A CN200910130576A CN101853804B CN 101853804 B CN101853804 B CN 101853804B CN 2009101305769 A CN2009101305769 A CN 2009101305769A CN 200910130576 A CN200910130576 A CN 200910130576A CN 101853804 B CN101853804 B CN 101853804B
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 40
- 239000004065 semiconductor Substances 0.000 title claims abstract description 34
- 238000000034 method Methods 0.000 title abstract description 12
- 239000004020 conductor Substances 0.000 claims abstract description 34
- 230000004888 barrier function Effects 0.000 claims description 30
- 239000013078 crystal Substances 0.000 claims description 16
- 229910052751 metal Inorganic materials 0.000 claims description 14
- 239000002184 metal Substances 0.000 claims description 14
- 239000010949 copper Substances 0.000 claims description 11
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 10
- 229910052802 copper Inorganic materials 0.000 claims description 10
- 229910045601 alloy Inorganic materials 0.000 claims description 2
- 239000000956 alloy Substances 0.000 claims description 2
- 239000000463 material Substances 0.000 abstract description 5
- 229910052710 silicon Inorganic materials 0.000 abstract description 5
- 239000010703 silicon Substances 0.000 abstract description 5
- 238000000227 grinding Methods 0.000 abstract description 4
- 239000002699 waste material Substances 0.000 abstract description 4
- 235000012431 wafers Nutrition 0.000 description 27
- 238000005530 etching Methods 0.000 description 15
- 238000001039 wet etching Methods 0.000 description 8
- 230000035515 penetration Effects 0.000 description 6
- 229910000967 As alloy Inorganic materials 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- 238000004070 electrodeposition Methods 0.000 description 4
- 239000007769 metal material Substances 0.000 description 4
- 238000009713 electroplating Methods 0.000 description 3
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 230000011664 signaling Effects 0.000 description 2
- 229910000679 solder Inorganic materials 0.000 description 2
- 239000010936 titanium Substances 0.000 description 2
- 229910017944 Ag—Cu Inorganic materials 0.000 description 1
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 1
- 229910020836 Sn-Ag Inorganic materials 0.000 description 1
- 229910020988 Sn—Ag Inorganic materials 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- HSGAUFABPUECSS-UHFFFAOYSA-N [Ag][Cu][Sn][Bi] Chemical compound [Ag][Cu][Sn][Bi] HSGAUFABPUECSS-UHFFFAOYSA-N 0.000 description 1
- PQIJHIWFHSVPMH-UHFFFAOYSA-N [Cu].[Ag].[Sn] Chemical compound [Cu].[Ag].[Sn] PQIJHIWFHSVPMH-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 229910052797 bismuth Inorganic materials 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 239000004332 silver Substances 0.000 description 1
- 229910000969 tin-silver-copper Inorganic materials 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P80/00—Climate change mitigation technologies for sector-wide applications
- Y02P80/30—Reducing waste in manufacturing processes; Calculations of released waste quantities
Abstract
The invention discloses a method for manufacturing a semiconductor device, comprising the following steps of: firstly, providing a wafer with an active surface and a back surface opposite to the active surface; then grinding the back surface of the wafer to obtain a thin wafer; forming a plurality of through holes with openings on the active surface and the back surface respectively on the thin wafer; forming insulating layers/conducting layers on the inner walls of the through holes and the active surface of the thin wafer; and filling the through holes with conductive material by an electrochemical mode. Making and filling through holes before thinning the wafer enables the through silicon via (TSV) technology to have shorter manufacturing time, higher reliability and lower material waste.
Description
Technical field
The invention relates to a kind of manufacturing approach of semiconductor device, particularly about the straight-through silicon wafer perforation of a kind of utilization (Through Silicon Via; TSV) manufacturing approach of the semiconductor device of technology.
Background technology
Three dimensional integrated circuits (3D IC) is to utilize advanced wafer stacking technology and be prepared from, and it is the integrated circuit (IC) that the chip of tool difference in functionality (chip) is stacked into the tool three-dimensional structure.Compared to the IC of two-dimensional structure, the technology of piling up of 3D IC not only can make 3D IC signaling path shorten, and more lets the running of 3D IC speed up, and the performance of tool low power consumption.Realize the technology of piling up of 3D IC, the TSV technology is that a new generation makes the chip that piles up can Interworking Technology.The TSV technology makes the signaling path of the chip chamber among the 3D IC shorter, so the running performance of 3D IC can be quicker, and owing to do not have the stacked die limited in number, so the TSV technology becomes one of key technology of present hot topic.
The process of traditional T SV technology at first forms a plurality of blind holes on wafer, then with electric conducting material blind hole is filled up, afterwards again with the wafer thinning, at last again through formation projection, cut crystal and pile up technology such as joint.
The mode of traditional T SV fabrication techniques perforation is that the back side of grinding wafers makes its thinning, till blind hole becomes perforation.It is deeply that common making upward need be made into the degree of depth of blind hole the last degree of depth of boring a hole; Have near the bottom of blind hole after the thinning partly and can be ground away; And electric conducting material wherein also can be ground away thereupon, so traditional T SV technology can cause the waste of electric conducting material, increases cost.
Moreover; Will darker blind hole filling up required Production Time needs longer; More uneconomical; And the darker blind hole of control bottom and the electric conducting material heap between its inwall place speed of filling out, make blind hole get that fully plating is filled out and the unlikely making that is formed with the hollow part that is not filled is difficult, and its success rate is also not high.In addition, the blind hole of high-aspect-ratio (Aspect ratio) causes the bad problem of insulating barrier and metal seed layer deposition quality easily.
In sum, at present the TSV technology still has needs the success rate of long filling perforation time and filling perforation not high, adds the partially conductive material and is ground away and cause shortcoming such as waste.These shortcomings are still to be overcome, in order to the sustainable development of 3DIC technology.
Summary of the invention
An example of the present invention provides a kind of manufacturing approach of semiconductor device, utilizes this manufacturing approach can make straight-through silicon wafer perforation (Through Silicon Via; TSV) technology shortens its Production Time, improves the reliability of its manufacturing and reduces the waste of its electric conducting material.
One of the manufacturing approach of semiconductor device of the present invention is implemented example at first provides tool one active face to reach a wafer at a back side that is oppositely arranged with this active face.Then, the back side of grinding wafers is to obtain a chip thinning.Afterwards, on this chip thinning, form a plurality of respectively at the through hole that has opening on the active face and the back side.Then, form an insulating barrier in the active face of this chip thinning and the inwall of those through holes.Subsequently, on this insulating barrier, form a conductive layer.Then, fill up electric conducting material in those through holes with electrochemical mode.Afterwards, at least one opening of this through hole respectively, form projection.At last, cut this chip thinning, to form crystal grain independent of each other.
Another of the manufacturing approach of semiconductor device of the present invention implemented example at first provides tool one active face to reach a wafer at a back side that is oppositely arranged with this active face.Then, the back side of grinding wafers is to obtain a chip thinning.Afterwards, on this chip thinning, form a plurality of respectively at the through hole that has opening on the active face and the back side.Then, form a conductive layer in this back side or this active face.Then, fill up electric conducting material in those through holes with electrochemical mode.Afterwards, remove this conductive layer.Then, at least one opening of this through hole respectively, form projection.At last, cut this chip thinning, to form crystal grain independent of each other.
Description of drawings
For let above-mentioned purpose of the present invention, feature and advantage can be more obviously understandable, elaborate below in conjunction with the accompanying drawing specific embodiments of the invention, wherein:
Figure 1A to Fig. 1 I is a series of generalized section, and it is the manufacturing approach of the semiconductor device of illustration first embodiment of the invention;
Fig. 2 A to Fig. 2 H is a series of generalized section, and it is the manufacturing approach of the semiconductor device of illustration second embodiment of the invention;
Fig. 3 A to Fig. 3 H is a series of generalized section, and it is the manufacturing approach of the semiconductor device of illustration third embodiment of the invention; And
Fig. 4 A to Fig. 4 I is a series of generalized section, and it is the manufacturing approach of the semiconductor device of illustration fourth embodiment of the invention.
The main element symbol description:
10 wafers
12 active faces
14 back sides
16 chip thinnings
18 through holes
20a, 20b opening
22 insulating barriers
24 inwalls
26 conductive layers
28 barrier layers
30 electric conducting materials
32 projections
34 crystal grain
36 conductive carriers
Embodiment
Figure 1A to Fig. 1 I is a series of generalized section, and it is the manufacturing approach of the semiconductor device of illustration first embodiment of the invention.Shown in Figure 1A, the manufacturing approach of the semiconductor device that first embodiment of the invention discloses at first provides a wafer 10.This wafer 10 comprises an active face 12, reaches a back side 14 that is oppositely arranged with this active face 12.Active face 12 is meant the surface that is loaded with integrated electronic circuit (Integrated circuitry) on the wafer 10, and the back side 14 can be in fact the plane parallel with active face 12.Then, shown in Figure 1B, the back side 14 of wafer 10 is ground, make it be thinned to a predetermined thickness, form a chip thinning 16.This predetermined thickness can be between 10 microns to 200 microns, and preferably, this predetermined thickness is about 50 microns.Afterwards, shown in Fig. 1 C, on this chip thinning 16, form a plurality of through holes 18.Those through holes 18 all run through this chip thinning 16, and making respectively, this through hole 18 has two openings (20a and 20b) that lay respectively on the active face 12 and the back side 14.Form one of a plurality of through holes 18 optional autoreaction property ion(ic) etchings of the mode on this chip thinning 16 (RIE), Deep Reaction property ion(ic) etching (DRIE), laser (LASER) and wet etching methods such as (Wet etching).Then, shown in Fig. 1 D, form an insulating barrier 22 in the active face 12 of this chip thinning 16 and the inwall 24 of those through holes 18.Insulating barrier 22 provides and is electrically insulated, and it is the function of filling metal penetration (Diffusion) to the chip thinning 16 of tool resistance barrier through hole 18 in addition also.
Subsequently, shown in Fig. 1 E, on insulating barrier 22, form a barrier layer 28 and a conductive layer 26 in regular turn.This barrier layer 28 can hinder barrier through hole 18 and fill metal penetration to chip thinnings 16, and this conductive layer 26 can be a electrochemical deposition process when electroplating the metal seed layer (Metal seed layer) of usefulness and being used for filling perforation.And for example shown in Fig. 1 F, fill up electric conducting material 30 in those through holes 18 with electrochemical mode, wherein electric conducting material 30 can be the metal materials such as alloy of copper or copper.Moreover shown in Fig. 1 G, respectively two openings of this through hole 18 (20a and 20b) are gone up and are formed corresponding and projection 32 that be connected with electric conducting material 30.In addition, shown in Fig. 1 H, cut this chip thinning 16, to form crystal grain 34 independent of each other.At last, a plurality of crystal grain 34 are piled up, wherein, the corresponding projection 32 of neighbouring crystal grain 34 pushes up mutually and supports.32 of the projections that support of top are through reflow (Reflow) mutually, projection 32 joints that top is mutually supported, and cause the crystal grain 34 that piles up to be engaged with each other, form a stacked structure.The material of projection 32 can be the solder containing pb that mainly comprises tin (Sn), plumbous (Pb), silver materials such as (Ag); Perhaps be lead-free solder, for example pure tin projection, Xi-Yin (Sn-Ag), Xi-Yin-bismuth (Sn-Ag-Bi), tin-silver-copper (Sn-Ag-Cu) or tin-silver-copper-bismuth materials such as (Sn-Ag-Cu-Bi) constitute.
Fig. 2 A to Fig. 2 H is a series of generalized section, and it is the manufacturing approach of the semiconductor device of illustration second embodiment of the invention.Shown in Fig. 2 A, the manufacturing approach of the semiconductor device that second embodiment of the invention discloses at first provides a wafer 10.This wafer 10 comprises an active face 12, reaches a back side 14 that is oppositely arranged with this active face 12.Active face 12 is meant the surface that is loaded with integrated electronic circuit (Integrated circuitry) on the wafer 10, and the back side 14 can be in fact the plane parallel with active face 12.Then, shown in Fig. 2 B, the back side 14 of wafer 10 is ground, make it be thinned to a predetermined thickness, form a chip thinning 16.The thickness of this chip thinning 16 can be between 10 microns to 200 microns, and preferably, this predetermined thickness is about 50 microns.Afterwards, shown in Fig. 2 C, on this chip thinning 16, form a plurality of through holes 18.Those through holes 18 all run through this chip thinning 16, and making respectively, this through hole 18 has two openings (20a and 20b) that lay respectively on the active face 12 and the back side 14.Form one of a plurality of through holes 18 optional autoreaction property ion(ic) etchings of the mode on this chip thinning 16 (RIE), Deep Reaction property ion(ic) etching (DRIE), laser (LASER) and wet etching methods such as (Wet etching).Then, shown in Fig. 2 D, the back side 14 of a conductive layer 36 in chip thinning 16 is set.In another embodiment, this conductive layer 36 is the active faces 12 that are arranged at chip thinning 16.Conductive layer 36 is the electrochemical deposition process when being used for filling perforation, and its material can be selected from one of copper (Cu), titanium (Ti), tungsten (W) or its alloy.
Subsequently, shown in Fig. 2 E, fill up electric conducting material 30 in those through holes 18, and after through hole 18 fills up, with etching solution this conductive layer 36 is removed again with electrochemical mode.Wherein electric conducting material 30 can be the metal materials such as alloy of copper or copper.And for example shown in Fig. 2 F, in respectively forming corresponding and projection 32 that be connected with electric conducting material 30 on two openings of this through hole 18 (20a and 20b).Moreover, shown in Fig. 2 G, cut this chip thinning 16, to form crystal grain 34 independent of each other.At last, shown in Fig. 2 H, a plurality of crystal grain 34 are piled up, wherein, the corresponding projection 32 of neighbouring crystal grain 34 pushes up mutually and supports.32 of the projections that support of top are through reflow (Reflow) mutually, projection 32 joints that top is mutually supported, and cause the crystal grain 34 that piles up to be engaged with each other, form a stacked structure.
Fig. 3 A to Fig. 3 H is a series of generalized section, and it is the manufacturing approach of the semiconductor device of illustration third embodiment of the invention.Shown in Fig. 3 A, the manufacturing approach of the semiconductor device that third embodiment of the invention discloses at first provides a wafer 10.This wafer 10 comprises an active face 12, reaches a back side 14 that is oppositely arranged with this active face 12.Active face 12 is meant the surface that is loaded with integrated electronic circuit (Integrated circuitry) on the wafer 10, and the back side 14 can be in fact the plane parallel with active face 12.Then, shown in Fig. 3 B, the back side 14 of wafer 10 is ground, make it be thinned to a predetermined thickness, form a chip thinning 16.This predetermined thickness can be between 10 microns to 200 microns, and preferably, this predetermined thickness is about 50 microns.Afterwards, shown in Fig. 3 C, on this chip thinning 16, form a plurality of through holes 18.Those through holes 18 all run through this chip thinning 16, and making respectively, this through hole 18 has two openings (20a and 20b) that lay respectively on the active face 12 and the back side 14.Form one of a plurality of through holes 18 optional autoreaction property ion(ic) etchings of the mode on this chip thinning 16 (RIE), Deep Reaction property ion(ic) etching (DRIE), laser (LASER) and wet etching methods such as (Wet etching).Then, shown in Fig. 3 D, form an insulating barrier 22 in the active face 12 of this chip thinning 16 and the inwall 24 of those through holes 18.Insulating barrier 22 provides and is electrically insulated and the function of filling metal penetration to the chip thinning 16 of tool resistance barrier through hole 18.
Subsequently, shown in Fig. 3 E, on insulating barrier 22, form a barrier layer 28 and a conductive layer 26 in regular turn.This barrier layer 28 can hinder barrier through hole 18 and fill metal penetration to chip thinnings 16, and this conductive layer 26 can be a electrochemical deposition process when electroplating the metal seed layer (Metal seed layer) of usefulness and being used for filling perforation.Again, shown in Fig. 3 F, fill up electric conducting material 30 in those through holes 18 with electrochemical mode, wherein electric conducting material 30 can be the metal materials such as alloy of copper or copper.Again, shown in Fig. 3 G, the opening 20a that is positioned at chip thinning 16 active faces 12 in this through hole 18 respectively goes up and forms the projection 32 that is connected with electric conducting material 30.In another embodiment, projection 32 is formed at this through hole 18 and is positioned at the opening 20b on the back side 14.At last, utilize microetch (Micro-etching) technology that the electric conducting material 30 that each through hole 18 is not provided with another opening 20b of projection 32 is carried out etching, make it form concavity down, shown in Fig. 3 H.After microetch (Micro-etching) technology finishes, cut this chip thinning 16, to form independently of one another and can be engaged with each other, form the crystal grain 34 of a stacked structure.
Fig. 4 A to Fig. 4 I is a series of generalized section, and it is the manufacturing approach of the semiconductor device of illustration fourth embodiment of the invention.Shown in Fig. 4 A, the manufacturing approach of the semiconductor device that fourth embodiment of the invention discloses at first provides a wafer 10.This wafer 10 comprises an active face 12, reaches a back side 14 that is oppositely arranged with this active face 12.Active face 12 is meant the surface that is loaded with integrated electronic circuit (Integrated circuitry) on the wafer 10, and the back side 14 can be in fact the plane parallel with active face 12.Then, shown in Fig. 4 B, the back side 14 of wafer 10 is ground, make it be thinned to a predetermined thickness, form a chip thinning 16.This predetermined thickness can be between 10 microns to 200 microns, and preferably, this predetermined thickness is about 50 microns.Afterwards, shown in Fig. 4 C, on this chip thinning 16, form a plurality of through holes 18.Those through holes 18 all run through this chip thinning 16, and making respectively, this through hole 18 has two openings (20a and 20b) that lay respectively on the active face 12 and the back side 14.Form one of a plurality of through holes 18 optional autoreaction property ion(ic) etchings of the mode on this chip thinning 16 (RIE), Deep Reaction property ion(ic) etching (DRIE), laser (LASER) and wet etching methods such as (Wet etching).Then, shown in Fig. 4 D, form an insulating barrier 22 in the active face 12 of this chip thinning 16 and the inwall 24 of those through holes 18.Insulating barrier 22 provides the function of filling metal penetration to the chip thinning 16 of the function that is electrically insulated and tool resistance barrier through hole 18.
Subsequently, shown in Fig. 4 E, on this insulating barrier 22, form a barrier layer 28 and a conductive layer 26 in regular turn.This barrier layer 28 can hinder barrier through hole 18 and fill metal penetration to chip thinnings 16, and this conductive layer 26 can be a electrochemical deposition process when electroplating the metal seed layer (Metal seed layer) of usefulness and being used for filling perforation.And for example shown in Fig. 4 F, fill up electric conducting material 30 in those through holes 18 with electrochemical mode, wherein electric conducting material 30 can be the metal materials such as alloy of copper or copper.Moreover shown in Fig. 4 G, respectively this through hole 18 is positioned on the opening 20a of active face 12, forms the projection 32 that is connected with electric conducting material 30 respectively.In another embodiment, projection 32 is formed at this through hole 18 and is positioned at the opening 20b on the back side 14.In addition, shown in Fig. 4 H, etching is carried out at the back side 14 that utilizes microetch (Micro-etching) technology will not to be provided with the chip thinning 16 of projection 32, and the electric conducting material of each through hole 18 is all exposed, and forms the cylindricality convex.At last, shown in Fig. 4 I, after microetch (Micro-etching) technology finishes, cut this chip thinning 16,, form the crystal grain 34 of a stacked structure to form independently of one another and can be engaged with each other.
Technology contents of the present invention and technical characterstic disclose as above, yet the personage who is familiar with this technology still maybe be based on instruction of the present invention and announcement and done all replacement and modifications that does not deviate from spirit of the present invention.Therefore, protection scope of the present invention should be not limited to the content that embodiment discloses, and should comprise various do not deviate from replacement of the present invention and modifications, and is contained by appending claims.
Claims (14)
1. the manufacturing approach of a semiconductor device comprises the following step:
One wafer is provided, wherein this wafer tool one active face and a back side relative with this active face;
Grind this back side of this wafer, to obtain a chip thinning;
Form a plurality of through holes on this chip thinning, wherein respectively this through hole has two openings on this back side of laying respectively at this wafer and this active face;
Form an insulating barrier in this active face of this chip thinning and the inwall of those through holes;
On this insulating barrier, form a conductive layer;
Fill up electric conducting material in those through holes with electrochemical mode;
On at least one opening of those through holes, form projection; And
Cut this chip thinning, to form crystal grain independent of each other.
2. according to the manufacturing approach of the semiconductor device of claim 1, it is characterized in that, fill up electric conducting material after the step of those through holes, comprise one and carry out the step of microetch to the electric conducting material surface of through hole with electrochemical mode.
3. according to the manufacturing approach of the semiconductor device of claim 1, it is characterized in that, fill up electric conducting material after the step of those through holes, comprise one and carry out the step of microetch to this back side of wafer with electrochemical mode.
4. according to the manufacturing approach of the semiconductor device of claim 1, it is characterized in that, on this at least one opening of those through holes, form the step of projection, those projections are these openings that are formed at this through hole on this active face of this chip thinning.
5. according to the manufacturing approach of the semiconductor device of claim 1, it is characterized in that, on this at least one opening of those through holes, form the step of projection, this projection is this opening that is formed at this through hole on this back side of this chip thinning.
6. according to the manufacturing approach of the semiconductor device of claim 1, it is characterized in that, grind the step at this back side of this wafer, comprise the following step:
Grind this back side to one predetermined thickness of this wafer, to obtain this chip thinning, wherein this predetermined thickness is between 10 microns to 200 microns.
7. according to the manufacturing approach of the semiconductor device of claim 1, it is characterized in that the step that forms a conductive layer is contained in and forms a barrier layer and a metal seed layer on this insulating barrier in regular turn.
8. the manufacturing approach of a semiconductor device comprises the following step:
One wafer is provided, wherein this wafer tool one active face and a back side relative with this active face;
Grind this back side of this wafer, to obtain a chip thinning;
Form a plurality of through holes on this chip thinning, wherein respectively this through hole has two openings on this back side of laying respectively at this wafer and this active face;
One conductive layer is set in this back side or this active face;
With electrochemical mode, fill up electric conducting material in those through holes;
Remove this conductive layer;
On at least one opening of those through holes, form projection; And
Cut this chip thinning, to form crystal grain independent of each other.
9. according to Claim 8 the manufacturing approach of semiconductor device is characterized in that fill up electric conducting material in the step of those through holes with electrochemical mode, this electric conducting material is copper or its alloy.
10. according to Claim 8 the manufacturing approach of semiconductor device is characterized in that, fills up electric conducting material after the step of those through holes with electrochemical mode, comprises one and carries out the step of microetch to the electric conducting material surface of through hole.
11. the manufacturing approach of semiconductor device according to Claim 8 is characterized in that, fills up electric conducting material after the step of those through holes with electrochemical mode, comprises one and carries out the step of microetch to this back side of wafer.
12. the manufacturing approach of semiconductor device according to Claim 8 is characterized in that, on this at least one opening of those through holes, forms the step of projection, those projections are these openings that are formed at this through hole on this active face of this chip thinning.
13. the manufacturing approach of semiconductor device according to Claim 8 is characterized in that, on this at least one opening of those through holes, forms the step of projection, this projection is this opening that is formed at this through hole on this back side of this chip thinning.
14. the manufacturing approach of semiconductor device according to Claim 8 is characterized in that, grinds the step at this back side of this wafer, comprises the following step:
Grind this back side to one predetermined thickness of this wafer, to obtain this chip thinning, wherein this predetermined thickness is between 10 microns to 200 microns.
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| CN2009101305769A CN101853804B (en) | 2009-04-03 | 2009-04-03 | Method for manufacturing semiconductor device |
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| CN2009101305769A CN101853804B (en) | 2009-04-03 | 2009-04-03 | Method for manufacturing semiconductor device |
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| TWI405303B (en) * | 2010-11-26 | 2013-08-11 | Ind Tech Res Inst | Fabricating method and testing method of semiconductor device and mechanical integrity testing apparatus |
| CN102376642A (en) * | 2011-11-24 | 2012-03-14 | 上海华力微电子有限公司 | Silicon through hole technology |
| CN102569251B (en) * | 2012-02-22 | 2014-07-02 | 华进半导体封装先导技术研发中心有限公司 | Intermetallic compound filled vertical through-hole interconnecting structure for three-dimensional package and preparation method thereof |
| WO2022241662A1 (en) * | 2021-05-19 | 2022-11-24 | 邱志威 | Fabrication method for semiconductor ultra-thin stacked structure |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6214731B1 (en) * | 1998-03-25 | 2001-04-10 | Advanced Micro Devices, Inc. | Copper metalization with improved electromigration resistance |
| CN101179037A (en) * | 2007-12-06 | 2008-05-14 | 清华大学 | High, depth and width three-dimensional uprightness interconnect and realization method of three-dimensional integrate circuit |
| CN101295653A (en) * | 2007-04-25 | 2008-10-29 | 台湾积体电路制造股份有限公司 | Manufacturing method of semiconductor element |
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6214731B1 (en) * | 1998-03-25 | 2001-04-10 | Advanced Micro Devices, Inc. | Copper metalization with improved electromigration resistance |
| CN101295653A (en) * | 2007-04-25 | 2008-10-29 | 台湾积体电路制造股份有限公司 | Manufacturing method of semiconductor element |
| CN101179037A (en) * | 2007-12-06 | 2008-05-14 | 清华大学 | High, depth and width three-dimensional uprightness interconnect and realization method of three-dimensional integrate circuit |
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