CN101853787A - Thin-film transistor and making method thereof - Google Patents
Thin-film transistor and making method thereof Download PDFInfo
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- CN101853787A CN101853787A CN 201010209943 CN201010209943A CN101853787A CN 101853787 A CN101853787 A CN 101853787A CN 201010209943 CN201010209943 CN 201010209943 CN 201010209943 A CN201010209943 A CN 201010209943A CN 101853787 A CN101853787 A CN 101853787A
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- dielectric layer
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Abstract
The invention relates to a thin-film transistor and a making method thereof. The making method comprises the following steps of: firstly providing a substrate, and sequentially forming a gate electrode and a first dielectric layer on the substrate, wherein the first dielectric layer covers the gate electrode; patterning, and removing at least a part of the first dielectric layer on the gate electrode so as to at least expose part of the gate electrode; and finally forming a second dielectric layer on the substrate, wherein the second dielectric layer covers the gate electrode. The invention can respectively control the thickness of the dielectric layer on the thin-film transistor and the thickness of the dielectric layer at the other positions of the substrate without affecting the electric performance of other components on the substrate when the thickness of a gate insulating layer is reduced to improve the thin-film transistors Ion and Ioff.
Description
Technical field
(thin-filmtransistor TFT) and preparation method thereof, refers to a kind ofly can effectively improve thin-film transistor structure of tft characteristics and preparation method thereof especially to the invention relates to a kind of thin-film transistor.
Background technology
Liquid crystal display panel of thin film transistor (thinfilmtransistorliquidcrystaldisplaypanel, TFT-LCDpanel) be to be the most widely used two-d display panel now, its mainly by plurality of groups of substrates of thin-film transistor (TFTarraysubstrate), colored optical filtering substrates (colorfiltersubstrate) and liquid crystal (liquidcrystal, LC) layer constitutes; And thin-film transistor is the usefulness as the switch module of each picture element unit (pixelunit) of control in the TFT-LCD panel.
See also Fig. 1 to Fig. 3, Fig. 1 is the partial schematic diagram for a known plurality of groups of substrates of thin-film transistor, and Fig. 2 is along a generalized section of A-A ' tangent line among Fig. 1; And Fig. 3 is a known thin-film transistor generalized section that is obtained along B-B ' tangent line among Fig. 1.As Fig. 1 and shown in Figure 2, each assembly of plurality of groups of substrates of thin-film transistor 100 such as thin-film transistor 110, data wire (dataline) 104, scan line (scanline) 106 and pixel electrode (pixelelectrode) 108 etc. are to utilize process technique such as film forming, little shadow and etching to be formed on the substrate 102, and data wire 104 is by at least one insulating barrier 114 electrical isolation with scan line 106.Generally speaking, the thickness of insulating barrier 114 be between 250～320 how rice (nanometer, nm) between.
As Fig. 1 and shown in Figure 3.Thin-film transistor 110 comprises a gate 112, and itself and scan line 106 electrically connect.Be to form insulating barrier 114 on the gate 112, as gate insulation layer; Then form semi-conductor layer 116 at least on the insulating barrier 114.Thin-film transistor 110 still comprises one source pole/drain 118, and source/drain 118 is to electrically connect with data line 104 and pixel electrode 108.
Please consult Fig. 2 and Fig. 3 again.Along with the lifting of TFT-LCD panel size and resolution, the size of pixel electrode 108 also increases thereupon, so thin-film transistor 110 must provide bigger firing current (I
On) charging ability is promoted, to avoid shortcomings such as contrast or briliancy deficiency or leakage current be higher; Thin-film transistor 110 need provide less close current (I in addition
Off) to avoid the situation of flicker (flicker).Have the knack of the personage Ying Zhi of this skill, the electrical performance of thin-film transistor 110 is closely bound up with the characteristic and the thickness of each rete.For instance, reduce insulating barrier 114 thickness and can reach the I that strengthens thin-film transistor 110
OnWith I
OffCharacteristic; But the reduction of insulating barrier 114 thickness makes the impurity electric capacity (parasiticcapacitor) between other assembly such as data wire 104 and the scan line 106 increase simultaneously thereupon, (RCdelay) effect that has a resistance-capacitance delays, even cause the image signal distortion.In addition, in the existing film forming processing procedure, still can't distinguish control TFT 110 places and plurality of groups of substrates of thin-film transistor 100 all the other required insulating barrier 114 thickness everywhere.
Summary of the invention
In view of this, the purpose of this invention is to provide a kind of all the other thickness of insulating layer everywhere of control TFT place and plurality of groups of substrates of thin-film transistor of distinguishing, to reach the I that improves thin-film transistor
OnWith I
OffCharacteristic, and do not increase the manufacture method of the thin-film transistor of impurity electric capacity.
According to claim provided by the present invention, provide a kind of manufacture method of thin-film transistor, the manufacture method of this thin-film transistor at first provides a substrate, next form a gate electrode and one first dielectric layer in regular turn on substrate, and this first dielectric layer covers this gate electrode.Next carry out a patterning step, remove on this gate electrode to this first dielectric layer of small part, and expose at least the part this gate electrode.On this substrate, form one second dielectric layer at last, and this second dielectric layer is to cover this gate electrode.
According to claim provided by the present invention, other provides a kind of thin-film transistor, this thin-film transistor includes a substrate, and is formed at gate electrode, on this substrate and is formed at first dielectric layer on this gate electrode and this substrate, and this first dielectric layer includes an opening, in order to expose this gate electrode of part at least.This thin-film transistor more includes one second dielectric layer, and this second dielectric layer is this gate electrode and this first dielectric layer that covers in this opening.This thin-film transistor more includes a semiconductor pattern that is formed on this second dielectric layer of this gate electrode top in addition, and a source/drain that is formed on this semiconductor pattern.
According to the manufacture method of thin-film transistor provided by the present invention, only there is this second dielectric layer this gate electrode top, in order to as gate insulation layer; Other place then still comprises this first dielectric layer and this second dielectric layer on this substrate.That is to say, according to manufacture method provided by the present invention, be the medium thickness that can distinguish other place on the medium thickness at control TFT place and the substrate, so can be in reducing gate insulation layer thickness to improve thin-film transistor I
OnWith I
OffThe time, do not have influence on the electrical performance of other assembly on this substrate.
Description of drawings
Fig. 1 is a partial schematic diagram of a known plurality of groups of substrates of thin-film transistor;
Fig. 2 is along a generalized section of A-A ' tangent line among Fig. 1;
Fig. 3 is a known thin-film transistor generalized section that is obtained along B-B ' tangent line among Fig. 1;
Fig. 4 to Fig. 9 is the schematic flow sheet of a preferred embodiment of the manufacture method of thin-film transistor provided by the present invention, wherein Fig. 4 is the partial schematic diagram for a plurality of groups of substrates of thin-film transistor that preferred embodiment provided, and Fig. 5 to Fig. 9 is thin film transistor region profile and the non-thin film transistor region profile that obtains along C-C ' tangent line and D-D ' tangent line among Fig. 4.
[primary clustering symbol description]
100 plurality of groups of substrates of thin-film transistor, 102 substrates
104 data lines, 106 scan lines
108 pixel electrodes, 110 thin-film transistors
112 gates, 114 insulating barriers
116 semiconductor layers, 118 source/drain
200 substrates, 202 thin film transistor regions
204 non-thin film transistor region 212 gate electrodes
214 scan lines, 220 first dielectric layers
222 patterning photoresistances, 224 openings
230 second dielectric layers, 240 semiconductor patterns
242 semiconductor layers, 244 heavily doped semiconductor layers
250 source/drain, 252 data lines
260 thin-film transistors, 300 light shields
A-A ', B-B ', C-C ', D-D ' tangent line.
Embodiment
In the middle of specification and follow-up claim, used some vocabulary to censure specific assembly.The person with usual knowledge in their respective areas should understand, and same assembly may be called with different nouns by manufacturer.This specification and follow-up claim are not used as distinguishing the mode of assembly with the difference of title, but the benchmark that is used as distinguishing with the difference of assembly on function.Be to be an open term mentioned " comprising " in the middle of specification and the follow-up request item in the whole text, so should be construed to " comprise but be not limited to ".In addition, " electric connection " speech is to comprise any indirect means that are electrically connected that directly reach at this.Therefore, be electrically connected at one second device, then represent this first device can be directly connected in this second device, or be connected to this second device indirectly through other device or connection means if describe one first device in the literary composition.
See also Fig. 4 to Fig. 9, Fig. 4 to Fig. 9 is the schematic flow sheet of a preferred embodiment of the manufacture method of thin-film transistor provided by the present invention, wherein Fig. 4 is the partial schematic diagram for a plurality of groups of substrates of thin-film transistor that preferred embodiment provided, and Fig. 5 to Fig. 9 is thin film transistor region profile and the non-thin film transistor region profile that obtains along C-C ' tangent line and D-D ' tangent line among Fig. 4.As Fig. 4 and shown in Figure 5, this preferred embodiment at first provides a substrate 200, and a glass substrate for example is in order to the substrate as the thin-film transistor array.And on the substrate 200 definable one thin film transistor region 202 and a non-thin film transistor region 204.Next form a first metal layer on substrate 200, it can comprise aluminium (Al), copper (Cu), tungsten (W), chromium (Cr), tantalum (Ta), titanium (Ti), molybdenum metal or its alloys such as (Mo), and the first metal layer can be single layer structure or lamination layer structure.Be the patterning the first metal layer afterwards, and form a gate electrode 212 in the thin film transistor region 202 on substrate 200; And when forming gate electrode 212, more can form one scan line 214 in the non-thin film transistor region 204 on substrate 200.
Please continue to consult Fig. 5.Next, on substrate 200, form one first dielectric layer, 220, the first dielectric layers 220 comprehensively and can comprise dielectric materials such as silica, silicon nitride or silicon oxynitride, but be not limited thereto; And the thickness of first dielectric layer 220 is between 100～170nm in this preferred embodiment, but not as limit.As shown in Figure 5, first dielectric layer 220 is to cover gate electrode 212 and scan line 214.After forming first dielectric layer 220, be to carry out a patterning step.Patterning step at first forms a photoresistance on first dielectric layer 220, and exposes by a light shield 300; Subsequently by a developing manufacture process, an ashing (ashing) processing procedure for example, with oxygen or carbon-fluorine is that reacting gas source forms electricity slurry and removes the part photoresistance, forms a patterning photoresistance 222, and wherein patterning photoresistance 222 exposes first dielectric layer 220 of part corresponding to gate electrode 212 at least.
See also Fig. 6 and Fig. 7.Carry out an etch process afterwards, see through patterning photoresistance 222 and remove the part of first dielectric layer 220 on the gate electrode 212 in the thin film transistor region 202, and form an opening 224, and gate electrode 212 is to be exposed in the opening 224, removes patterning photoresistance 222 subsequently.Next shown in the 7th figure, on substrate 200, form one second dielectric layer 230, and second dielectric layer 230 is to insert in the opening 224 more comprehensively, and covers gate electrode 212.The thickness of second dielectric layer 230 is the thickness that can be lower than known gate insulation layer, as is lower than 250nm; As in this preferred embodiment, the thickness of second dielectric layer 230 is between 150～200nm, but not as limit.Second dielectric layer 230 is to comprise dielectric materials such as silica, silicon nitride or silicon oxynitride, but not as limit, and second dielectric layer 230 can comprise identical or different dielectric material with first dielectric layer 220.As shown in Figure 7, the dielectric material of gate electrode 212 tops only has second dielectric layer 230 in the thin film transistor region 202, and place beyond the gate electrode 212 in the thin film transistor region 202 and the dielectric material in the non-thin film transistor region 204 have then comprised first dielectric layer 220 and second dielectric layer 230.
See also Fig. 8.Subsequently, be on second dielectric layer 230 of gate electrode 212 tops, to form semiconductor pattern 240; Semiconductor pattern 240 can comprise semi-conductor layer 242 and a heavy doping (heavilydoped) semiconductor layer 244, but not as limit.Semiconductor layer 242 is the usefulness as the channel layer of thin-film transistor, and its material can comprise an amorphous silicon (amorphoussilicon) layer; And heavily doped semiconductor layer 244 is the usefulness as ohmic contact layer, and its material can be a doped amorphous silicon (dopedamorphoussilicon) layer, in order to the contact impedance between the metal material that reduces semiconductor layer 242 and follow-up formation.It should be noted that in addition in thin film transistor region 202, semiconductor pattern 240 only is formed at the top of gate electrode 212, but in non-thin film transistor region in 204, then visual electrical requirement removes semiconductor layer 242 and/or heavily doped semiconductor layer 244; Or can keep semiconductor layer 242 and heavily doped semiconductor layer 244 in the non-thin film transistor region 204 as shown in Figure 8.
See also Fig. 9.Afterwards, be on substrate 200, to form one second metal level, second metal level also can comprise metal or its alloys such as Al, Cu, W, Cr, Ta, Ti, Mo, and second metal level can be single layer structure or lamination layer structure.Be patterning second metal level afterwards, and form one source pole/drain 250 in the thin film transistor region 202 on substrate 200, finish the making of thin-film transistor 260.In addition, when forming source/drain 250, also can form a data line 252 in the non-thin film transistor region 204 on substrate 200.It should be noted that the scan line 214 in the noncrystal area under control 204 is by first dielectric layer 220 and second dielectric layer, 230 electrical isolation with data wire 252.
Hence one can see that, and the present invention provides a kind of thin-film transistor 260, and thin-film transistor 260 includes a substrate 200, and is formed at gate electrode 212, on the substrate 200 and is formed at first dielectric layer 220 on gate electrode 212 and the substrate 200.It should be noted that first dielectric layer 220 includes an opening 224, in order to expose part gate electrode 212 at least.It is gate electrode 212 and first dielectric layers 220 that cover in the opening 224 that thin-film transistor 260 more includes one second dielectric layer, 230, the second dielectric layers 230.In addition, thin-film transistor 260 still comprises a semiconductor pattern 240 that is formed on second dielectric layer 230 of gate electrode 212 tops, and a source/drain 250 that is formed on the semiconductor pattern 240.
According to thin-film transistor provided by the present invention and preparation method thereof, be to remove part of first dielectric layer 220 on the gate electrode 212 in the thin film transistor region 202 by patterning step, on substrate 200, form second dielectric layer 230 again.Therefore, only there is second dielectric layer 230 of thickness far below known gate insulation layer gate electrode 212 tops, so can improve the I of thin-film transistor 260
OnAnd the I that reduces thin-film transistor 260
OffAnd other is located as part beyond the gate electrode in the thin film transistor region 202 212 on the substrate 200, with then still comprise first dielectric layer 220 and second dielectric layer 230 in the non-thin film transistor region 204, and the thickness of first dielectric layer 220 and second dielectric layer 230 adds up more and can postpone and can effectively reduce impurity electric capacity and improve RC greater than the thickness of known gate insulation layer.
In sum, according to manufacture method provided by the present invention, be the medium thickness that to distinguish other place on the medium thickness at control TFT place and the substrate, so can be in reducing gate insulation layer thickness to improve thin-film transistor I
OnWith I
OffDuring characteristic, do not have influence on the electrical performance of other assembly on the substrate.
The above only is preferred embodiment of the present invention, and all equalizations of being done according to the present patent application claim change and modify, and all should belong to covering scope of the present invention.
Claims (10)
1. the manufacture method of a thin-film transistor is characterized in that comprising:
One substrate is provided;
On this substrate, form a gate electrode;
On this substrate and this gate electrode, form one first dielectric layer;
Carry out a patterning step, remove on this gate electrode to this first dielectric layer of small part, and expose at least the part this gate electrode; And
On this substrate, form one second dielectric layer, and this second dielectric layer is to cover this gate electrode.
2. the manufacture method of thin-film transistor according to claim 1 is characterized in that: a thickness of described first dielectric layer is between 100～170 how between the rice.
3. the manufacture method of thin-film transistor according to claim 1 is characterized in that: a thickness of described second dielectric layer is between 150～200 how between the rice.
4. the manufacture method of thin-film transistor according to claim 1 is characterized in that: also comprise one and form the step of semiconductor pattern at least on this second dielectric layer of this gate electrode top.
5. the manufacture method of thin-film transistor according to claim 4 is characterized in that: the step that also comprises a formation one source pole/drain.
6. the manufacture method of thin-film transistor according to claim 5 is characterized in that also comprising:
On this substrate, form one scan line at least, form simultaneously with this gate electrode; And
On this substrate, form at least one data wire, form simultaneously with this source/drain.
7. the manufacture method of thin-film transistor according to claim 6, it is characterized in that: wherein this data wire and this scan line are by this first dielectric layer and this second dielectric layer electrical isolation.
8. thin-film transistor is characterized in that comprising:
One substrate;
One gate electrode is formed on this substrate;
One first dielectric layer is formed on this gate electrode and this substrate, and this first dielectric layer includes an opening, in order to expose this gate electrode of part at least;
One second dielectric layer, this second dielectric layer are this gate electrode and this first dielectric layers that covers in this opening;
The semiconductor pattern is formed on this second dielectric layer of this gate electrode top; And
One source pole/drain is formed on this semiconductor pattern.
9. thin-film transistor according to claim 8 is characterized in that: wherein this thickness of this first dielectric layer is between 100～170 how between the rice.
10. thin-film transistor according to claim 8 is characterized in that: wherein this thickness of this second dielectric layer is between 150～200 how between the rice.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201010209943 CN101853787A (en) | 2010-06-26 | 2010-06-26 | Thin-film transistor and making method thereof |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201010209943 CN101853787A (en) | 2010-06-26 | 2010-06-26 | Thin-film transistor and making method thereof |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104465516A (en) * | 2014-12-05 | 2015-03-25 | 京东方科技集团股份有限公司 | Manufacturing method of array substrate, array substrate and display device |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5828082A (en) * | 1992-04-29 | 1998-10-27 | Industrial Technology Research Institute | Thin film transistor having dual insulation layer with a window above gate electrode |
| US20100001277A1 (en) * | 2008-07-07 | 2010-01-07 | Samsung Electronics Co., Ltd. | Thin film transistor array and method of manufacturing the same |
-
2010
- 2010-06-26 CN CN 201010209943 patent/CN101853787A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5828082A (en) * | 1992-04-29 | 1998-10-27 | Industrial Technology Research Institute | Thin film transistor having dual insulation layer with a window above gate electrode |
| US20100001277A1 (en) * | 2008-07-07 | 2010-01-07 | Samsung Electronics Co., Ltd. | Thin film transistor array and method of manufacturing the same |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104465516A (en) * | 2014-12-05 | 2015-03-25 | 京东方科技集团股份有限公司 | Manufacturing method of array substrate, array substrate and display device |
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Application publication date: 20101006 |