CN101848392A - Video encoding and decoding device and integer transform and inverse transform method thereof - Google Patents

Video encoding and decoding device and integer transform and inverse transform method thereof Download PDF

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CN101848392A
CN101848392A CN 201010172984 CN201010172984A CN101848392A CN 101848392 A CN101848392 A CN 101848392A CN 201010172984 CN201010172984 CN 201010172984 CN 201010172984 A CN201010172984 A CN 201010172984A CN 101848392 A CN101848392 A CN 101848392A
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data
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transform
integer transform
inverse transformation
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陈烽
王新安
胡子一
安辉耀
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Peking University Shenzhen Graduate School
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Peking University Shenzhen Graduate School
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Abstract

The invention relates to a video encoding and decoding device, which comprises an integer transform and inverse transform realization device which comprises a combined computing unit, a storage transposition unit and a controller for controlling the combined computing unit and the storage transposition unit to perform coordinating operation, wherein the combined computing unit and the storage transposition unit are connected and exchange data; the combined computing unit comprises a matrix multiplication unit and a data processing unit which are connected and exchange data; and the matrix multiplication unit is used for the matrix operation of three basic symmetric matrixes. In the method, the two different matrix operations of (8*8)*(8*1) in the integer transform and inverse transform are cracked into two uniform matrix operations of (2*2)*(2*1) and a matrix operation of (4*4)*(4*1), so a multiplication operation is reduced by 67.5 percent, an addition (subtraction) operation is reduced by 50 percent, both integer transform and inverse transform can be realized, hardware sources are saved, and great generality and expandability are achieved.

Description

The method of a kind of video encoding/decoding apparatus and integer transform thereof and inverse transformation
Technical field the present invention relates to the coding and decoding video field, particularly is applied to the method for a kind of video encoding/decoding apparatus and integer transform and the integral inverse transform of AVS.
Background technology AVS (Advanced Video coding Standard) is the autonomous digital audio/video encoding and decoding technique standard that China's digital audio/video encoding and decoding technique standard operation group (being called for short AVS working group) proposes, its code efficiency has improved 2~3 times than MPEG-2 international standard, and with H.264 suitable, but encoding scheme is more succinct, has represented the advanced level of second generation audio/video encoding/decoding technology.AVS is a national standard by Ministry of Information Industry's official approval at the beginning of 2006, in Digital Television, the high definition optic disk, in this upcoming industry spring tide of Streaming Media and multimedia communication, the AVS standard provides rare opportunity for China makes up relevant industry chain (supply chain).
The important techniques feature of AVS has adopted 8 * 8 integer transform exactly, the mismatch problems that has adopted the floating-point dct transform to bring in numerous standards before having avoided.
The expression formula of AVS integer transform is:
Y = HXH T = 8 8 8 8 8 8 8 8 10 9 6 2 - 2 - 6 - 9 - 10 10 4 - 4 - 10 - 10 - 4 4 10 9 - 2 - 10 - 6 6 10 2 - 9 8 - 8 - 8 8 8 - 8 - 8 8 6 - 10 2 9 - 9 - 2 10 - 6 4 - 10 10 - 4 - 4 10 - 10 4 2 - 6 9 - 10 10 - 9 6 - 2 ( X ) 8 10 10 9 8 6 4 2 8 9 4 - 2 - 8 - 10 - 10 - 6 8 6 - 4 - 10 - 8 2 10 9 8 2 - 10 - 6 8 9 - 4 - 10 8 - 2 - 10 6 8 - 9 - 4 10 8 - 6 - 4 10 - 8 - 2 10 - 9 8 - 6 4 2 - 8 10 - 10 6 8 - 10 10 - 9 8 - 6 4 - 2
The transformation matrix of integral inverse transform and transposed matrix thereof are:
T = 8 10 10 9 8 6 4 2 8 9 4 - 2 - 8 - 10 - 10 - 6 8 6 - 4 - 10 - 8 2 10 9 9 2 - 10 - 6 8 9 - 4 - 10 8 - 2 - 10 6 8 - 9 - 4 10 6 - 6 - 4 10 - 8 - 2 10 - 9 8 - 9 4 2 - 8 10 - 10 6 8 - 10 10 - 9 8 - 9 4 - 2 T T = 8 8 8 8 8 8 8 8 10 9 6 2 - 2 - 6 - 9 - 10 10 4 - 4 - 10 - 10 - 4 4 10 9 - 2 - 10 - 6 - 6 10 2 - 9 8 - 8 - 8 8 8 - 8 - 8 8 6 - 10 2 9 - 9 - 2 10 - 6 4 - 10 10 - 4 - 4 10 - 10 4 2 - 6 9 - 10 10 - 9 6 - 2
In the integral inverse transform process, establishing transform coefficient matrix is Y, and the step that obtains residual error sample value matrix X after the inverse transformation is as follows:
The first step: transform coefficient matrix is horizontal inverse transformation: Z`=YT T, wherein, T TBe the transposed matrix of inverse transformation matrix T, Z` represents the intermediate object program of horizontal inverse transformation.
Second step: matrix Z " in element z " IjBe calculated as follows:
z″ ij=(clip3(-2 15,2 15-1,(z′ ij+4)))>>3 i,j=0~7。
The 3rd step: to matrix Z " do vertical inverse transformation: Z=T Z ", Z represents 8 * 8 matrixes after the inverse transformation.
The 4th step: the element of residual error sample value matrix X is calculated as follows:
x ij=(clip3(-2 15,2 15-1,(z ij+2 6)))>>7,i,j=0~7
Z wherein IjBe the element among the matrix Z.
In the hardware of AVS coding is realized, integer transform and the inverse transformation of research AVS, in the hope of using less hardware resource, realize conversion short operation time, and make the hardware implement device have good versatility and extensibility, is significant undoubtedly.
In list of references, people such as Wang Leirui study integer transform and the inverse transformation of AVS, have proposed some valuable thoughts.But its matrix properties analysis to AVS integer transform and inverse transformation is not thorough, and the hardware unit that causes its design still is not optimum.
Summary of the invention technical problem to be solved by this invention is to be used for a kind of video encoding/decoding apparatus of AVS and the method for integer transform and inverse transformation thereof, reduce hard-wired complexity on the one hand, the economize on hardware resource can realize integer transform and inverse transformation on the other hand on same set of hardware unit.
The invention discloses a kind of video encoding/decoding apparatus, comprise the implement device of integer transform and inverse transformation; The implement device of described integer transform and inverse transformation comprises combinatorial operation unit and the storage transposition unit that interconnects swap data, and the controller of controlling described combinatorial operation unit and the unit co-ordination of storage transposition; Described combinatorial operation unit comprises matrix multiplication unit and the data processing unit that interconnects swap data;
Described matrix multiplication unit comprises the arithmetic element of the matrix operation that realizes following three kinds of basic symmetrical matrixes respectively:
O 0 = 8 1 1 1 - 1 ;
O 1 = 2 5 2 2 - 5 ;
E = 10 9 6 2 9 - 2 - 10 - 6 6 - 10 2 9 2 - 6 9 10 ;
Described data processing unit is used for realizing at integer transform the preliminary treatment of input data, realizes the reprocessing of transform data in integral inverse transform, and the result of single step conversion is carried out clamped and shift operation;
Described transposition memory cell be used to deposit with output transform after data, and as required the input data are carried out transposition.
Video encoding/decoding apparatus disclosed by the invention also comprises following subordinate technical characterictic:
The implement device of described integer transform and inverse transformation comprises n group combinatorial operation unit, can carry out the integer transform and the inverse transformation of n group input data simultaneously; Described n group input data are imported corresponding n group combinatorial operation unit respectively, handle through importing described transposition memory cell after the computing again, and then the corresponding n group combinatorial operation unit of input carry out computing; Parameter n is a natural number.
The implement device of described integer transform and inverse transformation comprises prime n group combinatorial operation unit and level n group combinatorial operation unit, back, can carry out the integer transform and the inverse transformation of n group input data simultaneously; Described n group input data are imported corresponding described prime n group combinatorial operation unit respectively and are carried out computing, import described transposition memory cell again and handle, and then the corresponding level n group combinatorial operation unit, described back of input continues computing.
The control signal that described controller is controlled described combinatorial operation unit and the unit co-ordination of storage transposition comprises:
Trans_en, value 0 or 1, the implement device that is respectively applied for described integer transform of sign and inverse transformation is in does not work or operating state;
Trans_st, value 0 or 1, what be respectively applied for that the implement device of sign described integer transform and inverse transformation carries out is integer direct transform or integral inverse transform.
Trans_time, value 0 or 1, what be respectively applied for that the implement device of sign described integer transform and inverse transformation carries out is the conversion of single step for the first time, the still conversion of single step for the second time; And when control signal Trans_en became 1 by 0, the value of Trans_time was changed to 0.
The control signal that described storage transposition unit uses comprises row_en, col_en, and full:
Work as row_en=0, during col_en=1, handled data deposit in by row, read by row;
Work as row_en=1, during col_en=0, handled data deposit in by row, read by row; When full=1, the data in the described storage transposition unit are full, and the value of described control signal Trans_time becomes 1 by 0, carries out the single step conversion second time.
Described parameter n is 8 factor 1,2,4,8.
Described transposition memory cell is 8 * 8 register array.
The invention also discloses a kind of integer transform of video encoding/decoding apparatus and the method for inverse transformation, described integer transform carries out the matrix operation of twice three kinds of basic symmetrical matrixes respectively with inverse transformation in the identical matrix multiplication unit of structure; Described three kinds of basic symmetrical matrixes are:
O 0 = 8 1 1 1 - 1 ;
O 1 = 2 5 2 2 - 5 ;
E = 10 9 6 2 9 - 2 - 10 - 6 6 - 10 2 9 2 - 6 9 10 .
The method of integer transform disclosed by the invention and inverse transformation also comprises following subordinate technical characterictic:
The method of described integer transform comprises the steps:
If the data of input are p0, p1, p2 ... .p7, the data of output are q0, q1, and q2 ... ..q7, intermediate variable is r0, r1, and r2 ... .r7; The value of single step conversion register Trans_time is 0 or 1, and initial value is 1;
The first step, the value of step conversion register Trans_time adds 1; Data p0, p1, p2 ... .p7 import data processing unit and carry out preliminary treatment, obtain data r0, r1, r2 ... r7; Comprise:
r0=((p0+p7)+(p3+p4)),
r4=((p1+p6)+(p2+p5)),
r2=((p0+p7)-(p3+p4)),
r6=((p1+p6)-(p2+p5)),
r1=(p0-p7),
r3=(p1-p6),
r5=(p2-p5),
r7=(p3-p4).
Second step, data r0, r1, r2 ... r7 input matrix multiplication unit carries out the matrix operation of three basic symmetrical matrixes, to the data r0 that obtains after the preliminary treatment, and r1, r2 ... r7 carries out conversion:
q 0 q 4 = 8 1 1 1 - 1 r 0 r 4
q 2 q 6 = 2 5 2 2 - 5 r 2 r 6
q 1 q 3 q 5 q 7 = 10 9 6 2 9 - 2 - 10 - 6 6 - 10 2 9 2 - 6 9 10 r 1 r 3 r 5 r 7
The 3rd step, above-mentioned data q0, q1, q2 ... ..q7 the transposition unit is stored in input; When single step conversion register Trans_time=0, data q0, q1, q2 ... ..q7 by behind the transposition as new input data q0, q1, q2 ... ..q7, get back to the first step; When single step conversion register Trans_time=1, data q0, q1, q2 ... ..q7 the result as integer transform directly exports.
The method of described integral inverse transform comprises the steps:
If the data of input are p0, p1, p2 ... .p7, the data of output are q0, q1, and q2 ... ..q7, intermediate variable is r0, r1, and r2 ... .r7 and Tq0, Tq1, Tq2 ... ..Tq7; The value of single step conversion register Trans_time is 0 or 1, and initial value is 1;
Steps A, the value of single step conversion register Trans_time adds 1; Data p0, p1, p2 ..., p7 input matrix multiplication unit carries out the matrix operation of three basic symmetrical matrixes, obtains intermediate variable data r0, r1, r2 ... .r7:
r 0 r 4 = 8 1 1 1 - 1 p 0 p 4
r 2 r 6 = 2 5 2 2 - 5 p 2 p 6
r 1 r 3 r 5 r 7 = 10 9 6 2 9 - 2 - 10 - 6 6 - 10 2 9 2 - 6 9 10 p 1 p 3 p 5 p 7
Step B: above-mentioned data r0, r1, r2 ... .r7 import data processing unit and carry out reprocessing:
Tq0=(r0+r2)+r1,
Tq1=(r4+r6)+r3,
Tq2=(r4-r6)+r5,
Tq3=(r0-r2)+r7,
Tq4=(r0-r2)-r7,
Tq5=(r4-r6)-r5,
Tq6=(r4+r6)-r3,
Tq7=(r0+r2)-r1;
Step C: when single step conversion register Trans_time=0, then dateout is:
qi=(clip3(-215,215,(Tqi+4)))>>3;
And the data q0 that obtains, q1, q2 ... ..q7 as new input data p0, p1, p2 ... .p7, get back to
Steps A;
When single step conversion register Trans_time=1, then conversion dateout is:
qi=(clip3(-215,215,(Tqi+64)))>>7。
The method of a kind of video encoding/decoding apparatus disclosed by the invention and integer transform and inverse transformation, because the matrix operation of one (8 * 8) * (8 * 1) is cracked into the matrix operation of two (2 * 2) * (2 * 1) and the matrix operation and (subtracting) the method computing of some adding of one (4 * 4) * (4 * 1), make multiplying reduce 67.5%, add the computing of (subtracting) method and reduced 50%, and because the constant coefficient multiplying can realize by using displacement and add operation, reduce amount of calculation greatly, saved hardware resource.And, owing in the single step conversion, there is a large amount of conjugate operation form (a+b) that can calculate simultaneously and (a-b), reduce operation time greatly.Further, because the matrix operation in integer transform and the inverse transformation replaces with the matrix operation of three identical symmetrical matrixes, one cover hardware implement device both can be realized integer transform, can realize integral inverse transform again, therefore had great versatility and extensibility.
Description of drawings
Fig. 1 is the hardware unit block diagram that the parallel mode of AVS of the present invention realizes integer transform and inverse transformation.
Fig. 2 is the hardware unit block diagram that the parallel and pipeline mode of AVS of the present invention is realized integer transform and inverse transformation.
Fig. 3 is the data flow diagram in the AVS integer transform of the present invention.
Fig. 4 is the data flow diagram in the AVS integral inverse transform of the present invention.
Fig. 5 is an integer transform flow chart of the present invention.
Fig. 6 is an integral inverse transform flow chart of the present invention.
Embodiment is described in further detail the present invention below in conjunction with the drawings and specific embodiments.
Because it is the matrix of 3 symmetries that the matrix of integer transform and inverse transformation can be cleaved into, so the matrix multiplication in integer transform and the inverse transformation can utilize the matrix of these three symmetries to finish conversion.
In the direct transform of AVS integer, Y=HXH T=[H (HX) T] T=[(XH T) TH T] T, so the integer direct transform can be called 2 fundamental matrix multiplication W=HX or W=XH TCan finish, and when calling basic matrix multiplication for the second time, need carry out transposition the result of the fundamental matrix multiplying first time.
In the integral inverse transform process, if represent vertical conversion Z=T Z "=(Z " TT T) T, matrix multiplication operation and the horizontal inverse transformation Z`=YT before the transposition then THas identical form; If use W=ZT T, then can represent the matrix multiplication of vertical inverse transformation.
In integer transform and inverse transformation, inverse transformation adopts the step of the vertical again conversion of first horizontal transformation according to the requirement of AVS standard, and the earlier vertical conversion step of horizontal transformation is again adopted in direct transform, because the matrix of integer transform and inverse transformation transposed matrix, i.e. H=T each other T(H and T be transposition each other), in fact has only the computing of two kinds of basic single step conversion, after integer transform and inverse transformation can be carried out once basic single step conversion, the result is carried out behind the transposition (inverse transformation also needed to carry out necessary displacement and rounds operation before transposition) call the single step conversion once more and can finish conversion.
If the data of input are p0, p1, p2 ... .p7, the data of exporting after the basic single step conversion are q0, q1, and q2 ... ..q7.
If basic single step is transformed to the premultiplication matrix H, then:
q 0 q 1 q 2 q 3 q 4 q 5 q 6 q 7 = 8 8 8 8 8 8 8 8 10 9 6 2 - 2 - 6 - 6 - 10 10 4 - 4 - 10 - 10 - 4 4 10 9 - 2 - 10 - 6 6 10 2 - 9 8 - 8 - 8 8 8 - 8 - 8 8 6 - 10 2 9 - 9 - 2 10 - 6 4 - 10 10 - 4 - 4 10 - 10 4 2 - 6 9 - 10 10 - 9 6 - 2 p 0 p 1 p 2 p 3 p 4 p 5 p 6 p 7 ,
According to the character of matrix, can release:
q 0 q 4 = 8 1 1 1 - 1 ( p 0 + P 7 ) + ( p 3 + p 4 ) ( p 1 + p 6 ) + ( p 2 + p 5 )
q 2 q 6 = 2 5 2 2 - 5 ( p 0 + P 7 ) - ( p 3 + p 4 ) ( p 1 + p 6 ) - ( p 2 + p 5 )
q 1 q 3 q 5 q 7 = 10 9 6 2 9 - 2 - 10 - 6 6 - 10 2 9 2 - 6 9 10 p 0 - p 7 p 1 - p 6 p 2 - p 5 p 3 - p 4
If basic single step conversion is the premultiplication matrix T, then:
q 0 q 1 q 2 q 3 q 4 q 5 q 6 q 7 = 8 10 10 9 8 6 4 2 8 9 4 - 2 - 8 - 10 - 10 - 6 8 6 - 4 - 10 - 8 2 10 9 8 2 - 10 - 6 8 9 - 4 - 10 8 - 2 - 10 6 8 - 9 - 4 10 8 - 6 - 4 10 - 8 - 2 10 - 9 8 - 9 4 2 - 8 10 - 10 6 8 - 10 10 - 9 8 - 6 4 - 2 p 0 p 1 p 2 p 3 p 4 p 5 p 6 p 7
Note:
r 0 r 4 = 8 1 1 1 - 1 p 0 p 4
r 2 r 6 = 2 5 2 2 - 5 p 2 p 6
r 1 r 3 r 5 r 7 = 10 9 6 2 9 - 2 - 10 - 6 6 - 10 2 9 2 - 6 9 10 p 1 p 3 p 5 p 7
Then:
q 0 q 1 q 2 q 3 q 4 q 5 q 6 q 7 = ( r 0 + r 2 ) + r 1 ( r 4 + r 6 ) + r 3 ( r 4 - r 6 ) + r 5 ( r 0 - r 2 ) + r 7 ( r 0 - r 2 ) - r 7 ( r 4 - r 6 ) - r 5 ( r 4 + r 6 ) - r 3 ( r 0 + r 2 ) - r 1
Therefore the matrix operation of basic single step conversion can be cracked into three basic symmetrical matrix O 0, O 1, the matrix operation of E.Wherein:
O 0 = 8 1 1 1 - 1
O 1 = 2 5 2 2 - 5
E = 10 9 6 2 9 - 2 - 10 - 6 6 - 10 2 9 2 - 6 9 10
Because the matrix multiplication of one (8 * 8) * (8 * 1) is replaced by the matrix multiplication of the matrix multiplication of two (2 * 2) * (2 * 1) and one (4 * 4) * (4 * 1), the multiplication number of times reduces to 24 times by 64 times, the addition number of times is reduced to 28 times by 56 times, has reduced operand greatly.
In integer transform, integer transform can call twice single step conversion and finish.
The step of the single step conversion of integer transform comprises following two steps:
Step 2a: transform data preliminary treatment.
If the input data are p0, p1, p2 ... .p7, obtaining data after the preliminary treatment is r0, r1, and r2, r3, r4, r5, r6, r7, then:
r0=((p0+p7)+(p3+p4)),
r4=((p1+p6)+(p2+p5)),
r2=((p0+p7)-(p3+p4)),
r6=((p1+p6)-(p2+p5)),
r1=(p0-p7),
r3=(p1-p6),
r5=(p2-p5),
r7=(p3-p4).
Wherein, r0 and r2, r4 and r6 can calculate simultaneously because equation the right has only the difference of sign.
Step 2b: data conversion.
Utilize three fundamental matrixs, the data that obtain after the preliminary treatment carried out conversion:
q 0 q 4 = 8 1 1 1 - 1 r 0 r 4
q 2 q 6 = 2 5 2 2 - 5 r 2 r 6
q 1 q 3 q 5 q 7 = 10 9 6 2 9 - 2 - 10 - 6 6 - 10 2 9 2 - 6 9 10 r 1 r 3 r 5 r 7
The result who obtains the single step conversion is:
q0=3<<(r0+r4),
q4=3<<(r0-r4),
q2=1<<(5r2+2r6),
q6=1<<(2r2-5r6),
q1=10r1+9r3+6r5+2r7,
q3=9r1-2r3-10r5-6r7,
q5=6r1-10r3+2r5+9r7,
q7=2r1-6r3+9r5-10r7.
Wherein: the constant coefficient multiplication adopts addition and displacement to realize, as 5r0=r0+2<<r0.
Above-mentioned single step conversion need be imported 8 data at every turn.After 64 data of total of input are all finished the single step conversion, the result is made transposition, the transposition data repeat above-mentioned steps and finish integer transform as new input data.
In integral inverse transform, can call twice single step conversion and finish integral inverse transform.
The single step conversion of integral inverse transform comprises following three steps:
Step 3a: data conversion.
If the input data are p0, p1, p2 ... .p7, utilize three fundamental matrix calculated datas to obtain intermediate object program r0, r1, r2 earlier ... .r7 be:
r 0 r 4 = 8 1 1 1 - 1 p 0 p 4
r 2 r 6 = 2 5 2 2 - 5 p 2 p 6
r 1 r 3 r 5 r 7 = 10 9 6 2 9 - 2 - 10 - 6 6 - 10 2 9 2 - 6 9 10 p 1 p 3 p 5 p 7
The result who obtains the single step conversion is:
r0=3<<(p0+p4),
r4=3<<(p0-p4),
r2=1<<(5p2+2p6),
r6=1<<(2p2-5p6),
r1=10p1+9p3+6p5+2p7,
r3=9p1-2p3-10p5-6p7,
r5=6p1-10p3+2p5+9p7,
r7=2p1-6p3+9p5-10p7.
Wherein: the constant coefficient multiplication adopts addition and displacement to realize, as 5p0=p0+2<<p0.
Step 3b: transform data reprocessing.
Simple calculating can be expressed as:
Tq0=(r0+r2)+r1,
Tq1=(r4+r6)+r3,
Tq2=(r4-r6)+r5,
Tq3=(r0-r2)+r7,
Tq4=(r0-r2)-r7,
Tq5=(r4-r6)-r5,
Tq6=(r4+r6)-r3,
Tq7=(r0+r2)-r1。
Step 3c: if the conversion of single step for the first time, then dateout is:
qi=(clip3(-215,215,(Tqi+4)))>>3;
If the conversion of single step for the second time, then conversion dateout is:
qi=(clip3(-215,215,(Tqi+64)))>>7。
As from the foregoing, the required computing of the process of integer transform and inverse transformation is basic identical.
The hardware implement device of the integer transform of above-mentioned AVS and inverse transformation comprises matrix multiplication unit, data processing unit, storage transposition unit, controller.
Matrix multiplication unit: realize premultiplication matrix O 0, O 1Matrix multiplication operation with E.
Data processing unit: the transform data preliminary treatment of data shown in the performing step 2a in integer transform, in the reprocessing that realizes the transform data shown in step 3b in the integral inverse transform.Especially, in integral inverse transform, also to finish the operation that result with the single step conversion carries out the clamped and shift operation of Clip.
Storage transposition unit: be 8 * 8 register array, be used to deposit the intermediate object program after the conversion of single step for the first time, the input data of the conversion of single step are for the second time obtained by data transposition wherein.
Controller: the gating matrix multiplication unit, data processing unit, the transposition memory cell realizes the single step conversion, and finally finishes integer transform or inverse transformation.
The parallel mode that is illustrated in figure 1 as AVS of the present invention realizes the hardware unit block diagram of integer transform and inverse transformation, in this embodiment, adopts parallel mode, and n=2 promptly comprises 2 groups of parallel combinatorial operation unit.In each parallel group combinatorial operation unit, comprise the matrix multiplication unit and the data processing unit of mutual swap data.Storage transposition unit and each group combinatorial operation elements exchange data.Controller is by signal and Data Control storage transposition unit and each group combinatorial operation unit co-ordination.
The hardware implement device of the integer transform of AVS as shown in Figure 1 and inverse transformation, the situation when n=1 and n>2 only needs the combinatorial operation unit that data processing unit and matrix multiplication unit are combined into done and simply simplifies or increase.
In sum, the hardware implement device of the integer transform of a kind of AVS and inverse transformation can comprise n matrix multiplication unit, n data processing unit, a storage transposition unit and a controller.Wherein, n matrix multiplication unit is parallel, once finishes the single step conversion of 8n data, and n data processing unit is corresponding one by one with n matrix multiplication unit, realizes the preliminary treatment or the reprocessing of 8n data.Parameter n is adjustable, and recommended value is 8 factor 1,2,4,8.
Further, in another embodiment of the present invention, on the basis of above-mentioned hardware implement device, can improve degree of parallelism with two cover hardware implement devices, the parallel and pipeline mode that is illustrated in figure 2 as AVS of the present invention is realized the hardware unit block diagram of integer transform and inverse transformation.Same n=2 among Fig. 2.For the situation of n=1 and n>2, only need data processing unit and matrix multiplication unit done and simply simplify or increase.
Among Fig. 2, comprise 4 groups of combinatorial operation unit, storage transposition unit and controller.The data processing unit and the matrix multiplication unit that all comprise mutual swap data in every group of combinatorial operation unit.These 4 groups of combinatorial operation unit are divided into level combinatorial operation unit behind 2 groups of prime combinatorial operation unit and 2 groups.Two groups of input data are imported two groups of prime combinatorial operation unit respectively, through the conversion of the data after these two groups of prime combinatorial operation cell processing through storage unit, as the input data of level combinatorial operation unit after other two groups, export after the processing through level combinatorial operation unit after these two groups again.Controller is controlled every group of combinatorial operation unit and the unit co-ordination of storage transposition.
In sum, the hardware implement device of the integer transform of a kind of AVS and inverse transformation can comprise 2n matrix multiplication unit and 2n data processing unit, a transposition memory cell, a controller.Wherein, each data processing unit of n matrix multiplication unit and n constitutes prime combinatorial operation unit, each data processing unit of an other n matrix multiplication unit and n constitutes level combinatorial operation unit, back, the two-stage calculation device is by the unit serial of storage transposition, parallel by the n level, 2 grades of flowing water are realized integer transform or the inverse transformation of AVS.Parameter n is adjustable, and recommended value is 8 factor 1,2,4,8.
Above-mentioned controller has 3 status signals:
Trans_en, whole hardware unit is not worked when Trans_en=0, and whole hardware unit is just worked when Trans_en=1;
Trans_st represents to carry out the integer direct transform when Trans_st=0, represent to carry out integral inverse transform when Trans_st=1;
Trans_time represents the single step conversion first time carried out when Trans_time=0, represent the single step conversion second time carried out when Trans_time=1, and when data Trans_en became 1 by 0, the value of Trans_time was changed to 0.
Also there are three control signals above-mentioned storage transposition unit:
Row_en=0, col_en=1, the time represent data by the row deposit in, read by row.
Row_en=1 represents during col_en=0 that data deposit in by row, reads by row.
Full=1 shows that the data in the storage transposition unit are full, makes the value of Trans_time become 1 by 0, carries out the single step conversion second time.
Be illustrated in figure 3 as the data flow diagram in the AVS integer transform of the present invention, this is one embodiment of the present of invention.Among Fig. 3, the integer transform process of AVS is implemented as follows: Trans_en=1, device is started working.At this moment: Trans_st=0, Trans_time=0, full=0, row_en=1, col_en=0.
The first step: transform data preliminary treatment.If the input data are p0, p1, p2 ... .p7, obtain intermediate data r0 after the preliminary treatment, r1, r2, r3, r4, r5, r6, r7, then:
r0=((p0+p7)+(p3+p4)),
r4=((p1+p6)+(p2+p5)),
r2=((p0+p7)-(p3+p4)),
r6=((p1+p6)-(p2+p5)),
r1=(p0-p7),r3=(p1-p6),
r5=(p2-p5),r7=(p3-p4).
Wherein, r0 and r2, r4 and r6 can calculate simultaneously because equation the right has only the difference of sign.
Second step: data conversion.Utilize three fundamental matrixs, the data that obtain after the preliminary treatment carried out conversion:
q 0 q 4 = 8 1 1 1 - 1 r 0 r 4
q 2 q 6 = 2 5 2 2 - 5 r 2 r 6
q 1 q 3 q 5 q 7 = 10 9 6 2 9 - 2 - 10 - 6 6 - 10 2 9 2 - 6 9 10 r 1 r 3 r 5 r 7
The result who obtains the single step conversion is:
q0=3<<(r0+r4),
q4=3<<(r0-r4),
q2=1<<(5r2+2r6),
q6=1<<(2r2-5r6),
q1=10r1+9r3+6r5+2r7,
q3=9r1-2r3-10r5-6r7,
q5=6r1-10r3+2r5+9r7,
q7=2r1-6r3+9r5-10r7.
Wherein: the constant coefficient multiplication adopts addition and displacement to realize.
Store by row in storage transposition unit through q0~q7 after the single step conversion.
After 8 * 8 storage transposition unit was full, the data that full=1, Tans_time=1. store in the transposition unit were at this moment taken out by row, and as the input data of the single step conversion second time, the data of the conversion of single step are for the second time directly exported.
Be illustrated in figure 4 as the data flow diagram in the AVS integral inverse transform of the present invention, the specific implementation process of integral inverse transform is as follows: Trans_en=1, device is started working.At this moment: Trans_st=1, Trans_time=0, full=0, row_en=0, col_en=1.
The first step: data conversion.If the input data are p0, p1, p2 ... .p7, utilize three fundamental matrix calculated datas to obtain intermediate object program r0, r1, r2 earlier ... .r7 be:
r 0 r 4 = 8 1 1 1 - 1 p 0 p 4 r 2 r 6 = 2 5 2 2 - 5 p 2 p 6
r 1 r 3 r 5 r 7 = 10 9 6 2 9 - 2 - 10 - 6 6 - 10 2 9 2 - 6 9 10 p 1 p 3 p 5 p 7
The intermediate object program that obtains can be expressed as:
r0=3<<(p0+p4),
r4=3<<(p0-p4),
r2=1<<(5p2+2p6),
r6=1<<(2p2-5p6),
r1=10p1+9p3+6p5+2p7,
r3=9p1-2p3-10p5-6p7,
r5=6p1-10p3+2p5+9p7,
r7=2p1-6p3+9p5-10p7.
Wherein: the constant coefficient multiplication adopts addition and displacement to realize, as 5p0=p0+2<<p0.
Second step: transform data reprocessing.Simple calculating can be expressed as:
Tq0=(r0+r2)+r1,Tq1=(r4+r6)+r3,Tq2=(r4-r6)+r5,Tq3=(r0-r2)+r7,
Tq4=(r0-r2)-r7,Tq5=(r4-r6)-r5,Tq6=(r4+r6)-r3,Tq7=(r0+r2)-r1。
The 3rd step: dateout qi=(clip3 (215,215, (Tqi+4)))>>3.
The data of output deposit in the storage transposition unit by row.After storage transposition unit is filled with, full=1, Tans_time=1, the data of storing this moment in the transposition unit are taken out by row, as the input data of the single step conversion second time.In the conversion of single step for the second time, dateout is: qi=(clip3 (215,215, (Tqi+64)))>>7.
In sum, the matrix of the single step conversion in AVS integer transform (positive-going transition) and the integral inverse transform is the relation of transposition, and the present invention utilizes the data transposition recycling arithmetic element of this point with single-frequency conversion, but this point is not a core; The matrix of AVS integer transform and integral inverse transform is two matrix operations inequality, but also exist the relation of transposition between two matrixes, the present invention considers this relation exactly, matrix decomposition in the single step conversion is become the symmetrical matrix computing, because the transposition of symmetrical matrix is an itself, so just can realize integer transform and integral inverse transform with same set of hardware.And because a large amount of symmetries in the cracking matrix and the characteristic of conjugate operation, operand and hardware resource can further be saved.
The single-frequency conversion of integer transform and integral inverse transform also has an important difference except the order of data processing is different, being exactly has the clip computing and do not have in the direct transform in the inverse transformation.
Be illustrated in figure 5 as integer transform flow chart of the present invention, at first carry out the transform data preliminary treatment, and then carry out data conversion; Set up a flag register to be used for the number of times of record data conversion, for example Tans_time=1 or 0 when this flag register is depicted as conversion for the first time, just carries out conversion next time with the step cycle of getting back to beginning behind the transform data transposition.If shown in this flag register be not conversion for the first time, just direct dateout.
Be illustrated in figure 6 as integral inverse transform flow chart of the present invention, data conversion is at first carried out in beginning, and then carries out the transform data reprocessing, if same flag register represents it is conversion for the first time, just Bian is changed transposition behind the Shuo Ju position, the step cycle that returns beginning is carried out conversion next time.Otherwise export after Bian changed Shuo Ju position.
The above only is preferred embodiment of the present invention, not in order to restriction the present invention, all any modifications of being done within the spirit and principles in the present invention, is equal to and replaces and improvement etc., all should be included within protection scope of the present invention.The present invention is compared with people's such as Wang Leirui invention, and aspect integer transform and inverse transformation, the present invention has utilized the character of transformation matrix more fully, at operand, and hardware resource, aspects such as versatility all are better than this invention.

Claims (10)

1. video encoding/decoding apparatus comprises the implement device of integer transform and inverse transformation; The implement device of described integer transform and inverse transformation comprises combinatorial operation unit and the storage transposition unit that interconnects swap data, and the controller of controlling described combinatorial operation unit and the unit co-ordination of storage transposition; Described combinatorial operation unit comprises matrix multiplication unit and the data processing unit that interconnects swap data; It is characterized in that:
Described matrix multiplication unit comprises the arithmetic element of the matrix operation that realizes following three kinds of basic symmetrical matrixes respectively:
O 0 = 8 1 1 1 - 1 ;
O 1 = 2 5 2 2 - 5 ;
E = 10 9 6 2 9 - 2 - 10 - 6 6 - 10 2 9 2 - 6 9 10 ;
Described data processing unit is used for realizing at integer transform the preliminary treatment of input data, realizes the reprocessing of transform data in integral inverse transform, and the result of single step conversion is carried out clamper and shift operation;
Described transposition memory cell be used to deposit with output transform after data, and as required the input data are carried out transposition.
2. video encoding/decoding apparatus as claimed in claim 1 is characterized in that, the implement device of described integer transform and inverse transformation comprises n group combinatorial operation unit, can carry out the integer transform and the inverse transformation of n group input data simultaneously; Described n group input data are imported corresponding n group combinatorial operation unit respectively, handle through importing described transposition memory cell after the computing again, and then the corresponding n group combinatorial operation unit of input carry out computing; Parameter n is a natural number.
3. video encoding/decoding apparatus as claimed in claim 2, it is characterized in that, the implement device of described integer transform and inverse transformation comprises prime n group combinatorial operation unit and level n group combinatorial operation unit, back, can carry out the integer transform and the inverse transformation of n group input data simultaneously; Described n group input data are imported corresponding described prime n group combinatorial operation unit respectively and are carried out computing, import described transposition memory cell again and handle, and then the corresponding level n group combinatorial operation unit, described back of input continues computing.
4. as claim 2 or 3 described video encoding/decoding apparatus, it is characterized in that the control signal that described controller is controlled described combinatorial operation unit and the unit co-ordination of storage transposition comprises:
Trans_en, value 0 or 1, the implement device that is respectively applied for described integer transform of sign and inverse transformation is in does not work or operating state;
Trans_st, value 0 or 1, what be respectively applied for that the implement device of sign described integer transform and inverse transformation carries out is integer direct transform or integral inverse transform.
Trans_time, value 0 or 1, what be respectively applied for that the implement device of sign described integer transform and inverse transformation carries out is the conversion of single step for the first time, the still conversion of single step for the second time; And when control signal Trans_en became 1 by 0, the value of Trans_time was changed to 0.
5. video encoding/decoding apparatus as claimed in claim 4 is characterized in that, the control signal that described storage transposition unit uses comprises row_en, col_en, and full:
Work as row_en=0, during col_en=1, handled data deposit in by row, read by row;
Work as row_en=1, during col_en=0, handled data deposit in by row, read by row;
When full=1, the data in the described storage transposition unit are full, and the value of described control signal Trans_time becomes 1 by 0, carries out the single step conversion second time.
6. as claim 2 or 3 described video encoding/decoding apparatus, it is characterized in that described parameter n is 8 factor 1,2,4,8.
7. video encoding/decoding apparatus as claimed in claim 2 is characterized in that, described transposition memory cell is 8 * 8 register array.
8. the method for the integer transform of a video encoding/decoding apparatus and inverse transformation is characterized in that, the matrix operation of carrying out twice three kinds of basic symmetrical matrixes in the identical matrix multiplication unit of structure all is taken up in order of priority in the calculating of described integer transform and inverse transformation; Described three kinds of basic symmetrical matrixes are:
O 0 = 8 1 1 1 - 1 ;
O 1 = 2 5 2 2 - 5 ;
E = 10 9 6 2 9 - 2 - 10 - 6 6 - 10 2 9 2 - 6 9 10 .
9. the method for integer transform as claimed in claim 8 and inverse transformation is characterized in that the method for described integer transform comprises the steps:
If the data of input are p0, p1, p2 ... .p7, the data of output are q0, q1, and q2 ... ..q7, intermediate variable is r0, r1, and r2 ... .r7; The value of single step conversion register Trans_time is 0 or 1, and initial value is 1;
The first step, the value of single step conversion register Trans_time adds 1; Data p0, p1, p2 ... .p7 import data processing unit and carry out preliminary treatment, obtain data r0, r1, r2 ... r7; Comprise:
r0=((p0+p7)+(p3+p4)),
r4=((p1+p6)+(p2+p5)),
r2=((p0+p7)-(p3+p4)),
r6=((p1+p6)-(p2+p5)),
r1=(p0-p7),
r3=(p1-p6),
r5=(p2-p5),
r7=(p3-p4).
Second step, data r0, r1, r2 ... r7 input matrix multiplication unit carries out the matrix operation of three basic symmetrical matrixes, to the data r0 that obtains after the preliminary treatment, and r1, r2 ... r7 carries out conversion:
q 0 q 4 = 8 1 1 1 - 1 r 0 r 4
q 2 q 6 = 2 5 2 2 - 5 r 2 r 6
q 1 q 3 q 5 q 7 = 10 9 6 2 9 - 2 - 10 - 6 6 - 10 2 9 2 - 6 9 10 r 1 r 3 r 5 r 7
The 3rd step, above-mentioned data q0, q1, q2 ... ..q7 the transposition unit is stored in input; When single step conversion register Trans_time=0, data q0, q1, q2 ... ..q7 by behind the transposition as new input data q0, q1, q2 ... ..q7, get back to the first step; When single step conversion register Trans_time=1, data q0, q1, q2 ... ..q7 the result as integer transform directly exports.
10. the method for integer transform as claimed in claim 8 and inverse transformation is characterized in that the method for described integral inverse transform comprises the steps:
If the data of input are p0, p1, p2 ... .p7, the data of output are q0, q1, and q2 ... ..q7, intermediate variable is r0, r1, and r2 ... .r7 and Tq0, Tq1, Tq2 ... ..Tq7; The value of single step conversion register Trans_time is 0 or 1, and initial value is 1;
Steps A, the value of single step conversion register Trans_time adds 1; Data p0, p1, p2 ..., p7 input matrix multiplication unit carries out the matrix operation of three basic symmetrical matrixes, obtains intermediate variable data r0, r1, r2 ... .r7:
r 0 r 4 = 8 1 1 1 - 1 p 0 p 4
r 2 r 6 = 2 5 2 2 - 5 p 2 p 6
r 1 r 3 r 5 r 7 = 10 9 6 2 9 - 2 - 10 - 6 6 - 10 2 9 2 - 6 9 10 p 1 p 3 p 5 p 7
Step B: above-mentioned data r0, r1, r2 ... .r7 import described data processing unit and carry out reprocessing:
Tq0=(r0+r2)+r1,
Tq1=(r4+r6)+r3,
Tq2=(r4-r6)+r5,
Tq3=(r0-r2)+r7,
Tq4=(r0-r2)-r7,
Tq5=(r4-r6)-r5,
Tq6=(r4+r6)-r3,
Tq7=(r0+r2)-r1;
Step C: when single step conversion register Trans_time=0, then dateout is:
qi=(clip3(-215,215,(Tqi+4)))>>3;
And the data q0 that obtains, q1, q2 ... ..q7 as new input data p0, p1, p2 ... .p7, get back to steps A;
When single step conversion register Trans_time=1, then conversion dateout is:
qi=(Clip3(-215,215,(Tqi+64)))>>7。
CN 201010172984 2010-05-07 2010-05-07 Video encoding and decoding device and integer transform and inverse transform method thereof Pending CN101848392A (en)

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