CN101847382B - Noise suppression device for reducing noise of liquid crystal display and liquid crystal display related thereto - Google Patents
Noise suppression device for reducing noise of liquid crystal display and liquid crystal display related thereto Download PDFInfo
- Publication number
- CN101847382B CN101847382B CN2009101193551A CN200910119355A CN101847382B CN 101847382 B CN101847382 B CN 101847382B CN 2009101193551 A CN2009101193551 A CN 2009101193551A CN 200910119355 A CN200910119355 A CN 200910119355A CN 101847382 B CN101847382 B CN 101847382B
- Authority
- CN
- China
- Prior art keywords
- voltage
- signal
- grid
- data drive
- accurate position
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Images
Landscapes
- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
Abstract
The invention discloses a noise suppression device, comprising a voltage detection circuit and a display enabling signal generation device. The voltage detection circuit is used for detecting a grid opening voltage, a grid closing voltage and a data driving voltage all required by a liquid crystal display, in order to correspondingly generate a grid opening voltage level judging signal, a grid closing voltage level judging signal and a data driving voltage level judging signal. The display enabling signal generation device is used for generating a display enabling signal, according to the grid opening voltage level judging signal, the grid closing voltage level judging signal and the data driving voltage level judging signal, in order to enable the liquid crystal display to display pictures.
Description
Technical field
The invention relates to a kind of Noise Suppression Device of LCD, also in particular, the invention relates to that a kind of LCD that suppresses produces noise and influences the Noise Suppression Device that picture shows when start.
Background technology
Please refer to Fig. 1, Fig. 1 is to be the calcspar of the LCD 100 of a prior art.As shown in Figure 1, LCD 100 comprises electric power management circuit 110, data drive circuit 120, gate driver circuit 130 and viewing area 140.When LCD 100 starts, electric power management circuit 110 receives input voltage V
CC, and produce grid cut-in voltage V according to this
GH, grid closes voltage V
GLAnd data drive voltage V
DAElectric power management circuit 110 transmits grid cut-in voltage V
GH, grid closes voltage V
GLTo gate driver circuit 130; Electric power management circuit 110 transmits data drive voltage V
DATo data drive circuit 120.Gate driver circuit 130 is with received grid cut-in voltage V
GHClose voltage V with grid
GL, transmit gate drive signal S
GTo the viewing area 140; Data drive circuit 120 is with received data drive voltage V
DA, transmit data drive signal S
DTo the viewing area 140.Viewing area 140 is again according to the gate drive signal S that is received
GWith data drive signal S
D, display frame.
Yet, when open state,, will cause LCD 100 picture when start to have noise if the order of 110 output voltages of electric power management circuit is incorrect.More particularly, gate driver circuit 130 need receive grid earlier and close voltage V
GLTo close viewing area 140 in advance, data drive circuit 120 just can receive data drive voltage V then
DA Gate driver circuit 130 just can receive grid cut-in voltage V afterwards
GH Gate driver circuit 130 could be opened viewing area 140 then.That is to say that the order of voltage starting is required to be grid and closes voltage V
GL, data drive voltage V
DA, grid cut-in voltage V
GHAnd if the order of 110 output voltages of electric power management circuit is not as above-mentioned, then might be when the stage of start, the gate drive signal S that gate driver circuit 130 is exported
G, open viewing area 140 and make viewing area 140 that previous residual picture is shown, cause noise; Or the gate drive signal S that exported of gate driver circuit 130
G, the data drive signal S of viewing area 140 unlatchings and data drive circuit 120 misoperation output errors
D, and make viewing area 140 demonstrate incorrect picture, can cause noise equally.
Summary of the invention
The present invention provides a kind of Noise Suppression Device of reduction by one noise of liquid crystal display.
This Noise Suppression Device comprises a voltage detection circuit; Be used for detecting this LCD required a grid cut-in voltage, a grid and close a voltage and a data drive voltage, judge that to produce the accurate position of a grid cut-in voltage accordingly signal, a grid are closed voltage quasi position judgement signal and signal is judged in the accurate position of a data drive voltage; And one show the enable signal generation device; Be used for judging that according to the accurate position of this grid cut-in voltage signal, this grid are closed voltage quasi position judgement signal and signal is judged in the accurate position of this data drive voltage, produce a demonstration enable signal with this liquid crystal display displays picture of activation.
The present invention also provides a kind of tool to reduce the LCD of noise.This LCD comprises an electric power management circuit, be used for receiving an input voltage with produce a grid cut-in voltage according to this, a grid is closed a voltage and a data drive voltage; One Noise Suppression Device is electrically connected at this electric power management circuit, is used for closing voltage and this data drive voltage according to this grid cut-in voltage, this grid, produces one and shows enable signal; One gate driver circuit is electrically connected at this electric power management circuit, is used for closing voltage according to this grid cut-in voltage and this grid, transmits a gate drive signal; One data drive circuit is electrically connected at this electric power management circuit and this Noise Suppression Device, is used for changing and this demonstration enable signal according to this data drive voltage action, transmits a data drive signal; And a viewing area, be electrically connected at this gate driver circuit and this data drive circuit, be used for according to this gate drive signal and this data drive signal, display frame.
Description of drawings
Fig. 1 is to be the calcspar of the LCD of a prior art;
Fig. 2 is the calcspar for LCD of the present invention;
Fig. 3 is the sequential chart for when start explanation voltage starting order;
Fig. 4 is for the calcspar of Noise Suppression Device of the present invention is described;
Fig. 5 is for the sequential chart of Noise Suppression Device internal signal running of the present invention is described.
[primary clustering symbol description]
100,200 LCDs
110,210 electric power management circuits
120,220 data drive circuits
130,230 gate driver circuits
140,240 viewing areas
250 Noise Suppression Devices
251 voltage detection circuits
252 show the enable signal generation device
2511 grids are closed the voltage quasi position decision circuitry
The accurate position of 2512 grid cut-in voltages decision circuitry
The accurate position of 2513 data voltages decision circuitry
V
CCInput voltage
V
DAData drive voltage
V
GLGrid is closed voltage
V
GHThe grid cut-in voltage
S
GGate drive signal
S
DData drive signal
S
LPShow enable signal
S
GLGrid is closed voltage quasi position and is judged signal
S
GHSignal is judged in the accurate position of grid cut-in voltage
S
DASignal is judged in the accurate position of data drive voltage
T
1, T
2, T
3, T
4, T
5Constantly
N
1, N
2, N
3, N
4Node
X
1, X
2The signal latch assembly
AND
1, AND
2, AND
3The logic lock
Embodiment
In the middle of instructions and claims, used some vocabulary to censure specific assembly.Having common knowledge the knowledgeable in the affiliated field should understand, and same assembly may be called with different nouns by manufacturer.This instructions and claims are not used as distinguishing the mode of assembly with the difference of title, but the benchmark that is used as distinguishing with the difference of assembly on function.Be to be an open term mentioned " comprising " in the middle of instructions and the claim in the whole text, so should be construed to " comprise but be not limited to ".In addition, " electric connection " speech is to comprise any indirect means that are electrically connected that directly reach at this.Therefore, be electrically connected at one second device, then represent this first device can be directly connected in this second device, or be connected to this second device through other device or the intersegmental ground connection of connection hand if describe one first device in the literary composition.
Please refer to Fig. 2, Fig. 2 is the calcspar for LCD 200 of the present invention.As shown in Figure 2, LCD 200 comprises electric power management circuit 210, data drive circuit 220, gate driver circuit 230, Noise Suppression Device 250, and viewing area 240.Electric power management circuit 210 is electrically connected at data drive circuit 220, gate driver circuit 230 and Noise Suppression Device 250.Viewing area 240 be electrically connected at data drive circuit 220 with gate driver circuit 230.When LCD 200 starts, electric power management circuit 210 receives input voltage V
CC, and produce grid cut-in voltage V according to this
GH, grid closes voltage V
GLAnd data drive voltage V
DAElectric power management circuit 210 transmits grid cut-in voltage V
GH, grid closes voltage V
GLTo gate driver circuit 230; Electric power management circuit 210 transmits data drive voltage V
DATo data drive circuit 220.Gate driver circuit 230 is according to received grid cut-in voltage V
GHClose voltage V with grid
GL, transmit gate drive signal S
GTo the viewing area 240; Data drive circuit 220 is according to received data drive voltage V
DA, transmit data drive signal S
DTo the viewing area 240.Viewing area 240 is again according to the gate drive signal S that is received
GWith data drive signal S
D, display frame.Noise Suppression Device 250 is electrically connected at electric power management circuit 210 and data drive circuit 220.Noise Suppression Device 250 is to be used for receiving input voltage V
CC, grid cut-in voltage V
GH, grid closes voltage V
GLAnd data drive voltage V
DA, and judge that the voltage order received is whether for correctly and all stable, to export the demonstration enable signal S of corresponding states according to this
LPTo data drive circuit 220.More particularly, judge that when Noise Suppression Device 250 the present voltage that receives is incorrect or unstable in proper order, then see the demonstration enable signal S of logical zero (electronegative potential) off
LPTo data drive circuit 220, to stop data drive circuit 220 output data drive signal S
DOtherwise judging the present voltage that receives when Noise Suppression Device 250 is correct and stable in proper order, then sees the demonstration enable signal S of logical one (noble potential) off
LPTo data drive circuit 220, with activation data drive circuit 220 output data drive signal S
DTransmission display enable signal S like this
LPControl, can prevent effectively that LCD 200 from producing noise or demonstrating incorrect picture in start-up phase.The principle of work of Noise Suppression Device 250 below will more at large be described.
Please also refer to Fig. 3 and Fig. 4, Fig. 3 is the sequential chart for when start explanation voltage starting order.Fig. 4 is for the calcspar of Noise Suppression Device 250 of the present invention is described.As shown in Figure 3, in moment T
1After the start, to moment T
2The time, input voltage V
CCJust stable; To moment T
3The time, grid is closed voltage V
GLIt is just stable that (for instance, grid is closed voltage V
GLDrop to-6 volts for 0 volt from script); To moment T
4The time, data drive voltage V
DAJust stable (data drive voltage V for instance,
DARise to 9.6 volts for 0 volt from script); To moment T
5The time, grid cut-in voltage V
GHJust stable (grid cut-in voltage V for instance,
GHRise to 18 volts for 0 volt from script).In Fig. 4, Noise Suppression Device 250 comprises voltage detection circuit 251 and shows enable signal generation device 252.Voltage detection circuit 251 comprises grid and closes voltage quasi position decision circuitry 2511, grid cut-in voltage accurate position decision circuitry 2512 and the accurate position of data drive voltage decision circuitry 2513.The accurate position of grid cut-in voltage decision circuitry 2511 is used for receiving grid and closes voltage V
GL, and produce grid according to this and close voltage quasi position and judge signal S
GLMore particularly, close voltage V when grid
GLWhen still being 0 volt, grid is closed voltage quasi position and is judged signal S
GLBe logical zero (electronegative potential); When grid is closed voltage V
GLWhen dropping to-6 volts, grid is closed voltage quasi position and is judged signal S
GLBe by logical one (noble potential).The accurate position of grid cut-in voltage decision circuitry 2512 is used for receiving grid cut-in voltage V
GH, and produce the accurate position judgement of grid cut-in voltage signal S according to this
GHMore particularly, as grid cut-in voltage V
GHWhen still being 0 volt, signal S is judged in the accurate position of grid cut-in voltage
GHBe logical zero (electronegative potential); As grid cut-in voltage V
GHWhen rising to 18 volts, signal S is judged in the accurate position of grid cut-in voltage
GHBe by logical one (noble potential).The accurate position of data drive voltage decision circuitry 2513 is used for receiving data drive voltage V
DA, and produce the accurate position judgement of data drive voltage signal S according to this
DAMore particularly, as data drive voltage V
DAWhen still being 0 volt, signal S is judged in the accurate position of data drive voltage
DABe logical zero (electronegative potential); As data drive voltage V
DAWhen rising to 9.6 volts, signal S is judged in the accurate position of data drive voltage
DABe by logical one (noble potential).
Please continue with reference to figure 4, show that enable signal generation device 252 comprises three logic lock AND
1, AND
2And AND
3, and binary signal latch assembly X
1And X
2Logic lock AND
1, AND
2And AND
3Can be and door (AND gate).Signal latch assembly X
1And X
2Be used for the accurate position of logic of the signal that the bolt-lock residence receives.Logic lock AND
1Comprise a normal phase input end, two inverting inputs, and an output terminal; Logic lock AND
1The signal that is used for its all input end is received carries out and computing, and in its output terminal output operation result.Logic lock AND
2Comprise a normal phase input end, two inverting inputs, and an output terminal; Logic lock AND
2The signal that is used for its all input end is received carries out and computing, and in its output terminal output operation result.Logic lock AND
3Comprise two normal phase input ends, and an output terminal; Logic lock AND
3The signal that is used for its all input end is received carries out and computing, and in its output terminal output operation result.
Logic lock AND
1A normal phase input end electrically be connected to the output terminal that grid is closed voltage quasi position decision circuitry 2511, be used for receiving grid and close voltage quasi position and judge signal S
GLLogic lock AND
1An inverting input electrically be connected to the output terminal of the accurate position of grid cut-in voltage decision circuitry 2512, be used for receiving the accurate position of grid cut-in voltage and judge signal S
GHLogic lock AND
1Another inverting input electrically be connected to the output terminal of the accurate position of data drive voltage decision circuitry 2513, be used for receiving the accurate position of data drive voltage and judge signal S
DALogic lock AND
1Just close voltage quasi position according to the grid that is received and judge signal S
GL, the accurate position of grid cut-in voltage judges signal S
GHAnd signal S is judged in the accurate position of data drive voltage
DACarry out and computing, and in logic lock AND
1Output terminal (node N
1) the output operation result.
Signal latch assembly X
1Comprise an input end I, be electrically connected at logic lock AND
1Output terminal (node N
1); One output terminal O is electrically connected at logic lock AND
2Normal phase input end (node N
2).As input voltage V
CCBefore stable (as aforementioned at moment T
1Before), signal latch assembly X
1The signal exported of output terminal O remain on logical zero (electronegative potential); As input voltage V
CCAfter stable (as aforementioned at moment T
1Afterwards), and signal latch assembly X
1The signal that received of input end I be that (meaning is logic lock AND to logical zero (electronegative potential)
1Operation result), signal latch assembly X
1The signal exported of output terminal O remain on logical zero (electronegative potential); As input voltage V
CCAfter stable (as aforementioned at moment T
1Afterwards), in case and signal latch assembly X
1The signal that received of input end I be that (meaning is logic lock AND to logical one (noble potential)
1Operation result), signal latch assembly X
1The signal exported of output terminal O then continue to remain on logical one (noble potential).
Logic lock AND
2A normal phase input end electrically be connected to signal latch assembly X
1Output terminal O (node N
2), be used for receiving signal latch assembly X
1Output joint fruit; Logic lock AND
2An inverting input electrically be connected to the output terminal of the accurate position of grid cut-in voltage decision circuitry 2512, be used for receiving the accurate position of grid cut-in voltage and judge signal S
GHLogic lock AND
2Another inverting input electrically be connected to the output terminal of the accurate position of data drive voltage decision circuitry 2513, be used for receiving the accurate position of data drive voltage and judge signal S
DALogic lock AND
2Just according to the signal latch assembly X that is received
1The accurate position of output result, grid cut-in voltage judge signal S
GHAnd signal S is judged in the accurate position of data drive voltage
DACarry out and computing, and in logic lock AND
2Output terminal (node N
3) the output operation result.
Signal latch assembly X
2Comprise an input end I, be electrically connected at logic lock AND
2Output terminal (node N
3); One output terminal O is electrically connected at logic lock AND
3Normal phase input end (node N
4).As input voltage V
CCBefore stable (as aforementioned at moment T
1Before), signal latch assembly X
2The signal exported of output terminal O remain on logical zero (electronegative potential); As input voltage V
CCAfter stable (as aforementioned at moment T
1Afterwards), and signal latch assembly X
1The signal that received of input end I be that (meaning is logic lock AND to logical zero (electronegative potential)
2Operation result), signal latch assembly X
2The signal exported of output terminal O remain on logical zero (electronegative potential); As input voltage V
CCAfter stable (as aforementioned at moment T
1Afterwards), in case and signal latch assembly X
2The signal that received of input end I be that (meaning is logic lock AND to logical one (noble potential)
2Operation result), signal latch assembly X
2The signal exported of output terminal O then continue to remain on logical one (noble potential).
Logic lock AND
3A normal phase input end electrically be connected to signal latch assembly X
2Output terminal O (node N
4), be used for receiving signal latch assembly X
2Output joint fruit; Logic lock AND
3Another normal phase input end electrically be connected to the output terminal of the accurate position of grid cut-in voltage decision circuitry 2512, be used for receiving the accurate position of grid cut-in voltage and judge signal S
GHLogic lock AND
3Just judge signal S according to the accurate position of the grid cut-in voltage that is received
GHAnd signal latch assembly X
2The output result carry out and computing, and in logic lock AND
3Output terminal output operation result with as demonstration enable signal S
LP
Please refer to Fig. 5, Fig. 5 is for the sequential chart of Noise Suppression Device 250 internal signals running of the present invention is described.As shown in Figure 5, show enable signal S
LPCan be via node N
1, N
2, N
3And N
4On signal produce, and before all voltages are all stablized (T constantly
5), maintain the state of logical zero (electronegative potential), to stop data drive circuit 220 output data drive signal S
DAnd all stablize back (moment T at all voltages
5), maintain the state of logical one (noble potential), with activation data drive circuit 220 output data drive signal S
D
In sum, Noise Suppression Device provided by the present invention under the power supply order condition of different that starts, can suppress LCD at the noise that start-up phase produced effectively, and the user is provided bigger convenience.
The above is merely preferred embodiment of the present invention, and all equalizations of being done according to claim scope of the present invention change and modify, and all should belong to covering scope of the present invention.
Claims (4)
1. a Noise Suppression Device that reduces a noise of liquid crystal display is characterized in that, comprises:
One voltage detection circuit; Be used for detecting this LCD required a grid cut-in voltage, a grid and close a voltage and a data drive voltage, judge that to produce the accurate position of a grid cut-in voltage accordingly signal, a grid are closed voltage quasi position judgement signal and signal is judged in the accurate position of a data drive voltage; This voltage detection circuit comprises:
The accurate position of one grid cut-in voltage decision circuitry is used for receiving this grid cut-in voltage and judges signal to produce the accurate position of this grid cut-in voltage;
One grid is closed the voltage quasi position decision circuitry, is used for receiving this grid and closes voltage and close voltage quasi position and judge signal to produce this grid; And
The accurate position of one data voltage decision circuitry is used for receiving this data drive voltage and judges signal to produce the accurate position of this data drive voltage;
When this grid cut-in voltage did not reach one first predetermined standard position, the accurate position of this grid cut-in voltage judged that signal is to be an electronegative potential; When this grid cut-in voltage had reached this first predetermined accurate, the accurate position of this grid cut-in voltage judged that signal is to be a noble potential; Close voltage when not reaching one second predetermined accurate position when this grid, this grid is closed voltage quasi position and is judged that signal is to be this electronegative potential; Close voltage when having reached this second predetermined accurate position when this grid, this grid is closed voltage quasi position and is judged that signal is to be this noble potential; When this data drive voltage did not reach one the 3rd predetermined standard position, the accurate position of this data drive voltage judged that signal is to be this electronegative potential; When this data drive voltage had reached the 3rd predetermined standard position, the accurate position of this data drive voltage judged that signal is to be this noble potential;
One shows the enable signal generation device; Be used for judging that based on the accurate position of this grid cut-in voltage signal, this grid are closed voltage quasi position judgement signal and signal is judged in the accurate position of this data drive voltage, produce a demonstration enable signal with this liquid crystal display displays picture of activation; This demonstration enable signal generation device comprises:
One first logic lock comprises:
One normal phase input end is electrically connected at the accurate position of this grid cut-in voltage decision circuitry, is used for receiving the accurate position of this grid cut-in voltage and judges signal;
One first inverting input is electrically connected at this grid and closes the voltage quasi position decision circuitry, is used for receiving this grid and closes voltage quasi position judgement signal;
One second inverting input is electrically connected at the accurate position of this data voltage decision circuitry, is used for receiving the accurate position of this data drive voltage and judges signal; And
One output; This first logic sluice foundation is in the signal that this normal phase input end, this first inverting input and this second inverting input of this first logic lock received, and carries out logical operation with in the result of this output output logic computing of this first logic lock;
One first signal latch assembly comprises:
One input end is electrically connected at this output terminal of this first logic lock, is used for receiving the result of the logical operation of this first logic lock; And
One output terminal, when the result of the logical operation of this first logic lock was low level, this first signal latch assembly was in its this low level of output terminal output; In case after the result of the logical operation of this first logic lock was high levle, this first signal latch assembly continued this high levle of output in its output terminal;
One second logic lock comprises:
One normal phase input end is electrically connected at this output terminal of this first signal latch assembly, is used for receiving the result that this first signal latch assembly is exported;
One first inverting input is electrically connected at this grid and closes the voltage quasi position decision circuitry, is used for receiving this grid and closes voltage quasi position judgement signal;
One second inverting input is electrically connected at the accurate position of this data voltage decision circuitry, is used for receiving the accurate position of this data drive voltage and judges signal; And
One output; This second logic sluice foundation is in the signal that this normal phase input end, this first inverting input and this second inverting input of this second logic lock received, and carries out logical operation with in the result of this output output logic computing of this second logic lock;
One secondary signal latch assembly comprises:
One input end is electrically connected at this output terminal of this second logic lock, is used for receiving the result of the logical operation of this second logic lock; And
One output terminal, when the result of the logical operation of this second logic lock was this low level, this secondary signal latch assembly was in its this low level of output terminal output; In case after the result of the logical operation of this second logic lock was this high levle, this secondary signal latch assembly continued this high levle of output in its output terminal; And
One the 3rd logic lock comprises:
One first normal phase input end is electrically connected at this output terminal of this secondary signal latch assembly, is used for receiving the result that this secondary signal latch assembly is exported;
One second normal phase input end is electrically connected at this grid and closes the voltage quasi position decision circuitry, is used for receiving this grid and closes voltage quasi position judgement signal; And
One output terminal; The 3rd logic lock is according to the signal that this first normal phase input end and this second normal phase input end of the 3rd logic lock received, carry out logical operation with in the result of this output terminal output logic computing of the 3rd logic lock with as this demonstration enable signal.
2. Noise Suppression Device as claimed in claim 1 is characterized in that, this first, this second and the 3rd logic lock is and door, in order to carry out and computing.
3. the LCD of a tool reduction noise is characterized in that, comprises:
One electric power management circuit, be used for receiving an input voltage with produce a grid cut-in voltage according to this, a grid is closed a voltage and a data drive voltage;
One Noise Suppression Device is electrically connected at this electric power management circuit, is used for closing voltage and this data drive voltage according to this grid cut-in voltage, this grid, produces one and shows enable signal;
One gate driver circuit is electrically connected at this electric power management circuit, is used for closing voltage according to this grid cut-in voltage and this grid, transmits a gate drive signal;
One data drive circuit is electrically connected at this electric power management circuit and this Noise Suppression Device, is used for changing and this demonstration enable signal according to this data drive voltage action, transmits a data drive signal; And
One viewing area is electrically connected at this gate driver circuit and this data drive circuit, is used for according to this gate drive signal and this data drive signal, display frame;
Wherein, this Noise Suppression Device comprises:
One voltage detection circuit; Be used for detecting this grid cut-in voltage, this grid is closed voltage and this data drive voltage, judges that to produce the accurate position of a grid cut-in voltage accordingly signal, a grid close voltage quasi position and judge that signal and the accurate position of a data drive voltage judge signal; And
One shows the enable signal generation device, is used for judging that based on the accurate position of this grid cut-in voltage signal, this grid are closed voltage quasi position judgement signal and signal is judged in the accurate position of this data drive voltage, produces to be somebody's turn to do to show enable signal;
This voltage detection circuit further comprises:
The accurate position of one grid cut-in voltage decision circuitry is used for receiving this grid cut-in voltage and judges signal to produce the accurate position of this grid cut-in voltage;
One grid is closed the voltage quasi position decision circuitry, is used for receiving this grid and closes voltage and close voltage quasi position and judge signal to produce this grid; And
The accurate position of one data drive voltage decision circuitry is used for receiving this data drive voltage and judges signal to produce the accurate position of this data drive voltage;
When this grid cut-in voltage did not reach one first predetermined standard position, the accurate position of this grid cut-in voltage judged that signal is to be an electronegative potential; When this grid cut-in voltage had reached this first predetermined accurate, the accurate position of this grid cut-in voltage judged that signal is to be a noble potential; Close voltage when not reaching one second predetermined accurate position when this grid, this grid is closed voltage quasi position and is judged that signal is to be this electronegative potential; Close voltage when having reached this second predetermined accurate position when this grid, this grid is closed voltage quasi position and is judged that signal is to be this noble potential; When this data drive voltage did not reach one the 3rd predetermined standard position, the accurate position of this data drive voltage judged that signal is to be this electronegative potential; When this data drive voltage had reached the 3rd predetermined standard position, the accurate position of this data drive voltage judged that signal is to be this noble potential;
This demonstration enable signal generation device further comprises:
One first logic lock comprises:
One normal phase input end is electrically connected at the accurate position of this grid cut-in voltage decision circuitry, is used for receiving the accurate position of this grid cut-in voltage and judges signal;
One first inverting input is electrically connected at this grid and closes the voltage quasi position decision circuitry, is used for receiving this grid and closes voltage quasi position judgement signal;
One second inverting input is electrically connected at the accurate position of this data drive voltage decision circuitry, is used for receiving the accurate position of this data drive voltage and judges signal; And
One output; This first logic sluice foundation is in the signal that this normal phase input end, this first inverting input and this second inverting input of this first logic lock received, and carries out logical operation with in the result of this output output logic computing of this first logic lock;
One first signal latch assembly comprises:
One input end is electrically connected at this output terminal of this first logic lock, is used for receiving the result of the logical operation of this first logic lock; And
One output terminal, when the result of the logical operation of this first logic lock was low level, this first signal latch assembly was in its this low level of output terminal output;
In case after the result of the logical operation of this first logic lock was high levle, this first signal latch assembly continued this high levle of output in its output terminal;
One second logic lock comprises:
One normal phase input end is electrically connected at this output terminal of this first signal latch assembly, is used for receiving the result that this first signal latch assembly is exported;
One first inverting input is electrically connected at this grid and closes the voltage quasi position decision circuitry, is used for receiving this grid and closes voltage quasi position judgement signal;
One second inverting input is electrically connected at the accurate position of this data drive voltage decision circuitry, is used for receiving the accurate position of this data drive voltage and judges signal; And
One output; This second logic sluice foundation is in the signal that this normal phase input end, this first inverting input and this second inverting input of this second logic lock received, and carries out logical operation with in the result of this output output logic computing of this second logic lock;
One secondary signal latch assembly comprises:
One input end is electrically connected at this output terminal of this second logic lock, is used for receiving the result of the logical operation of this second logic lock; And
One output terminal, when the result of the logical operation of this second logic lock was this low level, this secondary signal latch assembly was in its this low level of output terminal output; In case after the result of the logical operation of this second logic lock was this high levle, this secondary signal latch assembly continued this high levle of output in its output terminal; And
One the 3rd logic lock comprises:
One first normal phase input end is electrically connected at this output terminal of this secondary signal latch assembly, is used for receiving the result that this secondary signal latch assembly is exported;
One second normal phase input end is electrically connected at this grid and closes the voltage quasi position decision circuitry, is used for receiving this grid and closes voltage quasi position judgement signal; And
One output terminal; The 3rd logic lock is according to the signal that this first normal phase input end and this second normal phase input end of the 3rd logic lock received, carry out logical operation with in the result of this output terminal output logic computing of the 3rd logic lock with as this demonstration enable signal.
4. LCD as claimed in claim 3 is characterized in that, this first, this second and the 3rd logic lock is and door, in order to carry out and computing.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2009101193551A CN101847382B (en) | 2009-03-25 | 2009-03-25 | Noise suppression device for reducing noise of liquid crystal display and liquid crystal display related thereto |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2009101193551A CN101847382B (en) | 2009-03-25 | 2009-03-25 | Noise suppression device for reducing noise of liquid crystal display and liquid crystal display related thereto |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN101847382A CN101847382A (en) | 2010-09-29 |
| CN101847382B true CN101847382B (en) | 2012-06-27 |
Family
ID=42771981
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2009101193551A Expired - Fee Related CN101847382B (en) | 2009-03-25 | 2009-03-25 | Noise suppression device for reducing noise of liquid crystal display and liquid crystal display related thereto |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN101847382B (en) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR102345396B1 (en) * | 2015-04-03 | 2021-12-31 | 삼성디스플레이 주식회사 | Power management driver and display device having the same |
| TWI637367B (en) * | 2016-09-12 | 2018-10-01 | 瑞鼎科技股份有限公司 | Gate driver |
| CN114207698B (en) | 2020-05-19 | 2023-12-22 | 京东方科技集团股份有限公司 | Power management device and display device |
| CN112994436B (en) * | 2021-02-04 | 2022-06-03 | 重庆先进光电显示技术研究院 | Grid opening voltage generation circuit, display panel driving device and display device |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4873574A (en) * | 1988-12-20 | 1989-10-10 | North American Philips Corporation | Noise measurement for video signals |
| JP2004205588A (en) * | 2002-12-24 | 2004-07-22 | Casio Comput Co Ltd | Display device and its driving control method |
| TW200428352A (en) * | 2003-06-03 | 2004-12-16 | Chunghwa Picture Tubes Ltd | Method for restraining noise when flat display turn on/off |
| JP2006235169A (en) * | 2005-02-24 | 2006-09-07 | Canon Inc | Image display device, control method thereof, and television device |
| CN101178878A (en) * | 2006-11-06 | 2008-05-14 | 中华映管股份有限公司 | Critical application integrate circuit and method of use thereof |
| CN101271675A (en) * | 2007-03-20 | 2008-09-24 | 三星电子株式会社 | LCD driving method using self-masking, and masking circuit and asymmetric latches thereof |
-
2009
- 2009-03-25 CN CN2009101193551A patent/CN101847382B/en not_active Expired - Fee Related
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4873574A (en) * | 1988-12-20 | 1989-10-10 | North American Philips Corporation | Noise measurement for video signals |
| JP2004205588A (en) * | 2002-12-24 | 2004-07-22 | Casio Comput Co Ltd | Display device and its driving control method |
| TW200428352A (en) * | 2003-06-03 | 2004-12-16 | Chunghwa Picture Tubes Ltd | Method for restraining noise when flat display turn on/off |
| JP2005037707A (en) * | 2003-06-03 | 2005-02-10 | Chuka Eikan Kofun Yugenkoshi | Method for suppressing noise when switch of flat panel display is turned on/off |
| JP2006235169A (en) * | 2005-02-24 | 2006-09-07 | Canon Inc | Image display device, control method thereof, and television device |
| CN101178878A (en) * | 2006-11-06 | 2008-05-14 | 中华映管股份有限公司 | Critical application integrate circuit and method of use thereof |
| CN101271675A (en) * | 2007-03-20 | 2008-09-24 | 三星电子株式会社 | LCD driving method using self-masking, and masking circuit and asymmetric latches thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| CN101847382A (en) | 2010-09-29 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN102592559B (en) | Display panel and gate driver therein | |
| CN102819998B (en) | Shift register and display device | |
| CN108648714B (en) | Shifting register unit, driving method, grid driving circuit and display device | |
| CN100492111C (en) | Discharge circuit and liquid crystal display device adopting the discharge circuit | |
| CN104835442A (en) | Shifting register and drive method thereof, gate drive circuit and display device | |
| US20110199397A1 (en) | Liquid crystal panel driving method, and source driver and liquid crystal display apparatus using the method | |
| CN102622983B (en) | Gate driving circuit of display | |
| TW200818086A (en) | Liquid crystal display for reducing residual image phenomenon and its related method | |
| CN100557668C (en) | Drive unit | |
| CN103325353A (en) | Level shifter for liquid crystal display | |
| CN101847382B (en) | Noise suppression device for reducing noise of liquid crystal display and liquid crystal display related thereto | |
| CN103794171A (en) | Display device and method for driving the same | |
| WO2019080600A1 (en) | Shutdown discharge circuit and related method, driving circuit and display device | |
| CN105047127A (en) | Shifting register unit, driving method, row scanning driving circuit and display device | |
| US20150123886A1 (en) | Gate driving circuit for display | |
| KR20090071024A (en) | Lcd driver ic and method for operating the same | |
| CN101996549A (en) | Start protection circuit for grid driver and liquid crystal display using same | |
| CN102770898B (en) | Source driver circuit of liquid crystal display device | |
| CN108648703B (en) | Display panel and display device | |
| CN104464645A (en) | Shifting register and display device | |
| CN1953030A (en) | Control circuit device and liquid crystal display with the same | |
| US7992063B2 (en) | Control circuit for releasing residual charges | |
| CN101527109B (en) | Flat panel display and drive method thereof | |
| CN106601207A (en) | Control circuit, source control circuit, driving method, and display device | |
| CN101452687A (en) | Liquid crystal driving device, and liquid crystal display device using same |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20120627 |