CN101841503A - Method for recovering sampling clock in VSB (Vestigial Sideband) modulating system - Google Patents
Method for recovering sampling clock in VSB (Vestigial Sideband) modulating system Download PDFInfo
- Publication number
- CN101841503A CN101841503A CN200910056962A CN200910056962A CN101841503A CN 101841503 A CN101841503 A CN 101841503A CN 200910056962 A CN200910056962 A CN 200910056962A CN 200910056962 A CN200910056962 A CN 200910056962A CN 101841503 A CN101841503 A CN 101841503A
- Authority
- CN
- China
- Prior art keywords
- sampling clock
- data
- signal
- modulating system
- vsb
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000005070 sampling Methods 0.000 title claims abstract description 52
- 238000000034 method Methods 0.000 title claims abstract description 24
- 238000004891 communication Methods 0.000 claims description 8
- 238000001914 filtration Methods 0.000 claims description 3
- 238000011084 recovery Methods 0.000 abstract description 6
- 238000004364 calculation method Methods 0.000 abstract 1
- 238000010586 diagram Methods 0.000 description 4
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 238000000205 computational method Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000012886 linear function Methods 0.000 description 1
- 238000004904 shortening Methods 0.000 description 1
- 238000001228 spectrum Methods 0.000 description 1
- 230000007704 transition Effects 0.000 description 1
Images
Landscapes
- Digital Transmission Methods That Use Modulated Carrier Waves (AREA)
Abstract
The invention discloses a method for recovering a sampling clock in a VSB (Vestigial Sideband) modulating system, which comprises the following steps of: carrying out carrier recovery and phase correction to an input signal to obtain a double symbol rate complex signal; multiplying the imaginary part of the double symbol rate complex signal and training data or hard decision data of sign bits thereof to produce a sampling clock deviation signal; recovering the sampling clocking using the sampling clock deviation signal and performing loop tracking. The method effectively shortens the recovery time of the sampling clock using auxiliary data and calculates the deviation of the sampling clock using the data of double symbol rate; thus, the invention can effectively reduce the complexity of a clock recovery calculation method, the difficulty of algorithm hardware implementation and the chip area.
Description
Technical field
The present invention relates to a kind of communication broadcast modulating system, the method that sampling clock recovers in particularly a kind of modulating system.
Background technology
Vestigial sideband modulation (VSB) is a kind of modulation system between single-side band modulation and double-sideband modulation, and it had both overcome the problem of DSB signal occupied bandwidth, has solved the difficult difficult problem that realizes of single sideband filter again.In vestigial sideband modulation, except transmitting a sideband, also kept the part of another one sideband.For the modulation signal with low frequency and DC component, the unlimited steep ideal filter of needed transition band no longer needs in vestigial sideband modulation when realizing single-side band modulation with filter method, and this has just been avoided the difficulty in the realization.
In the existing communication system, in order to improve spectrum efficiency, sampling clock does not transmit with data, but need recover sampling clock at receiving terminal, produces the sampling clock that is complementary with symbol rate, obtains optimum sampling point.Therefore in order to improve communication quality, good clock recovery algorithm is essential.
And in the system that adopts the VSB modulation, the sampling clock recovery algorithms mainly contains two kinds, and a kind of method is that the blind sampling of no auxiliary data recovers, and this method convergence rate is slow, restrains length consuming time.Another kind method is to use auxiliary data to adopt the character rate data of twice to carry out the calculating of sampling clock deviation simultaneously, and this method desired data amount is big, the algorithm complexity.
Summary of the invention
Technical problem to be solved by this invention provides the method that sampling clock in a kind of VSB modulating system recovers, the time that it can simple and effective shortening sampling clock recovers.
In order to solve above technical problem, the invention provides the method that sampling clock recovers in a kind of VSB modulating system; May further comprise the steps: input signal is carried out carrier wave recover and phasing, and obtain one times of character rate complex signal; The imaginary part of one times of character rate complex signal and training data or judgement data or their sign bit are multiplied each other, produce the sampling clock deviation signal; Utilize described sampling clock deviation signal that sampling clock is recovered and carry out loop tracks.
Beneficial effect of the present invention is, utilize auxiliary data effectively to shorten the time that sampling clock recovers, and the data that adopt one times of character rate are carried out sampling clock deviation and are calculated, can effectively reduce the complexity of clock recovery computational methods, reduce the difficulty that hardware algorithm is realized, reduce chip area.
Description of drawings
Below in conjunction with the drawings and specific embodiments the present invention is described in further detail:
Fig. 1 is the algorithm schematic diagram of the embodiment of the invention;
Fig. 2 is the schematic diagram of the embodiment of the invention in VSB modulation communication system receiver;
Fig. 3 realizes the schematic diagram that timing error detects with multiplier among the embodiment;
Fig. 4 is the pulse respond schematic diagram of matched filter.
Embodiment
As shown in Figure 1, at the VSB modulating system, according to a preliminary estimate or under the known condition, present embodiment may further comprise the steps in carrier frequency and phase place:
Earlier input signal being carried out carrier wave recovers and phasing, obtain one times of smaller character rate complex signal of phase deviation, perhaps obtain the sampled point of character rate more than 2 times or 2 times by interpolation filter, sampled point is through down-sampled again behind the matched filter, to one times of speed complex signal.
Utilize the imaginary part of one times of character rate complex signal and training data or hard decision data or their sign bit to multiply each other then, produce the sampling clock deviation signal; Perhaps earlier hard decision data is taken advantage of 2 or take advantage of other multiple to multiply each other with imaginary part again.
Utilize PHASE-LOCKED LOOP PLL TECHNIQUE to come sampling clock is accurately recovered and carries out loop tracks at last.
As shown in Figure 2, in concrete VSB modulation communication system receiver:
Input continuous time signal Ain becomes discrete-time signal Din through the over-sampling device, obtains the sampled point Sin of one times of character rate again by interpolation filter.Sin is through obtaining the complex signal Sc of one times of speed after the matched filtering, its real part and imaginary part are used Sc_real respectively, and Sc_imag represents.
Hard decision data Shd makes hard decision by the hard decision device to the real part Sc_real of one times of speed complex signal and obtains.Training data St is the predefined known data sequence of this communication system.Reference data Sp is selected the two by selection signal St_en and gets, and method is as follows:
When St_en=1, Sp=St;
When St_en=0, Sp=Shd;
As shown in Figure 3, Timing Error Detector adopts multiplier to realize, Sc_imag and Sp are multiplied each other obtains sampling clock deviation.For example: when training data exists, then multiply by imaginary part and ask sampling clock deviation, multiply each other with the result of data-signal hard decision and imaginary part if training data uses up and ask sampling clock deviation with training data.
The pulse respond of matched filter as shown in Figure 4, in the VSB system, wherein T is a symbol period.Suppose A (n) for sending signal, if clock sampling point is entirely true promptly in the nT moment, then the signal A ' after the matched filtering (n)=A (n).If sampling clock deviation is Δ t, then A ' (n)=A '
r(n)+j*A '
i(n).
When Δ t is smaller, can think A '
i(n)=f (sin (Δ t)) is the once linear function of Δ t, promptly thinks A '
i(n)=K*A (n) * Δ t.
If reference signal is training data then St=A (n), if to A '
r(n) do hard decision Shd=A (n) is arranged equally.
So have: Sp*Sc_imag=A (n) * A '
i(n)=K*A (n)
2* Δ t=f (Δ t);
E(f(Δt))＝E[K*A(n)
2*Δt]＝K*E[A(n)
2]*Δt＝C*Δt
Through behind the loop filter, give digital controlled oscillator (NCO) with its compensation.Digital controlled oscillator will carry out the adjustment of sampling time point in the adjusted sampled point input interpolation filter.So just constitute a complete sampling clock and recovered loop.
More than, the present invention is had been described in detail, but these are not to be construed as limiting the invention by embodiment.Under the situation that does not break away from the principle of the invention, those skilled in the art also can make many distortion and improvement, and these also should be considered as protection scope of the present invention.
Claims (10)
1. the method that sampling clock recovers in the VSB modulating system; It is characterized in that, may further comprise the steps:
Input signal is carried out carrier wave recover and phasing, and obtain one times of character rate complex signal;
The imaginary part of one times of character rate complex signal and training data or judgement data or their sign bit are multiplied each other, produce the sampling clock deviation signal;
Utilize described sampling clock deviation signal that sampling clock is recovered and carry out loop tracks.
2. the method that sampling clock recovers in the VSB modulating system as claimed in claim 1 is characterized in that,
Obtain the sampled point of one times of character rate by interpolation filter, sampled point obtains described one times of speed complex signal through after the matched filtering.
3. the method that sampling clock recovers in the VSB modulating system as claimed in claim 1 is characterized in that,
By decision device the real part of one times of speed complex signal is done judgement and obtain adjudicating data Shd;
Training data St is a communication system predefined data sequence;
By selecting signal St_en that aforementioned training data or judgement data are selected.
4. the method that sampling clock recovers in the VSB modulating system as claimed in claim 3 is characterized in that, with multiplier will described one times of character rate complex signal imaginary part and training data or adjudicate data and multiply each other and obtain sampling clock deviation.
5. the method that sampling clock recovers in the VSB modulating system as claimed in claim 1 is characterized in that,
The sampling clock deviation signal is through behind the loop filter, and digital controlled oscillator is given in compensation, and digital controlled oscillator will carry out the adjustment of sampling time point in the adjusted sampled point input interpolation filter.
6. the method that sampling clock recovers in the VSB modulating system as claimed in claim 1 is characterized in that, utilizes phase-locked loop that sampling clock is recovered and carries out loop tracks.
7. the method that sampling clock recovers in the VSB modulating system as claimed in claim 1, it is characterized in that, obtain the sampled point of character rate more than 2 times or 2 times by interpolation filter, sampled point is through down-sampled again behind the matched filter, to one times of speed complex signal.
8. the method that sampling clock recovers in the VSB modulating system as claimed in claim 1 is characterized in that, will adjudicate data earlier and take advantage of 2 or take advantage of the multiple more than 2 to multiply each other with imaginary part again.
9. the method that sampling clock recovers in the VSB modulating system as claimed in claim 1 is characterized in that,
By decision device the real part of one times of speed complex signal is done judgement and obtain adjudicating data Shd;
Training data St is a communication system predefined data sequence;
By selecting signal St_en that the sign bit of aforementioned training data or the sign bit of judgement data are selected.
10. the method that sampling clock recovers in the VSB modulating system as claimed in claim 9, it is characterized in that with multiplier the sign bit of the sign bit of the imaginary part of described one times of character rate complex signal and training data or judgement data being multiplied each other obtains sampling clock deviation.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN200910056962.8A CN101841503B (en) | 2009-03-20 | 2009-03-20 | Method for recovering sampling clock in VSB (Vestigial Sideband) modulating system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN200910056962.8A CN101841503B (en) | 2009-03-20 | 2009-03-20 | Method for recovering sampling clock in VSB (Vestigial Sideband) modulating system |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN101841503A true CN101841503A (en) | 2010-09-22 |
| CN101841503B CN101841503B (en) | 2014-01-15 |
Family
ID=42744632
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN200910056962.8A Expired - Fee Related CN101841503B (en) | 2009-03-20 | 2009-03-20 | Method for recovering sampling clock in VSB (Vestigial Sideband) modulating system |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN101841503B (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102255864A (en) * | 2011-08-30 | 2011-11-23 | 豪威科技(上海)有限公司 | Low-complexity general sampling recovery method and device |
| CN106842248A (en) * | 2016-11-23 | 2017-06-13 | 西安电子科技大学昆山创新研究院 | A kind of new method for improving Beidou receiver timing locating speed |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100564836B1 (en) * | 1997-10-31 | 2006-03-30 | 톰슨 라이센싱 | Apparatus and method for use in a system for processing a received vestigial sidebandvsb modulated signal |
-
2009
- 2009-03-20 CN CN200910056962.8A patent/CN101841503B/en not_active Expired - Fee Related
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102255864A (en) * | 2011-08-30 | 2011-11-23 | 豪威科技(上海)有限公司 | Low-complexity general sampling recovery method and device |
| CN102255864B (en) * | 2011-08-30 | 2013-05-29 | 豪威科技(上海)有限公司 | Low-complexity general sampling recovery method and device |
| CN106842248A (en) * | 2016-11-23 | 2017-06-13 | 西安电子科技大学昆山创新研究院 | A kind of new method for improving Beidou receiver timing locating speed |
Also Published As
| Publication number | Publication date |
|---|---|
| CN101841503B (en) | 2014-01-15 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN111343125B (en) | 32APSK modulation system receiver synchronization method | |
| CN102164031B (en) | Link clock recovery method and device | |
| US6985549B1 (en) | Blind cost criterion timing recovery | |
| EP1112648B1 (en) | A system and method for sending and receiving data signals over a clock signal line | |
| CA2484281C (en) | Clock timing recovery methods and circuits | |
| CN111600823B (en) | Parallel OQPSK offset quadriphase shift keying demodulator | |
| CN106656168B (en) | Clock data recovery device and method | |
| WO1998012835A1 (en) | Symbol timing recovery based on complex sample magnitude | |
| US9621381B2 (en) | Communication apparatus and method for high efficiency satellite service | |
| CN105515639A (en) | Universal satellite high-speed data transmission signal timing synchronization method | |
| JP4224152B2 (en) | Symbol timing recovery apparatus and method | |
| JP5582140B2 (en) | Receiving apparatus and demodulation method | |
| CN101841503B (en) | Method for recovering sampling clock in VSB (Vestigial Sideband) modulating system | |
| US8774321B2 (en) | Clock data recovery circuit and clock data recovery method | |
| CN101854320B (en) | Estimating and correcting device of sampling clock in VSB (Vestigial Sideband) modulation system | |
| CN101795250A (en) | Demodulation method and device of D8PSK (differential 8-ary phase shift keying) modulation signals of VDL (VHF (very high frequency) digital link) communication system | |
| EP1334594A2 (en) | Apparatus and method for sending and receiving data signals over a clock signal line by pulse width modulation | |
| US9426016B2 (en) | Self track scheme for multi frequency band serializer de-serializer I/O circuits | |
| US8218702B2 (en) | System and method of adapting precursor tap coefficient | |
| US5802113A (en) | Clock signal recovery system for communication systems using quadrature amplitude modulation | |
| CN101521641A (en) | Carrier recovery system and carrier recovery method | |
| KR20040046168A (en) | Symbol timing synchronous apparatus and method, and symbol Timing recovery apparatus for multi-level modulation scheme | |
| US5917869A (en) | Apparatus and method for timing/carrier recovery in bandwidth-efficient communications systems | |
| JPH0548975B2 (en) | ||
| Cao et al. | An All-Digital, High Data-Rate Parallel OQPSK Demodulator for Very Low SNR Signals |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| ASS | Succession or assignment of patent right |
Owner name: ATHEROS COMMUNICATION TECHNOLOGY (SHANGHAI) CO., L Free format text: FORMER OWNER: TIANJI MICROCHIP (BEIJING) TECHNOLOGY CO., LTD. Effective date: 20101203 Free format text: FORMER OWNER: OPULAN TECHNOLOGIES CO., LTD. |
|
| C41 | Transfer of patent application or patent right or utility model | ||
| COR | Change of bibliographic data |
Free format text: CORRECT: ADDRESS; FROM: 100124 ROOM 1228, COMPREHENSIVE BUILDING, NO.100, PINGLEYUAN, CHAOYANG DISTRICT, BEIJING TO: 201203 4/F, BUILDING 9, NO.690, BIBO ROAD, ZHANGJIANG, PUDONG NEW DISTRICT, SHANGHAI |
|
| TA01 | Transfer of patent application right |
Effective date of registration: 20101203 Address after: 201203, Shanghai, Pudong New Area Zhangjiang Road, No. 690, No. 9, building 4 Applicant after: Creative communications technology (Shanghai) Co., Ltd. Address before: 100124, Beijing, Chaoyang District Ping paradise, building 1228, room 100 Applicant before: Opulan Technologies Corp. Co-applicant before: Atheros Communications (Shanghai) Co., Ltd. |
|
| C53 | Correction of patent for invention or patent application | ||
| CB02 | Change of applicant information |
Address after: 201203, Shanghai, Pudong New Area Zhangjiang Road, No. 690, No. 9, building 4 Applicant after: Qualcomm Atheros, Inc. Address before: 201203, Shanghai, Pudong New Area Zhangjiang Road, No. 690, No. 9, building 4 Applicant before: Creative communications technology (Shanghai) Co., Ltd. |
|
| COR | Change of bibliographic data |
Free format text: CORRECT: APPLICANT; FROM: ATHEROS COMMUNICATION TECHNOLOGY (SHANGHAI) CO., LTD. TO: QUALCOMM ATHEROS ENTERPRISE MANAGEMENT (SHANGHAI) CO., LTD. |
|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20140115 Termination date: 20160320 |
|
| CF01 | Termination of patent right due to non-payment of annual fee |