CN101841230B - Zero voltage switching DC-DC power tube drive circuit based on double delay chain phase-locked loop - Google Patents

Zero voltage switching DC-DC power tube drive circuit based on double delay chain phase-locked loop Download PDF

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CN101841230B
CN101841230B CN2010101375529A CN201010137552A CN101841230B CN 101841230 B CN101841230 B CN 101841230B CN 2010101375529 A CN2010101375529 A CN 2010101375529A CN 201010137552 A CN201010137552 A CN 201010137552A CN 101841230 B CN101841230 B CN 101841230B
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voltage
delay chain
locked loop
phase
controlled delay
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CN101841230A (en
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田鑫
刘祥昕
皮常明
李文宏
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Fudan University
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Fudan University
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    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02BCLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
    • Y02B70/00Technologies for an efficient end-user side electric power management and consumption
    • Y02B70/10Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

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Abstract

The invention belongs to the electronic technical field and particularly relates to a zero voltage switching DC-DC power tube drive circuit based on double delay chain phase-locked loop. Zero voltage switching is the main technology used for increasing the efficiency of the synchronous rectification low voltage output buck DC-DC converter. The delay phase-locked loop has the advantages of ability of synchronizing signal, high precision and temperature drift resistance so that the delay phase-locked loop can be used as the zero voltage switching controller. The drive circuit adopts a voltage controlled delay chain 1 using a pseudo-current control inverter as the unit, a double voltage controlled delay chain structure 2 composed of a first voltage controlled delay chain and a second voltage controlled delay chain and a buffer capable of preventing negative dead-time. The invention solves the problem that the linearity of the pseudo-current control inverter is poor, designs the delay phase-locked loop which is applicable to zero voltage switching under the conditions of low power consumption and high linearity, and provides a good solution for zero voltage switching.

Description

Zero voltage switching DC-DC power tube drive circuit based on double delay chain phase-locked loop
Technical field
The invention belongs to electronic technology field, be specifically related to a kind of power tube drive circuit, be mainly used in the buck DC-DC transducer of synchronous rectification low voltage output.
Background technology
Synchronous rectification buck DC-DC transducer is widely used in portable set because of its high efficiency.The topological structure of synchronous rectification buck DC-DC transducer is as shown in Figure 1.M PAnd M NBe respectively to go up trombone slide and following trombone slide, D NBe M NParasitic body diode, L is a filter inductance, C is an output capacitance, I OBe output loading, V DDAnd V OBe respectively input voltage and output voltage, V PMAnd V NMBe respectively M PAnd M NThe grid drive signal, V SWBe M PAnd M NCommon drain terminal voltage.For fear of M PAnd M NConducting simultaneously causes power supply to arrive the short circuit on ground, and they will insert one section delay and be called Dead Time between the conducting region, and considers reason such as process deviation, sets longlyer usually during this period of time, more than 10ns.Work as V PMTurn-off and V NMAs yet not conducting the time, in order to keep inductive current, V SWCan be gradually descend, until drop to-make body diode D about 0.7V NConducting is until M NConducting is as shown in Figure 2, t ERRORBe D NThe time of conducting, interior during this period of time electric current is at D NOn can consume bigger energy.If at V SWReduce to 0 o'clock M NJust conducting just can be eliminated this part unnecessary energy consumption, and Here it is has realized so-called Zero voltage transition, and Dead Time is at this moment optimized Dead Time exactly.Optimize Dead Time according to the output loading real-time change, therefore need certain control circuit to realize.
Delay phase-locked loop has the ability of synchronizing signal, and precision is high, and temperature resistance floats, and can realize Zero voltage transition.Yet the voltage-controlled delay chain in traditional delay phase-locked loop often uses comparator as elementary cell, and comparator consumes quiescent dissipation, aspect low-power consumption, has weakness.The voltage-controlled delay chain structure of pseudo-Current Control inverter has only dynamic power consumption, but the linearity is relatively poor, is difficult to realize the delay of wide variation.The present invention uses the elementary cell of pseudo-Current Control inverter as the voltage-controlled delay chain of delay phase-locked loop, has reduced the power consumption of delay phase-locked loop; Adopt the double delay chain structure simultaneously, solved the problem of the poor linearity of pseudo-Current Control inverter, make delay phase-locked loop that very fast lock speed all arranged under each quiescent point.
Summary of the invention
The objective of the invention is to propose a kind of drive circuit of realizing the Zero voltage transition of buck DC-DC transducer with the delay phase-locked loop of low-power consumption; Be fully loaded with to unloaded scope; Can both adjust Dead Time in real time, realize Zero voltage transition, promote the efficient of DC-DC transducer.
The present invention uses the voltage-controlled delay chain 1 of pseudo-Current Control inverter as the unit, the double pressure-controlled delay chain structure 2 that is made up of the first and second voltage-controlled delay chains and prevent the buffer 3 of negative Dead Time.
The structure that is applied to the double delay chain delay phase-locked loop that DC-DC conversion grid drives is as shown in Figure 3.Zero voltage switching DC-DC power tube drive circuit based on the double delay chain delay phase-locked loop comprises phase discriminator and charge pump, overstates the last trombone slide M that leads amplifier, the first voltage-controlled delay chain and the second voltage-controlled delay chain, first inductor and second inductor, DC-DC transducer PWith following trombone slide M N, and start-up circuit.
Start-up circuit forms signal En0 to control signal En after treatment, and signal En0 is through control phase discriminator and charge pump and overstate that leading amplifier comes the startup of control lag phase-locked loop and close.V PWMBe square wave, through forming signal V behind the first voltage-controlled delay chain and the second voltage-controlled delay chain with certain phase difference with certain duty ratio PM0And V NM0, signal V PM0And V NM0Amplify driving force through buffer, obtain signal V PMAnd V NMFirst inductor and second inductor are adopted V respectively SWTrailing edge and V NMRising edge, obtain signal phase1 and phase2.Phase discriminator and charge pump change into control voltage V with differing of phase1 and phase2 CTR, overstate and lead amplifier control voltage V CTRConvert difference current to, and form two groups of bias voltages, wherein one group of bias voltage V UP1With V DN1Be input to the first voltage-controlled delay chain, and another group bias voltage V UP2With V DN2Be input to the second voltage-controlled delay chain.When signal phase1 leads over signal phase2; The output voltage of phase discriminator and charge pump reduces, and overstates and leads amplifier through the adjustment bias voltage, and the delay and second that increases the first voltage-controlled delay chain simultaneously reduces the delay of voltage-controlled delay chain; Signal phase1 is lagged behind; Signal phase1 adjusts, until phase1 and phase2 homophase in advance so step by step.And, is complementary the time of delay of first inductor and second inductor, like this V through reasonably design SWTrailing edge and V NMRising edge also with homophase.Waveform is as shown in Figure 4, t 1And t 2Be respectively V SWTrailing edge and V NMThe time point of rising edge, t 1' and t 2' be respectively the rising edge time point of the output signal of first inductor and second inductor, Δ t 1With Δ t 2It is respectively the time of delay of first inductor and second inductor, if t is arranged 1'=t 2' and Δ t 1=Δ t 2, t is just arranged 1=t 2, promptly realized Zero voltage transition.
The elementary cell that adopts pseudo-Current Control inverter to adopt as the voltage-controlled delay chain has only dynamic power consumption.But the linearity of its transfer function is relatively poor, and the present invention adopts the double delay chain structure, and the delay difference of using two delay chains has overcome the shortcoming of the poor linearity of pseudo-Current Control inverter as Dead Time.Because Dead Time is that postpone difference therefore possibly be negative value, promptly goes up trombone slide and the conducting simultaneously of following trombone slide, in order to stop this accident generation fully, in the buffer through minimum Dead Time of certain control dictate.
Description of drawings
Fig. 1 is the topological structure of synchronous rectification buck DC-DC transducer.
Fig. 2 is the waveform diagram of Zero voltage transition.
The sketch map that Fig. 3 uses in the buck DC-DC transducer for the grid drive circuit.
Fig. 4 realizes the schematic diagram of Zero voltage transition for delay phase-locked loop.
Fig. 5 leads amplifier and pseudo-Current Control inverter circuit figure for overstating in the delay phase-locked loop.
Fig. 6 (a) (b) is respectively the voltage-delay relation curve of single delay chain and double delay chain.
Fig. 7 is buffer circuits figure.
Embodiment
Below in conjunction with accompanying drawing and instance the present invention is described in more detail.
The principle of realization Zero voltage transition is set forth.Pseudo-Current Control inverter with overstate that the structure of leading amplifier is as shown in Figure 5, the part on the left side is to overstate the equivalent schematic of leading amplifier, the part on the right is the delay chain that pseudo-Current Control inverter forms, metal-oxide-semiconductor M UP1, M 1, M 2And M DN1Constitute the unit of a pseudo-Current Control inverter, metal-oxide-semiconductor M 1And M 2Grid end input high level or low level, their common drain terminal output high level or low level, and the speed that the high-low level signal transmits is depended on metal-oxide-semiconductor M UP1And M DN1Gate voltage control.Among the figure altogether picture two elementary cells, unit number can be adjusted.V CTRBe to overstate the input voltage of leading amplifier, also can be described as the control voltage that voltage-controlled delay connects, V 0Be the dc point of overstating the input voltage of leading amplifier, g mBe to overstate that leading overstating of amplifier leads, at V CTRControl forms Control current I down CTR, I CTR0Be to overstate the I that leads amplifier CTRDc point, metal-oxide-semiconductor M UPAnd M DNGrid leak link to each other to form and I CTRRelevant bias voltage metal-oxide-semiconductor V UPAnd V DN, be input to metal-oxide-semiconductor M UP1, M UP2, M DN1, M DN2The grid end, input and output are respectively the square-wave signals that need to postpone and have passed through the square-wave signal that postpones.Such structure makes only consumed energy just when the upset of the level of input of circuit, and postpones also can be controlled, device structure relatively, and power consumption but reduces greatly.
Yet, if use wall scroll voltage-controlled delay chain, from the linearity of the transfer function that controls voltage to delay and bad.What Fig. 6 (a) showed is the simulation curve of the voltage-delay relation of wall scroll voltage-controlled delay chain.Can see that only to change the linearity of controlling voltage-delay under the situation about 3 times in time of delay very poor; Roughly is inversely prroportional relationship from Control current to the transfer function that postpones; In conjunction with from controlling voltage to the transfer function of Control current, Dead Time can be expressed as:
t d = K 1 I CTR = K 1 I CTR 0 + g m ( V CTR - V 0 ) - - - ( 1 )
T wherein dBe Dead Time, K 1It is a constant.The variation of Dead Time needs more than ten times (ns more than the 1ns to ten) usually, and the linearity of under such condition, controlling voltage-Dead Time relation is poorer.The residue module of loop all has the favorable linearity transfer function, so the gain of loop will become non-constant.Based on the delay phase-locked loop principle, loop gain greatly then responds soon, has overshoot but surpass at 1 o'clock, surpasses 2 o'clock instabilities.If will guarantee that loop is stable at the maximum gain place, then loop can be very slow at the lock speed at least gain place.The present invention has used delay difference that the structure of double delay chain utilizes two voltage-controlled delay chains as Dead Time, and Dead Time can be expressed as:
t d = K 1 I CTR 0 + g m ( V CTR - V 0 ) - K 2 I CTR 0 - g m ( V CTR - V 0 )
= ( K 1 - K 2 ) I CTR 0 - ( K 1 + K 2 ) g m ( V CTR - V 0 ) I CTR 0 2 - g m ( V CTR - V 0 ) 2 - - - ( 2 )
K in the formula (2) 1And K 2Be constant, I CTR0+ g m(V CTR-V 0) and I CTR0-g m(V CTR-V 0) be respectively the Control current of the first voltage-controlled delay chain and the second voltage-controlled delay chain 2.Only from expression parsing; Formula (2) is well more a lot of than the linearity of formula (1); And can realize that theoretically the delay from Ons to any time, maximum delay are infinite many times of minimum delay, only need increase unit number and increase maximum delay; This does not influence the linear of control voltage-Dead Time, and through being that two delay chains are set different unit number-be equivalent to adjust K 1And K 2Size-can regulate the dc point of Dead Time.What Fig. 6 (b) showed is the simulation relation curve of the voltage-Dead Time of double delay chain, and simulation result has also shown the improvement of double delay chain structure aspect the linearity.Because what emulation was used is the delay chain of same unit number, so the direct current of Dead Time is about Ons, and negative maximum approximates positive maximum.
The circuit of buffer is as shown in Figure 7.M 1Be PMOS, M 2, M 3Be NMOS, M 1And M 2Drain terminal join M 2Source end and M 3Drain terminal join M 1And M 3The grid termination need amplify the primary signal V of the last trombone slide drive signal of driving force PM0, M 2Grid termination V NMThe negate signal, so this grade output level receives V by height to low upset NMControl is only at V NMOutput level just can be by height to low upset during for low level.Be the inverter module that even number increases step by step afterwards, obtain the drive signal V of trombone slide after driving force is amplified PM, like this from V NMTrailing edge to V PMTrailing edge just stagger by force one section and postpone, delay is exactly that signal is from M 2The grid end pass to V PMThe needed time.
Same principle, M 4, M 5Be PMOS, M 6Be NMOS, M 5And M 6Drain terminal join M 5Source end and M 4Drain terminal join M 4And M 6The grid termination need amplify the primary signal V of the following trombone slide drive signal of driving force NM0, M 5Grid termination V PMThe negate signal, so this grade output level receives V by low to high tumble PMControl is only at V PMOutput level can be the inverter module that even number increases step by step by low to high tumble afterwards just during for high level, obtains the drive signal V of trombone slide after driving force is amplified NM, like this from V PMRising edge to V NMRising edge just stagger by force one section and postpone, delay is exactly that signal is from M 5The grid end pass to V NMThe needed time.

Claims (1)

1. the power tube drive circuit based on the Zero voltage switching DC-DC transducer of double delay chain phase-locked loop is characterized in that this drive circuit comprises phase discriminator and charge pump, overstates the last trombone slide M that leads amplifier, the first voltage-controlled delay chain and the second voltage-controlled delay chain, first inductor and second inductor, DC-DC transducer PWith following trombone slide M N, and start-up circuit; Start-up circuit forms signal En0 to control signal En after treatment, and signal En0 is through control phase discriminator and charge pump and overstate that leading amplifier controls the startup of double delay chain phase-locked loop and close; V PWMBe square wave, through forming signal V behind the first voltage-controlled delay chain and the second voltage-controlled delay chain with certain phase difference with certain duty ratio PM0And V NM0, signal V PM0And V NM0Amplify driving force through buffer, obtain signal V PMWith NMFirst inductor and second inductor are adopted V respectively SWTrailing edge and V NMRising edge, obtain signal phase1 and phase2, V SWBe to go up trombone slide M PWith following trombone slide M NCommon drain terminal voltage; Phase discriminator and charge pump change into control voltage V with differing of phase1 and phase2 CTR, overstate and lead amplifier control voltage V CTRConvert difference current to, and form two groups of bias voltages, wherein one group of bias voltage V UP1With V DN1Be input to the first voltage-controlled delay chain, and another group bias voltage V UP2With V DN2Be input to the second voltage-controlled delay chain.
CN2010101375529A 2010-04-01 2010-04-01 Zero voltage switching DC-DC power tube drive circuit based on double delay chain phase-locked loop Expired - Fee Related CN101841230B (en)

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CN103066990B (en) * 2013-01-16 2016-03-09 南通大学 A kind of output unit circuit based on integrated circuit
CN107659300B (en) * 2013-06-17 2021-08-27 英飞凌科技股份有限公司 Circuit arrangement and method for bidirectional data transmission
CN104333366B (en) * 2014-10-30 2018-04-27 深圳市国微电子有限公司 A kind of Digital I/O Circuit
CN106953507B (en) * 2017-05-04 2019-06-25 广州金升阳科技有限公司 A kind of buck converter synchronous rectification driving circuit and control method
CN107124166B (en) * 2017-05-25 2019-07-23 西安交通大学 A kind of low-power consumption high speed Zero Current Switch

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