CN101840883A - Forming method of copper film - Google Patents
Forming method of copper film Download PDFInfo
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- CN101840883A CN101840883A CN200910047646A CN200910047646A CN101840883A CN 101840883 A CN101840883 A CN 101840883A CN 200910047646 A CN200910047646 A CN 200910047646A CN 200910047646 A CN200910047646 A CN 200910047646A CN 101840883 A CN101840883 A CN 101840883A
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- copper film
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Abstract
The invention relates to a forming method of a copper film, comprising the following steps of implementing a first electroplating step to form the copper film with a first thickness on a surface needing to form the copper film; implementing a first annealing step on the formed copper film with the first thickness; implementing a second electrodeposition step to continuatively form a copper film on the surface of the formed copper film until reaching the required thickness of the formed copper film; and implementing a second annealing step on the formed copper film, wherein the first electroplating step has the same conditions as the second electroplating step. The invention has the advantage that the forming method of the copper film improves the condition of warpage deformation of wafers.
Description
Technical field
The present invention relates to field of semiconductor manufacture, particularly copper film formation method in the postchannel process of semiconductor manufacturing.
Background technology
At present, the device in mixed signal radio frequency (MS/RF) circuit need be applied to super thick metal (UTM, Ultra Thick Metal) technology.For example, (ECP, Electro-CopperPlating) technology forms the thick copper film of for example about 3 μ m by electro-coppering.Described copper plating process generally comprises: form the copper film of the surface of copper film by electric plating method formation design thickness at needs, anneal then.
At for example application number is to find the relevant information of more and above-mentioned copper plating process in 200580019070.0 the Chinese patent application.
Yet along with the widespread usage of large scale wafer, the problem that super thick smithcraft is brought thereupon is also more and more obvious.For example, for the 300mm wafer that is applied to 90nm technology that nowadays often adopts, because the copper film has bigger tensile stress (Tensile Stress), for example the tensile stress of copper film has reached 280Mpa in the 90nm technology, therefore, the copper film that thickness is bigger can make wafer produce buckling deformation.Wherein, more serious silicon wafer warpage distortion, its warpage maximum (bow), i.e. depth displacement during buckling deformation between the wafer highs and lows, even reached about 300 μ m, almost near a half thickness of wafer.And the distortion of described silicon wafer warpage may cause wafer to be scrapped in subsequent technique, for example produce wafer and break in the wafer reverse side grinding process of follow-up packaging technology, or wafer will be considered as waste product by follow-up technology board and refuse to be written into.
Thereby, one of bottleneck of silicon wafer warpage distortion having become restriction large scale wafer (for example 300mm wafer) the postchannel process smooth implementation that described super thick smithcraft is brought.
Summary of the invention
What the present invention will solve is the problem that the super thick smithcraft of prior art makes the silicon wafer warpage distortion.
For addressing the above problem, the invention provides a kind of formation method of copper film, comprising:
On the surface of needs formation copper film, carry out the copper film that first plating step forms first thickness;
Copper film to established first thickness is carried out first annealing steps;
At established copper film surface, carry out second plating step and continue to form the copper film until reaching required copper film thickness;
Established copper film is carried out second annealing steps,
Wherein, the plating condition of first plating step and second plating step is identical.
Compared with prior art, the formation method of above-mentioned copper film has the following advantages: make the tensile stress of the copper film that formed thickness is bigger reduce by twice annealing, improved the situation of silicon wafer warpage distortion.
Description of drawings
Fig. 1 is a kind of execution mode flow chart of the formation method of copper film of the present invention;
Fig. 2 a to Fig. 2 d is the simple and easy schematic diagram of a kind of embodiment of the formation method of copper film of the present invention.
Embodiment
With reference to shown in Figure 1, a kind of execution mode of the formation method of copper film of the present invention comprises:
Step s1 on the surface of needs formation copper film, carries out the copper film that first plating step forms first thickness;
Step s2 carries out first annealing steps to the copper film of established first thickness;
Step s3 at established copper film surface, carries out second plating step and continues to form the copper film until reaching required copper film thickness;
Step s4 carries out second annealing steps to established copper film.
Wherein, the plating condition of first plating step and second plating step is identical.
Below further specify by the formation method of a concrete craft embodiment above-mentioned copper film.
Shown in Fig. 2 a, had logical device structure and corresponding multi-layer metal structure in the substrate 10, for example have in the substrate 10 except that top-level metallic other each layer metal interlevel structures and under the logical device structure.Also has conductive layer 11 in the described substrate 10.Described substrate 10 surfaces have etching stopping layer 12, also have insulating barrier 13 on the described etching stopping layer 12.Groove 14 connect described insulating barriers 13 and under etching stopping layer 12, be communicated with described conductive layer 11.Described groove 14 is for needing to form the place of copper film.Describe for convenient, suppose that the copper film of required formation should fill up groove 14 and neat high with the surface of described insulating barrier 13.Herein, the degree of depth of supposing described groove 14 is 3 μ m, and the thickness that also is the copper film of required formation is 3 μ m.
Then at first use electric plating method forms first thickness in described groove 14 copper film, for example form the copper film of 1.5 μ m.The electroplate liquid that copper ions is used in electro-coppering for example can adopt H
2SO
4, CuSO
4And CuCl
2Mixed solution, the electric current during plating can be for example 5 peaces (A), the temperature during plating is a room temperature, for example 25 ℃.
In above-mentioned electroplating process, copper is connected to the anode of power supply, substrate 10 is connected to the negative electrode of power supply, substrate 10 is soaked in the described electroplate liquid, and applies electric current by power supply, make copper ion in the electroplate liquid and electron reaction form copper and groove 14 in, deposit.
The copper film of described plating first thickness can be controlled by electroplating time, copper growth for Thin Film speed when the experiment of for example doing different electroplating times on not having the wafer of figure can obtain electroplating.Copper growth for Thin Film speed just can obtain electroplating time during then according to described first thickness and plating.
Shown in Fig. 2 b,, be formed with the copper film 15a of first thickness in the groove 14 through above-mentioned electro-coppering step.Then substrate 10 heating are annealed with the copper film 15a to formed first thickness.
Described annealing process can be carried out in the annealing boiler tube, and the temperature of described annealing can be for example 200 ℃.The time of described annealing decides the electrical requirement of formation copper film according to process specification, and for example the time of described annealing can be 100 seconds.
Shown in Fig. 2 c, continue to form the copper film on the copper film 15a surface of first thickness through annealing, adopt electric plating method equally.It is identical that the electroplate liquid that is adopted in this step, the electric current when electroplating and the temperature when electroplating adopt during all with the copper film 15a of above-mentioned formation first thickness.Described electroplating process lasts till that the copper film fills up groove 14 and neat high with the surface of described insulating barrier 13.
The thickness of copper film can be controlled by electroplating time when electroplated the above-mentioned second time, for example can obtain copper growth for Thin Film speed in the experiment that does not have to do different electroplating times on the wafer of figure.Then the thickness of the copper film of electroplating as required and when electroplating copper growth for Thin Film speed just can obtain electroplating time.
Shown in Fig. 2 d, after electroplating for the second time, the thickness of formed copper film 15 reaches 3 μ m in the groove 14.At last, once more to substrate 10 being heated so that formed copper film 15 is annealed.
Described annealing process can be carried out in the annealing boiler tube, and the temperature of described annealing can be 200 ℃.The time of described annealing decides the electrical requirement of formation copper film according to process specification, and for example the time of described annealing can be 100 seconds.
Below be respectively to after adopting art methods and the inventive method to form the copper film of same thickness, detect the silicon wafer warpage maximum, the contrast table as a result that is obtained.
Table 1
From table 1, can see, can see that by detection the distortion of adopting the copper film that forms after twice plating, twice annealing technology of the inventive method that wafer is caused is far smaller than the distortion that copper film that prior art forms same thickness causes wafer to 3 groups of different sample wafer.The warpage maximum of the inventive method dropped to substantially the warpage of art methods peaked half.
Therefore, the formation method of copper film of the present invention has been improved the situation of silicon wafer warpage distortion.
Though the present invention discloses as above with preferred embodiment, the present invention is defined in this.Any those skilled in the art without departing from the spirit and scope of the present invention, all can do various changes and modification, so protection scope of the present invention should be as the criterion with claim institute restricted portion.
Claims (9)
1. a copper film formation method is characterized in that, comprising:
On the surface of needs formation copper film, carry out the copper film that first plating step forms first thickness;
Copper film to established first thickness is carried out first annealing steps;
At established copper film surface, carry out second plating step and continue to form the copper film until reaching required copper film thickness;
Established copper film is carried out second annealing steps,
Wherein, the plating condition of first plating step and second plating step is identical.
2. copper film formation method as claimed in claim 1 is characterized in that described first thickness is half of required copper film thickness.
3. copper film formation method as claimed in claim 1 is characterized in that, the temperature when electric current the when electroplate liquid that adopts when described plating condition comprises plating, plating and plating.
4. copper film formation method as claimed in claim 3 is characterized in that, the electroplate liquid that described first plating step and second plating step adopt is H
2SO
4, CuSO
4And CuCl
2Mixed solution.
5. copper film formation method as claimed in claim 3 is characterized in that, described first plating step and second plating step electric current when electroplating is 5 peaces.
6. copper film formation method as claimed in claim 3 is characterized in that, described first plating step and second plating step temperature when electroplating is a room temperature.
7. copper film formation method as claimed in claim 6 is characterized in that described room temperature is 25 ℃.
8. copper film formation method as claimed in claim 1 is characterized in that the temperature of described first annealing steps is 200 ℃, and the time is 100 seconds.
9. copper film formation method as claimed in claim 1 is characterized in that the temperature of described second annealing steps is 200 ℃, and the time is 100 seconds.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2009100476464A CN101840883B (en) | 2009-03-16 | 2009-03-16 | Forming method of copper film |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2009100476464A CN101840883B (en) | 2009-03-16 | 2009-03-16 | Forming method of copper film |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN101840883A true CN101840883A (en) | 2010-09-22 |
| CN101840883B CN101840883B (en) | 2012-01-25 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2009100476464A Expired - Fee Related CN101840883B (en) | 2009-03-16 | 2009-03-16 | Forming method of copper film |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105810557A (en) * | 2014-12-31 | 2016-07-27 | 格科微电子（上海）有限公司 | Semiconductor wafer, flattening method therefor, and packaging method |
| CN112435959A (en) * | 2020-11-20 | 2021-03-02 | 长江存储科技有限责任公司 | Semiconductor device and method for manufacturing the same |
| CN112899735A (en) * | 2014-03-19 | 2021-06-04 | 应用材料公司 | Electrochemical plating method |
-
2009
- 2009-03-16 CN CN2009100476464A patent/CN101840883B/en not_active Expired - Fee Related
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112899735A (en) * | 2014-03-19 | 2021-06-04 | 应用材料公司 | Electrochemical plating method |
| CN105810557A (en) * | 2014-12-31 | 2016-07-27 | 格科微电子（上海）有限公司 | Semiconductor wafer, flattening method therefor, and packaging method |
| CN112435959A (en) * | 2020-11-20 | 2021-03-02 | 长江存储科技有限责任公司 | Semiconductor device and method for manufacturing the same |
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| Publication number | Publication date |
|---|---|
| CN101840883B (en) | 2012-01-25 |
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