CN101835186A - Detection method and detection device of misconnection of Yuanyang lines and base station subsystem - Google Patents
Detection method and detection device of misconnection of Yuanyang lines and base station subsystem Download PDFInfo
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Abstract
The invention provides a detection method and a detection device of misconnection of Yuanyang lines and a base station subsystem. The method comprises the following steps: test data is written in a sending buffer of the Yth time slot for transmitting data in an E1/T1 link X1, wherein the E1/T1 link X1 is an E1/T1 link with the number of X1, and the test data corresponds to the X1; the sending buffer sends the test data to the opposite terminal through the Yth time slot of the link X1 of an E1/T1 chip; and a receiving buffer of the E1/T1 link X1 receives the data of the Yth time slot returned from the opposite terminal through the link X1 of the E1/T1 chip, wherein if the data of the Yth time slot returned from the opposite terminal corresponds to the number of an E1/T1 link X2, the E1/T1 link X1 and the E1/T1 link X2 have misconnection of Yuanyang lines. The scheme provided by the invention can conveniently detect whether misconnection of Yuanyang lines exists or not.
Description
Technical field
The present invention relates to the communications field, particularly E1/T1 crossed pair misconnection detection technique.
Background technology
At present, between base station and the base station controller, often adopt the E1/T1 link to connect.E1 is the bandwidth rates standard of the pulse code modulation multiplex system digital hierarchy primary group (or claiming the mirror group) in Europe, and it comprises the channel of 32 64kbit/s, and the bandwidth rates of primary group is 2.048Mbit/s.The frame length of an E1 is 256 bit, is divided into 32 time slots, and a time slot is 8 bit.Per second has the frame of 8k E1 by interface, i.e. 8K*256=2048kbps.Each time slot accounts for 8bit in the E1 frame, 8*8k=64k promptly contains 32 64K among an E1.In the HDLC transmission means, E1 has two frames and CRC multi-frame, is used for the transmission frame synchronizing signal at basic frame 0 time slot of E1, and all the other 31 time slots can be used for transfer of data.
T1 and E1 are similar, be a kind of pulse code modulation multiplex system digital hierarchy primary group bandwidth rates standard of (or claiming the mirror group), different is that it is the standard of North America, Japan, comprise 24 telephone channels (each channel is 64kbit/s), bandwidth rates is 1.544Mbit/s.
Article one, the E1/T1 link divides the physical link that receives and send both direction, and the crossed pair misconnection is meant that many circuit transmitting-receiving lines connect the situation of entanglement.For example, as shown in Figure 1, the reception (RX) that No. 2, the transmission of E1/T1 link 1 (TX) and opposite end link is docked, and the RX of link 1 docks with the TX of the link of opposite end 1.
Under crossed pair misconnection situation, with nowhere to turn to the police, but business can't normal operation, influences bigger on the surface.
Part producer proposes to insert data and transmits on the E1/T1 chip, in the opposite end loopback is set, and the data that detect loopback determine whether to exist the crossed pair misconnection.
The inventor finds that this scheme can only be applicable to the situation that the E1/T1 number of links is less, and can not be applicable to the situation that the E1/T1 number of links is more.
Summary of the invention
In view of this, an aspect of of the present present invention provides a kind of crossed pair misconnection detection method, can the crossed pair misconnection whether occur by offline inspection E1/T1 link, and this method comprises:
The transmission buffer memory that is used for transmitting the Y time slot of data at E1/T1 link X1 writes test data, and described E1/T1 link X1 is an E1/T1 link that is numbered X1, and described test data is corresponding to described X1;
Described transmission buffer memory sends described test data by the Y time slot of the link X1 of E1/T1 chip to the opposite end;
The reception buffer memory of described E1/T1 link X1, receive the data of the Y time slot of described opposite end loopback by the link X1 of described E1/T1 chip, if the data of the Y time slot of described opposite end loopback are corresponding to the numbering of E1/T1 link X2, there are the crossed pair misconnection in then described E1/T1 link X1 and described E1/T1 link X2.
Another aspect of the present invention provides a kind of, crossed pair misconnection checkout gear, and described device links to each other with the E1/T1 chip, and described device comprises:
Send cache module, be used to write test data, the Y time slot of the link X1 by the E1/T1 chip sends test data to the opposite end, and described test data is corresponding to described X1;
Receive cache module, be used for receiving the data of the Y time slot of described opposite end loopback by the link X1 of described E1/T1 chip, if the data of the Y time slot of described opposite end loopback are corresponding to the numbering of E1/T1 link X2, there are the crossed pair misconnection in described E1/T1 link X1 and described E1/T1 link X2.
Another aspect of the present invention provides a kind of base station sub-system, comprises above-mentioned device.
Above-mentioned method, device and base station sub-system, whether offline inspection exists the crossed pair misconnection easily.
Description of drawings
Fig. 1 is the connected mode of existing crossed pair among the E1;
Fig. 2 is the method flow schematic diagram that detects the crossed pair misconnection;
Fig. 3 is the apparatus structure schematic diagram that detects the crossed pair misconnection;
Fig. 4 is another crossed pair misconnection checkout gear structural representation;
Fig. 5 is the structural representation that comprises the base station sub-system of crossed pair misconnection checkout gear.
Embodiment
For making the purpose, technical solutions and advantages of the present invention clearer, the present invention is described in further detail below in conjunction with accompanying drawing.
In an embodiment of the present invention, E1/T1 refers to E1 or T1, and the E1/T1 link refers to E1 link or T1 link, and E1/T1 link X1 represents to be numbered the E1/T1 link of X1, and the Y time slot is represented Y time slot.
As an example, present embodiment provides a kind of offline inspection E1/T1 crossed pair misconnection detection method, sees also Fig. 2, and this method comprises the steps:
Step S201, the transmission buffer memory that is used for transmitting the Y time slot of data at E1/T1 link X1 writes test data.
The time slot of E1/T1 link all has corresponding transmission buffer memory, writes test data in the pairing transmission buffer memory of Y time slot.Send buffer memory and link to each other, can send data to the opposite end by the E1/T1 chip with the E1/T1 chip.Wherein, E1 can have 32 time slots, and time slot 0 is used for the transmission frame synchronizing signal, therefore is not useable for writing test data, and remaining 31 time slot for being used to transmit the time slot of data, can write test data; And for T1, arbitrary time slot of time slot 1-time slot 24 can be used to write test data.
This test data is corresponding to the numbering X1 of this E1/T1 link, for example, if this E1/T1 link be numbered 2, then this test data can be 2, perhaps with 2 numerals that have an one-to-one relationship.
The data format that inserts can adopt signless integer type (Unsigned Int), and the position is long can be 8 bits, also can be 16 bits.
S202, the Y time slot of the link X1 by the E1/T1 chip sends described test data to the opposite end.
Can there be a plurality of links in an E1/T1 chip, sends the Y time slot of buffer memory by the link X1 of E1/T1 chip, and test data is sent to the opposite end.
S203 receives buffer memory receives the Y time slot of opposite end loopback by the link X1 of E1/T1 chip data.
By configuration order, all E1/T1 links are set to remote loopback, and the opposite end is after receiving data, and the link X1 of the E1/T1 chip by the opposite end is transmitted to transmit leg with the test data that receives by the Y time slot.
Receive buffer memory, receive the data of the Y time slot of opposite end loopback, if then there is the crossed pair misconnection in the data of obtaining from the Y time slot between the X2 of E1/T1 link X1 and E1/T1 link corresponding to the numbering of E1/T1 link X2 by the link X1 of E1/T1 chip.
Further, normal if the data that step S203 obtains, can judge then that E1/T1 link X1 connects corresponding to the numbering X1 of the tested E1/T1 link of step S201.
Further, if the bit of Y time slot is 8, the data that step S203 obtains are default value " 0xff ", then can occur opening circuit by the tested E1/T1 link X1 of determining step S201; Perhaps, if the bit of Y time slot is 16, the data that step S203 obtains are default value " 0xffff ", then can the tested E1/T1 link X1 existence of determining step S201 open circuit.
The method that present embodiment provides, the time slot that writes test data is the E1/T1 time slot of transmission data, and available bit number is more, and the test data that can support is also with more, thereby can support a fairly large number of E1/T1 link is tested.For example, 8 bits are arranged, then can be used to represent 256 different test datas in theory, support the E1/T1 link of measuring to reach 255 (all are 1 can be used for representing situation about opening circuit) if write in the time slot of test data.
Further, the method that present embodiment provides, send test data by E1/T 1 chip time slot corresponding again after in sending buffer memory, inserting data, adopt the reception buffer memory from time slot corresponding, to receive data, avoid the E1/T1 chip directly to insert data, receive the data-bias that data produced by the E1/T1 chip.
Further, the method that present embodiment provides after finding that there is the crossed pair misconnection in the E1/T1 link, can also be determined the numbering of the E1/T1 link of generation misconnection according to test signal, thus the connected mode that corrects mistakes.
Further, the method that present embodiment provides can also be supported simultaneously multichannel E1/T1 link to be carried out offline inspection.
Another embodiment of the present invention provides a kind of crossed pair misconnection checkout gear, can be used for the method that realizes that the foregoing description provides.The crossed pair misconnection checkout gear that present embodiment provides links to each other with the E1/T1 chip, and the E1/T1 chip links to each other with the opposite end by the E1/T1 link, and this E1/T1 link can be a coaxial cable, also can be optical fiber.
The E1/T1 chip is mainly realized the processing of E1/T1 link physical layer signal, and provides access interface to data link layer; And crossed pair misconnection checkout gear, the function of realization data link layer is as realizing High-Level Data Link Control (High-Level Data Link Control, HDLC) function of agreement.
As an example, crossed pair misconnection checkout gear, can adopt FPGA (Field Programmable Gate Array) to realize, that FPGA (Field Programmable Gate Array) is corresponding with the E1/T1 link is high-speed channel HW (High Way, HW), HW is a kind of bus, and transmitting-receiving respectively has a cover usually, 3 holding wires are arranged respectively, and for example: holding wire is used for 8K frame synchronization, a holding wire is used to provide 2M clock, a holding wire to be used to transmit data.
In the present embodiment, HW is corresponding to the ascending time slot of E1/T1, and another HW is corresponding to the descending time slot of E1/T1.
For example, E1 has 32 time slots, and then a HW correspondence has 32 ascending time slots, another HW correspondence 32 descending time slots are arranged.
The device that present embodiment provides comprises:
Send cache module 301, after being used to write test data, the Y time slot of the link X1 by the E1/T1 chip sends test data to the opposite end.
Wherein, test data is corresponding to the numbering of E1/T1 link.
Receive cache module 302, receive the data of the Y time slot of opposite end loopback by the link X1 receiving terminal of E1/T1 chip, if the data of the Y time slot that obtains are corresponding to the numbering of other E1/T1 link, then there are the crossed pair misconnection in this tested E1/T1 link and other E1/T1 link.
For example, in time slot 2, write test data, then receive cache module 302 and from the time slot 2 of loopback, obtain data if send cache module 301.If these data, illustrate this tested E1/T1 link corresponding to the numbering of other E1/T1 link and the crossed pair misconnection occurs; Perhaps, if the data that receive are default value 0xff (when the time slot word length is 8) or 0xffff (when the time slot word length is 16), illustrate that then opening circuit appears in this link.
Further, receive cache module 302, also be used for, if the test data that the data of obtaining from the Y time slot equal to write, it is normal to illustrate that then the E1/T1 link connects.
The device that present embodiment provides, the Y time slot that is used for writing test data can be arbitrary time slot of E1 link 1-31 time slot, perhaps, the time slot that is used for writing test data is arbitrary time slot of T1 link 1-24 time slot.
As an example, test data is signless integer type data, and the byte length of test data can be 8 bits, perhaps 16 bits.
The device that present embodiment provides, the time slot that writes test data is the E1/T1 time slot of transmission data, and available bit number is more, and the test data that can support is also with more, thereby can support a fairly large number of E1/T1 link is tested.
Further, the device that present embodiment provides, send test data by E1/T1 chip time slot corresponding again after in sending buffer memory, inserting data, adopt the reception buffer memory to receive data from time slot corresponding, avoid the E1/T1 chip directly to insert data, receive the data-bias that data produced by the E1/T1 chip.
Further, the device that present embodiment provides after finding that there is the crossed pair misconnection in the E1/T1 link, can also be determined the numbering of the E1/T1 link of generation misconnection according to test signal, thus the connected mode that corrects mistakes.
Further, the device that present embodiment provides can also be supported simultaneously multichannel E1/T1 link to be carried out offline inspection.
The device that present embodiment provides can adopt FPGA (Field Programmable Gate Array) to realize, as on-site programmable gate array FPGA (Field Programmable Gate Array, FPGA).
See also Fig. 4, Fig. 4 has provided the embodiment of another crossed pair misconnection checkout gear, and in the present embodiment, crossed pair misconnection checkout gear adopts FPGA to realize that this FPGA can be arranged in base station controller, also can be arranged in the base station.
FPGA is connected with the E1/T1 chip, and FPGA can be used to realize the function of HDLC agreement, and FPGA comprises transmission buffer memory 22, receives buffer memory 23, and corresponding with the descending time slot of E1/T1 by descending HW respectively, up HW is corresponding with the ascending time slot of E1/T1.Wherein, the transmission buffer memory 22 of FPGA, in the Y time slot, insert data after, TX end by the E1/T1 chip sends to the base station, after the RX termination of the E1/T1 chip of base station is received data, if the E1/T1 link is normal, then the data that receive are sent to base station controller by the TX end.Receive buffer memory 23, receive the data of Y time slot, with the data that receive and test data relatively,, illustrate that then the E1/T1 link is working properly then if consistent by the E1/T1 chip; If the data of the Y time slot that reception buffer memory 23 receives are the numbering corresponding to other E1/T1 link, illustrate that then there are the crossed pair misconnection in E1/T1 link and other E1/T1 link.
Above-mentioned apparatus and method can be applied in the base station sub-system.As an example, see also Fig. 5, comprising:
In base station controller 401 and the base station 402, in the base station controller 401, comprise FPGA (Field Programmable Gate Array), the E1/T1 chip; In the base station 402, also comprise FPGA (Field Programmable Gate Array) and E1/T1 chip.Wherein, FPGA (Field Programmable Gate Array) can be used for realizing above-mentioned crossed pair misconnection checkout gear.
In test, can go into test data at base station controller 401 sidelights on, also can be at base station controller 402 side tests, below being that example describes at side of base station controller 401.
In off-line test crossed pair misconnection, earlier to the E1/T1 link number between base station controller 401 and the base station 402, and the test data of definite each E1/T1 link.In order to simplify test, can be with the numbering of each E1/T1 link as test data.Can have many E1/T1 links between base station controller 401 and the base station 402, for ease of explanation, only be 2 E1/T1 links in the example that Fig. 4 provides.
Each time slot of every HW of FPGA (Field Programmable Gate Array) is to there being a sending and receiving buffer memory.As an example, can there be one-to-one relationship between buffer memory and the time slot.
In the present embodiment, adopt loopback method test crossed pair misconnection, therefore, need pass through configuration order earlier, all links are provided with remote loopback, make the base station after receiving the E1/T1 data of base station controller, the transmitting terminal of the E1/T1 chip by base station side sends the data that receive to base station controller.
When test data, insert the numbering of E1/T1 link by the E1/T1 chip at the E1/T1 time slot that is used for transmitting data by FPGA (Field Programmable Gate Array) 4011, for ease of expression, be the example explanation with time slot 2 here.
In E1/T1 link 1, the test data that FPGA (Field Programmable Gate Array) 4012 is inserted in the buffer memory of time slot 2 is 1; In E1/T1 link 2, FPGA (Field Programmable Gate Array) 4014 is 2 in the test data of the buffer memory insertion of time slot 2.Insert after the data, FPGA (Field Programmable Gate Array) 4012,4014 sends to test data base station 402 respectively by the link 1 and the link 2 of E1/T1 chip 4011.
Test data can be the signless integer type, and word length can be 8 or 16.
After base station controller 401 side joints were received data, the FPGA (Field Programmable Gate Array) on each E1/T1 link by the E1/T1 chip, was obtained data from the time slot 2 of separately link.
If FPGA (Field Programmable Gate Array) 4012 is 1 from the data that the time slot 2 of link 1 obtains, FPGA (Field Programmable Gate Array) 4014 is 2 from the data that the time slot 2 of link 2 obtains, and illustrates that then E1/T1 link 1, E1/T1 link 2 connect normal; If the data that FPGA (Field Programmable Gate Array) 4012 is obtained are 2, the data that FPGA (Field Programmable Gate Array) 4014 is obtained are 1, illustrate that then there are the crossed pair misconnection in E1/T1 link 1, E1/T1 link 2; If the data that FPGA (Field Programmable Gate Array) is obtained are 0xff (perhaps when word length is 16, being 0xfffff), illustrate that then opening circuit appears in link when the word length of time slot is 8.
The base station sub-system that present embodiment provides, the time slot that writes test data is the E1/T1 time slot of transmission data, and available bit number is more, and the test data that can support is also with more, thereby can support a fairly large number of E1/T1 link is tested.Further, the base station sub-system that present embodiment provides, the device that adopts the foregoing description to provide sends test data, receives data by the E1/T1 chip from time slot corresponding by E1/T1 chip time slot corresponding again write test data in time slot after, the data-bias of avoiding the E1/T1 chip directly to insert data, produce when receiving data.
Further, the base station sub-system that present embodiment provides after finding that the crossed pair misconnection appears in the E1/T1 link, can also be determined the numbering of the E1/T1 link of generation misconnection according to test signal, thus the connected mode that corrects mistakes.
By the description of above embodiment, the those skilled in the art can be well understood to the present invention and can realize by the mode that software adds essential general hardware platform, can certainly pass through hardware.Based on such understanding, the part that technical scheme of the present invention contributes to prior art in essence in other words can embody with the form of software product, this computer software product is stored in the storage medium, comprise that some instructions are with so that a computer equipment (can be a personal computer, server, the perhaps network equipment etc.) carry out all or part of step of the described method of each embodiment of the present invention.And aforesaid storage medium comprises: various media that can be program code stored such as USB flash disk, portable hard drive, read-only memory (ROM), random-access memory (ram), magnetic disc or CD.
Though by with reference to some preferred embodiment of the present invention, the present invention is illustrated and describes, those of ordinary skill in the art should be understood that and can do various changes to it in the form and details, and without departing from the spirit and scope of the present invention.
Claims (11)
1. a crossed pair misconnection detection method is characterized in that, comprises following steps:
The transmission buffer memory that is used for transmitting the Y time slot of data at E1/T1 link X1 writes test data, and described E1/T1 link X1 is an E1/T1 link that is numbered X1, and described test data is corresponding to described X1;
Described transmission buffer memory sends described test data by the Y time slot of the link X1 of E1/T1 chip to the opposite end;
The reception buffer memory of described E1/T1 link X1, receive the data of the Y time slot of described opposite end loopback by the link X1 of described E1/T1 chip, if the data of the Y time slot of described opposite end loopback are corresponding to the numbering of E1/T1 link X2, there are the crossed pair misconnection in then described E1/T 1 link X1 and described E1/T1 link X2.
2. the method for claim 1 is characterized in that, described method also comprises:
If the data of the Y time slot of described opposite end loopback equal described test data, described E1/T1 link X1 connects normal.
3. as the described arbitrary method of claim 1-2, it is characterized in that described Y time slot is arbitrary time slot of 1-31 time slot in the E1 link, or described Y time slot arbitrary time slot that is 1-24 time slot in the T1 link.
4. as the described arbitrary method of claim 1-2, it is characterized in that described test data is signless integer type data.
5. method as claimed in claim 4 is characterized in that, the length of described test data is 8 bits or 16 bits.
6. crossed pair misconnection checkout gear, described device links to each other with the E1/T1 chip, it is characterized in that, and described device comprises:
Send cache module, be used to write test data, the Y time slot of the link X1 by the E1/T1 chip sends test data to the opposite end, and described test data is corresponding to described X1;
Receive cache module, be used for receiving the data of the Y time slot of described opposite end loopback by the link X1 of described E1/T1 chip, if the data of the Y time slot of described opposite end loopback are corresponding to the numbering of E1/T1 link X2, there are the crossed pair misconnection in described E1/T1 link X1 and described E1/T1 link X2.
7. device as claimed in claim 6 is characterized in that, described reception cache module also is used for, if the data of the Y time slot of described opposite end loopback equal described test data, described E1/T1 link X1 connects normal.
8. as the described arbitrary device of claim 6-7, it is characterized in that described Y time slot is arbitrary time slot of 1-31 time slot in the E1 link, or described Y time slot arbitrary time slot that is 1-24 time slot in the T1 link.
9. as the described arbitrary device of claim 6-7, it is characterized in that described test data is signless integer type data.
10. device as claimed in claim 9 is characterized in that, the length of described test data is 8 bits or 16 bits.
11. a base station sub-system is characterized in that, comprises described arbitrary device as claim 6-10.
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| CN 201010118860 CN101835186A (en) | 2010-03-01 | 2010-03-01 | Detection method and detection device of misconnection of Yuanyang lines and base station subsystem |
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| CN 201010118860 CN101835186A (en) | 2010-03-01 | 2010-03-01 | Detection method and detection device of misconnection of Yuanyang lines and base station subsystem |
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| CN102801462A (en) * | 2011-05-23 | 2012-11-28 | 中兴通讯股份有限公司 | Method and device for detecting optical fiber connection |
| CN105450432A (en) * | 2014-07-31 | 2016-03-30 | 华为技术有限公司 | Method for positioning port connection error and associated equipment |
| CN102801462B (en) * | 2011-05-23 | 2016-11-30 | 南京中兴新软件有限责任公司 | The detection method of optical fiber connection and device |
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| CN105450432A (en) * | 2014-07-31 | 2016-03-30 | 华为技术有限公司 | Method for positioning port connection error and associated equipment |
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Application publication date: 20100915 |