CN101834780B - Method for optimizing topological structure and mapping of network on chip - Google Patents

Abstract

The invention discloses a method for optimizing a topological structure and mapping of a network on chip (NoC), which comprises the following steps of: determining a single sequence (SS) for optimizing the topological structure through two drawing methods; and acquiring a name sequence for optimizing the mapping through a mapping relation between the single sequence (SS) and a module collection. So, the method can optimize a network structure and the mapping and reduce the power consumption. Besides, the method adopts a GXY routing algorithm to determine the routing of the entire network on chip (NoC), and performs optimization according to a simulated annealing algorithm to obtain a layout result that the power consumption is low and the area is small.

Description

The mapping optimization method of the topological structure of network-on-chip

Technical field

The present invention relates to the general 2D topological structure based on floor planning technology, particularly the mapping optimization method of the topological structure of network-on-chip (NoC, Network-on-Chip).

Background technology

Along with the exhibition of not stopping paying out of the manufacturing technology of integrated circuit, the transistor size that can hold on single silicon chip is more and more, has reached billions of gate leves, and this means can integrated increasing IP kernel in one single chip.Traditional bus structures cannot adapt to the communicating requirement of dozens of and even up to a hundred IP kernels.Now network-on-chip is as the multiprocessing system of the communication Network Based realizing on one chip, solve well the problem (referring to document 1-4) that bus structures are brought, it is applied to chip design by computer networking technology, has obtained being better than bus-structured result.

Yet, in existing NoC design (referring to document 5-8), mapping problems and topological structure are failed to realize always and are optimized, the final position of deteriorated mapping impact on corresponding topological structure, simultaneously, the topological structure of rule causes the waste that chip area is very large, and on this basis, existing NoC design power consumption is larger.

Therefore, be necessary to provide a kind of topological structure and mapping optimization method of improved network-on-chip

The above-mentioned pertinent literature of mentioning:

[1]Kumar?S,Jantsch?A,Soininen?J?P,et?al.A?network?on?chip?architecture?and?design?methodology[C],Proceedings?of?the?IEEE?Computer?Society?Annual?Symposium?on?VLSI,Pittsburgh,2002.105-112

[2]Dally?W?J,Towles?B.Route?packets,not?wires:on-chip?interconnection?networks[C],Proceedings?of?Design?Automation?Conference,Las?Vegas,Nevada,2001,684-689

[3] Zhang Lei, Li Huawei, Li Xiaowei.For the fault-tolerant communications algorithm [J] of network-on-chip, computer-aided design and graphics journal, 2007,19 (4) .508-514

[4] Zhou Ganmin, brilliant human relations.NoC basic research [D]. Hefei: HeFei University of Technology

[5]Chae-Eun?Rhee,Han-You?Jeong,Soonhoi?Ha.Many-to-many?core-switch?mapping?in2-D?mesh?NoC?architecturs[C],ICCD2004,San?Jose,CA,2004.438-443.

[6]Srinivasan?Murali,Giovanni?De?Micheli.Bandwidth-constrained?mapping?of?cores?onto?NoC?architectures[C],Proceedings?of?Design,Automation?and?Test?in?Europe?Conference?and?Exhibition(DATE04).France:Paris,2004,896-901.

[7]Jingcao?Hu，Radu?Marculescu.Energy-and?performance-aware?mapping?for?regular?NoC?architectures[J],IEEE?Transactions?on?CAD?of?IC?and?Systems,2005,24(4),551-562.

[8] Gu Haiyun, Li Zhangwen, Sun Shu. irregular 2D Mesh NoC mapping algorithm research [J]. microelectronics and computer .2008,25 (7) .56-60

Summary of the invention

The mapping optimization method that the object of this invention is to provide a kind of topological structure of network-on-chip, energy optimized network structure and mapping, reduce power consumption.

To achieve these goals, the invention provides a kind of mapping optimization method of topological structure of network-on-chip, comprise the steps: each module in layout, summit from the upper right corner of each module, preferential upwards drafting, then draw to the right, be plotted to the upper right corner of Butut always; From the summit in the lower left corner of each module, preferentially draw downwards, then draw left, be plotted to the lower left corner of Butut always; The all modules numberings in layout, to the straight line in the upper right corner and the crossing order of the first broken line, are given in the lower left corner based on layout; To the numbering module in layout, from the summit in the upper left corner of each module, preferentially upwards draw, then draw left, be plotted to the upper left corner of Butut always; From the summit in the lower right corner of each module, preferentially draw downwards, then draw to the right, be plotted to the lower left corner of Butut always; The upper left corner based on layout, to the straight line in the lower right corner and the crossing order of the second broken line, obtains the simple sequence of optimizing topological structure; According to the mapping relations of simple sequence and module collection, obtain the title sequence of optimizing mapping.

In one embodiment of the invention, described method also comprises step: simple sequence is decoded into horizontal relationship figure and vertical relation figure, and horizontal relationship figure and vertical relation figure are subdivided into up and down to totally four syntople figure.

In another embodiment of the present invention, described method also comprises step: according to title sequence and the horizontal relationship figure being determined by simple sequence and vertical relation figure to sequence to decoding, determine the position of modules.

In an embodiment more of the present invention, described method also comprises step: by comparing the size of integer element and the relation up and down of the left and right location positioning integer element corresponding module of integer element in simple sequence in simple sequence.

In another embodiment of the present invention, described method also comprises step: the route of determining whole network-on-chip NoC according to GXY routing algorithm.

Wherein, the principle of described GXY routing algorithm is first along horizontal direction route, then along vertical direction route, until pass the signal to object module.

In an embodiment more of the present invention, described method also comprises step: according to four syntople figure judge modules are adjacent up and down.

In another embodiment of the present invention, described method also comprises step: according to the distance between the adjacent judged result determination module of module, the route acquisition power consumption of the network-on-chip based on definite.

As shown from the above technical solution, the mapping optimization method of the topological structure of network-on-chip of the present invention is determined the simple sequence of optimizing topological structure by two kinds of method for drafting, and then by the mapping relations of simple sequence and module collection, obtain the title sequence of optimizing mapping, therefore, this method can optimized network structure and mapping, reduces power consumption.In addition, the present invention has adopted GXY routing algorithm to determine the route of whole network-on-chip NoC, and is optimized according to simulated annealing, has obtained layout result low in energy consumption and that area is little.

By following description also by reference to the accompanying drawings, it is more clear that the present invention will become, and these accompanying drawings are used for explaining embodiments of the invention.

Accompanying drawing explanation

Fig. 1 is the flow chart of mapping optimization method of the topological structure of network-on-chip of the present invention.

Fig. 1 a has shown the first topological structure method for drafting in the mapping optimization method of topological structure of network-on-chip shown in Fig. 1.

Fig. 1 b for drawing the schematic diagram of a straight line from the upper left corner to the lower right corner in Fig. 1 a.

Fig. 1 c has shown method module being numbered according to method for drafting shown in Fig. 1 b.

Fig. 1 d has shown the second topological structure method for drafting in the mapping optimization method of topological structure of network-on-chip shown in Fig. 1.

Fig. 1 e for drawing the schematic diagram of a straight line from the lower left corner to the upper right corner in Fig. 1 d.

Fig. 2 a has shown the horizontal relationship figure of the simple sequence decoding that method for drafting shown in Fig. 1 d is definite.

Fig. 2 b has shown the vertical relation figure of the simple sequence decoding that method for drafting shown in Fig. 1 d is definite.

Fig. 2 c has shown topology diagram corresponding to simple sequence that method for drafting shown in Fig. 1 d is definite.

Fig. 3 has shown simple sequence that method for drafting shown in Fig. 1 d is definite and the mapping relations of module collection.

Fig. 4 has shown the up and down relation of sequence to two modules in decoded layout in the mapping optimization method of topological structure of network-on-chip shown in Fig. 1.

Fig. 5 has shown the neighbouring relations between module in the mapping optimization method of topological structure of network-on-chip shown in Fig. 1.

Fig. 6 is the schematic diagram that in the mapping optimization method of topological structure of network-on-chip shown in Fig. 1, GXY routing algorithm is realized route.

Fig. 7 is the task image of MPEG4.

Fig. 8 has shown the result of optimizing distribution that adopts index cooling strategy to anneal and obtain based on task image shown in Fig. 7.

Embodiment

With reference now to accompanying drawing, describe embodiments of the invention, in accompanying drawing, similarly element numbers represents similar element.

See Fig. 1, the mapping optimization method of the topological structure of the present embodiment network-on-chip, comprises the steps:

Step S10, to each module in layout, from the summit in the upper right corner of each module, preferentially upwards draws, then draws to the right, is plotted to the upper right corner of Butut always; From the summit in the lower left corner of each module, preferentially draw downwards, then draw left, be plotted to the lower left corner of Butut always;

Step S11, all modules numberings in layout, to the straight line in the upper right corner and the crossing order of the first broken line, are given in the lower left corner based on layout;

Step S12, to the numbering module in layout, from the summit in the upper left corner of each module, preferentially upwards draws, then draws left, is plotted to the upper left corner of Butut always; From the summit in the lower right corner of each module, preferentially draw downwards, then draw to the right, be plotted to the lower left corner of Butut always;

Step S13, the upper left corner based on layout, to the straight line in the lower right corner and the crossing order of the second broken line, obtains the simple sequence (Single-Sequence, SS) of optimizing topological structure;

Step S14, is decoded into horizontal relationship figure and vertical relation figure by simple sequence, and horizontal relationship figure and vertical relation figure are subdivided into up and down to totally four syntople figure;

Step S15, according to the mapping relations of simple sequence and module collection, obtains the title sequence (Name-Sequence, NS) of optimizing mapping;

Step S16, according to title sequence and the horizontal relationship figure being determined by simple sequence and vertical relation figure to sequence to decoding, determine the position of modules;

Step S17, by comparing the size of integer element and the relation up and down of the left and right location positioning integer element corresponding module of integer element in simple sequence in simple sequence;

Step S18, determines the route of whole network-on-chip NoC according to GXY routing algorithm;

Step S19, according to four syntople figure judge modules are adjacent up and down;

Step S20, according to the distance between the adjacent judged result determination module of module, the route acquisition power consumption of the network-on-chip based on definite.

As seen from the above, this method adopts two sequence representations-determine the simple sequence SS of topological structure and determines the title sequence NS of mapping, can be optimized topological structure, mapping, realizes the alap target of power consumption in the manufacture process of special-purpose multinuclear equipment.Because this method adopts simple sequence SS and module title sequence NS, represent layout, therefore can be described as SSNS layout representation.

Below the mapping optimization method of the topological structure of embodiment network-on-chip is elaborated.

Determine the simple sequence of optimizing topological structure

The first topological structure method for drafting

Step1: to each module in layout, from the summit in the upper right corner of each module, preferentially upwards draw, then draw to the right, be plotted to the upper right corner of Butut always.

Step2: in like manner, from the summit in the lower left corner of each module, preferentially draw downwards, then draw left, be plotted to the lower left corner of Butut always, obtain topological structure as shown in Figure 1a.

The second is flutterred structure method for drafting

Step1: to each module in layout, from the summit in the upper left corner of each module, preferentially upwards draw, then draw left, be plotted to the upper left corner of Butut always.

Step2: in like manner, from the summit in the lower right corner of each module, preferentially draw downwards, then draw to the right, be plotted to the lower left corner of Butut always.

In Fig. 1 a, draw a straight line from the upper left corner to the lower right corner, as Fig. 1 b, according to straight line and the crossing order of broken line, by numeral, to module, be numbered, obtain Fig. 1 c.As Fig. 1 c, module is numbered with digital 1-6.Use the second topological structure method for drafting, the module of numbering is carried out to topological structure drafting, obtain topological structure as shown in Figure 1 d.In Fig. 1 d, draw a straight line from the lower left corner to the upper right corner, as Fig. 1 e, according to straight line and the crossing order of broken line, obtain one group of sequence: (4,2,6,1,3,5)-determine simple sequence SS of topological structure.

As seen from the above, to the topological structure location problem that contains n module, the length of simple sequence SS is only n, this method be sequence to representation (with reference to H.Murata, K.Fujiyoshi, S.Nakatake, et al.. " Rectangle-Packing-based Module Placement, " IEEE/ACM International Conference on Computer-Aided Design (ICCAD), San Jose, California, USA, November1995, a kind of improvement 472-479), only use an integer sequence just (ABLR) up and down relation of module can be showed, determine topological structure, realize the optimization of topological structure.In NoC problem, through the topological structure of optimizing, to be far superior to general topological structure (as Mesh topological structure).

Relation up and down between determination module

In simple sequence SS, by comparing the size of integer element and the relation up and down of the left and right location positioning integer element corresponding module of integer element in simple sequence SS in simple sequence SS.Specifically be defined as follows:

(1) in simple sequence SS, integer element a is when the right while of integer element b a<b, and the module that integer element a is corresponding is positioned at the top of the module that integer element b is corresponding.

(2) in simple sequence SS integer element a on the left side of integer element b a>b simultaneously, the module that integer element a is corresponding be positioned at module that integer element b is corresponding below.

(3) in simple sequence SS, integer element a is at the left side while of integer element b a<b, and the module that integer element a is corresponding is positioned at the left side of the module that integer element b is corresponding.

(4) in simple sequence SS, integer element a is at the right while of integer element b a>b, and the module that integer element a is corresponding is positioned at the right of the module that integer element b is corresponding.

Fig. 4 has shown the up and down relation of sequence to two modules in (SP) decoded layout.As figure, the left margin of module j not yet leaves the region of top, therefore the position of module j belongs to the top of module i.

The decoding of simple sequence

Simple sequence SS is decoded into unique horizontal relationship figure and vertical relation figure, and (concrete coding/decoding method is with reference to Kang Li, Juebang Yu, YongbingYu, Configuration of Floorplan and Placement Algorithm Using Horizontal and Vertical Contour Based on Single Sequence[C], In Proceedings of Communications, Circuits and Systems, 2008, 1171-1174), this two figure correspondence the general 2D topological structure of NoC, it is comparatively simple that visible this method is decoded into layout to this integer sequence of simple sequence SS.Horizontal relationship figure and the vertical relation figure of above-mentioned simple sequence SS (4,2,6,1,3,5) decoding be shown in shown in Fig. 2 a, 2b, and Fig. 2 c is shown in by corresponding 2D topological structure.

The present invention adopts in abutting connection with this data structure of chained list and carrys out storage map, different according to the sensing of pointer, and above-mentioned horizontal relationship figure and vertical relation figure are stored as respectively to left and right in abutting connection with chained list with up and down in abutting connection with chained list.To right and upper in abutting connection with chained list, new limit is inserted into the tail end of chained list.Directly traversal is right and upper in abutting connection with chained list, obtains a left side and lower to chained list, and for left and lower to chained list, new limit is inserted into after a node of chained list.

Determine the title sequence of optimizing mapping

According to the mapping relations of simple sequence and module collection, determine title sequence.Above-mentioned simple sequence SS=(4,2,6,1,3,5) for example, module collection M={SRAM, FIFO, ME, Input, VLC, CompBlock}, the element in simple sequence SS forms with element in module collection M anyly shines upon corresponding a kind of layout one by one.

Mapping relations as shown in Figure 3 can obtain the sequence of modules corresponding with simple sequence SS: (SRAM, FIFO, ME, Input, VLC, CompBlock), this sequence is called title sequence NS.

The module title sequence NS that the simple sequence SS that the sequence that is 2n by length is n to (SP) by a length and length are n represents.According to title sequence NS and the horizontal relationship figure being determined by simple sequence SS and vertical relation figure, sequence is decoded to (SP), the apex coordinate in the lower left corner of each IP module (is usingd as its position in the position of determining each IP module, particular location determines that method is with reference to Kang Li, Juebang Yu, YongbingYu, Configuration of Floorplan and Placement Algorithm Using Horizontal and Vertical Contour Based on Single Sequence[C], In Proceedings of Communications, Circuits and Systems, 2008, 1171-1174).The position of each IP module that this method obtains is all tightly adjacent.

The mapping method of above-mentioned NoC has following benefit: 1) position due to each IP module is all tightly adjacent, so the also shortening thereupon of the distance of route, and power consumption also can reduce; 2) the tightly adjacent area that also can reduce whole Butut in the position of each IP module; 3) from above-mentioned algorithm, can find out, need not consider the problem that module is overlapping.

Whether judge module is adjacent

Suppose module M _ithe numeral being mapped in simple sequence SS is S _i, module M _jthe numeral being mapped in simple sequence SS is S _j.Two modules are adjacent is:

1) in right syntople figure, S _ifirst abutment points in abutting connection with chained list be S _j, M _iat M _jthe left side and be adjacent.

2) in left syntople figure, S _ifirst abutment points in abutting connection with chained list be S _j, M _iat M _jthe right and be adjacent.

3) in lower syntople figure, S _ifirst abutment points in abutting connection with chained list be S _j, M _iat M _jtop and be adjacent.

4) in upper syntople figure, S _ifirst abutment points in abutting connection with chained list be S _j, M _iat M _jbelow and be adjacent.

Based on above-mentioned definition, module adjacent with module M in Fig. 5 has:

1) left adjacent: a module M left side 1, a module M left side 2;

2) right adjacent: the module M right side 1, the module M right side 2;

3) upper adjacent: module M is upper 1, and module M upper 2;

4) lower adjacent: under module M 1, under module M 2, under module M 3.

Without the static GXY routing algorithm of deadlock

Based on the definite topological structure of simple sequence SS, according to GXY routing algorithm, determine the route of whole network-on-chip NoC.Wherein the principle of GXY routing algorithm is first along horizontal direction route, then along vertical direction route, until pass the signal to object module.

Describe GXY routing algorithm below in detail and how to realize route.As shown in Figure 6, suppose that it is module M that route plays point module _s, terminal module is module M _g, concrete route step is:

Step1: determination module M _swith module M _grelative position relation: module M _sat module M _gupper right side;

Step2: make module M _sroute one step (choosing one of them left adjacent block) left, and new module is designated as to module M _s; Make module M _groute one step (choosing adjacent block on one of them) upwards, and new module is designated as to M _g;

Step3: constantly repeat step2, until run into joining module M _cross;

Step4: by module M in step2 _swith module M _gthe Path Connection of route gets up, and the path of connection is module M _sto module M _grouting plan.

At module M _sduring route, according to actual conditions, choose left adjacent block left, when switch is all placed on the lower left corner, choose last left adjacent block at every turn; At module M _gduring the route that makes progress, according to actual conditions, choose upper adjacent block, when switch is all placed on the lower left corner, choose adjacent block on first at every turn.In addition, do not have right adjacent block, using first abutment points as right adjacent block, not having upper and lower, left adjacent block is similar processing.

As seen from the above, this method has adopted the XY dimension order routing algorithm GXY routing algorithm (generalized XY routing algorithm) of promoting to determine the route of whole network-on-chip NoC, than traditional XY dimension order routing algorithm, not only overcome the defect that can only be applied on regular Mesh topological structure, can be applied on irregular 2D topological structure, and can reduce largely power consumption.

NoC power consumption calculation

Because the circuit scale of NoC is huge, and processing based under nanometer technology, on single-chip, realize under the integrated condition of large-scale circuit more, how to reduce communication power consumption and become the problem that designer is more and more concerned about, so power consumption also becomes the most important constraint of NoC.

Definition 1IP core communication task figure G (V, C) is a directed graph, and each vertex v ∈ V, represents an IP module, every directed edge c _ij∈ C, represents the communication task from i IP kernel to j IP kernel, weight w _ijrepresent communication task c _ijdata traffic, unit is flit, traffic is directly proportional to flit number.

Definition 2NoC topology diagram P (R, L) is an oriented complete graph, and each summit r ∈ R represents a resource node, every directed edge l _ij∈ L, represents the path from node i to node j, its weights t _ijthe power consumption size of expression from flit of node i transmission to node j.

Given IP kernel communication task figure G and NoC topology diagram P, find processing unit T to the mapping function Φ of resource node R, and the target function of NoC power consumption is:

$\mathrm{MinE}=\underset{i=1}{\overset{n}{\mathrm{\&Sigma;}}}\underset{j=1}{\overset{n}{\mathrm{\&Sigma;}}}{w}_{\mathrm{ij}}{e}_{\mathrm{map}\left(r_i\right)\mathrm{map}\left(r_j\right)}---\left(1\right)$

Constraints is:

$\&ForAll;v_j\&Element;G,\mathrm{\&Phi;}\left(v_i\right)\&Element;R---\left(2\right)$

$\&ForAll;v_i\&NotEqual;v_j\&Element;G,\mathrm{\&Phi;}\left(v_i\right)\&NotEqual;\mathrm{\&Phi;}\left(v_j\right)\&Element;R---\left(3\right)$

Wherein, constraints (2) and (3) show that each processing unit can only be assigned on a resource node, and each resource node can only distribute a processing unit.

Wherein, wherein, the total power consumption that E is NoC, w _ijrepresent that i IP kernel is to the data traffic of the communication task of j IP kernel,

expression is from resource node r _itransmit a data flow control to resource node r _jpower consumption.

calculating adopted the people such as H-S.Wang (with reference to Hangsheng Wang, Xinping Zhu, Li-Shiuan Peh, et al..Orion:A Power-Performance Simulator for Interconnection Networks, In Proceedings of MICRO35, Istanbul, Turkey, November2002,294-305) the communication power consumption model of the architecture level set up.Particularly,

for:

$e_{\mathrm{map}\left(r_i\right)\mathrm{map}\left(r_j\right)}=N_{\mathrm{node}}{e}_{\mathrm{node}}+D_{\mathrm{link}}{e}_{\mathrm{link}}---\left(4\right)$

Wherein, e _noderepresent the energy that 1 flit data of each switch processes consume, e _linkrepresent the energy that each flit data consumes through a passage, N _nodethe number of switches that represents process in routing procedure, D _linkexpression is from node r _ito node r _jroute distance.

If i IP module is adjacent with j IP module, the distance between two modules adopts manhatton distance; If i IP module and j IP module are non-conterminous, by routed path, again i IP module, a j IP module and the module between two modules are numbered: i, i+1 ..., j-1, j, now the distance between two modules is:

$\underset{k=i}{\overset{j-1}{\mathrm{\&Sigma;}}}{d}_k$

Wherein, d _krepresent the manhatton distance between k IP module and k+1 IP module, the power consumption size that can obtain between i IP module and j IP module is thus:

$e_{\mathrm{map}\left(r_i\right)\mathrm{map}\left(r_j\right)}=N_{\mathrm{node}}{e}_{\mathrm{node}}+\underset{k=i}{\overset{j-1}{\mathrm{\&Sigma;}}}{d}_k{e}_{\mathrm{link}}$

By formula (1), just can calculate total power consumption again.

Analysis of complexity of the present invention

The complexity of solution space

Adopt BSG grid (whole chip is divided into n * n grid), its solution space is

2, the complexity of solution space much larger than O ((n! ) ²).

Use SSNS layout representation of the present invention, if there be n module, the complexity of solution space be O (( ) ²).

Therefore, the solution space complexity of SSNS layout representation of the present invention is lower than adopting the solution space complexity of BSG.

Calculate the complexity of power consumption

Adopt BSG grid, dijkstra's algorithm when calculating power consumption, its complexity be node number square, the Layout matrix that is n * n due to size has (n+1) ²individual node, will calculate so

to the distance between module, the complexity of calculating power consumption is

be O (n ⁶).

By SSNS layout representation of the present invention, only need calculate the manhatton distance between module between two with the decoded module coordinate of layout, the complexity of calculating the beeline of a pair of module is Constant Grade.The complexity of decoding due to layout is O (n ²), the complexity of calculating power consumption is be O (n ²).

Therefore, the calculating power consumption complexity of SSNS layout representation of the present invention is lower than adopting the calculating power consumption complexity of BSG.

Consider the calculating power consumption complexity of routing algorithm

If calculate in the process of power consumption and consider route, according to graph of a relation up and down, can obtain modules A to the routed path of module B, complexity is only O (n).Due to total in layout

2 pairs of modules, introduce after routing algorithm, and the complexity of calculating power consumption is O (n ³).

Therefore,, even if consider routing algorithm, the calculating power consumption complexity of SSNS layout representation of the present invention is still low than adopting the calculating power consumption complexity of BSG.

Complexity by the mapping of NoC and the solution space of routing issue can find out, this problem is a NP difficult problem (NP-Complete, a nonpolynomial algorithm difficult problem), and the general heuritic approach that adopts solves at present.

The present invention adopts simulated annealing method that the mapping of network-on-chip and routing issue are optimized and are solved.If the initial value of NS and SS is 1,2,3 ..., n.Can produce new solution with following several operations:

Operation 1: some to numeral in NS of exchange;

Operation 2: i numeral in NS is inserted into j position;

Operation 3: some to numeral in SS of exchange;

Operation 4: i numeral in SS is inserted into j position;

Operation 5: set a probable value (as 0.0001), and exchange width and the height of i module with this probability.

Adopt index cooling strategy to anneal, with the task image of the MPEG4 shown in Fig. 7, test, what obtain optimizes distribution result as shown in Figure 8.This method has carried out route to be optimized according to simulated annealing, has obtained layout result low in energy consumption and that area is little.

Invention has been described for above combination most preferred embodiment, but the present invention is not limited to the embodiment of above announcement, and should contain the various modifications of carrying out according to essence of the present invention, equivalent combinations.

Claims (6)

1. a mapping optimization method for the topological structure of network-on-chip, comprises the steps:

Step S10, to each module in layout, from the summit in the upper right corner of each module, preferentially upwards draws, then draws to the right, is plotted to the upper right corner of Butut always; From the summit in the lower left corner of each module, preferentially draw downwards, then draw left, be plotted to the lower left corner of Butut always;

Step S11, all modules numberings in layout, to the straight line in the upper right corner and the crossing order of the first broken line, are given in the lower left corner based on layout;

Step S12, to the numbering module in layout, from the summit in the upper left corner of each module, preferentially upwards draws, then draws left, is plotted to the upper left corner of Butut always; From the summit in the lower right corner of each module, preferentially draw downwards, then draw to the right, be plotted to the lower left corner of Butut always;

Step S13, the upper left corner based on layout, to the straight line in the lower right corner and the crossing order of the second broken line, obtains the simple sequence SS that optimizes topological structure, is specially:

Draw a straight line from the upper left corner to the lower right corner, according to straight line and the crossing order of broken line, with digital 1-16, to module, be numbered, the module of numbering is carried out to topological structure as follows and draw and obtain topological structure:

Step1: to each module in layout, from the summit in the upper left corner of each module, preferentially upwards draw, then draw left, be plotted to the upper left corner of Butut always;

Step2: in like manner, from the summit in the lower right corner of each module, preferentially draw downwards, then draw to the right, be plotted to the lower left corner of Butut always;

Draw a straight line from the lower left corner to the upper right corner, according to straight line and the crossing order of broken line, obtain one group of sequence: (4,2,6,1,3,5), this sequence is exactly the simple sequence SS of topological structure;

Step S14, is decoded into horizontal relationship figure and vertical relation figure by simple sequence, and horizontal relationship figure and vertical relation figure are subdivided into up and down to totally four syntople figure;

Step S15, according to the mapping relations of simple sequence and module collection, obtains the title sequence NS that optimizes mapping;

Step S16, according to title sequence and the horizontal relationship figure being determined by simple sequence and vertical relation figure to sequence to decoding, determine the position of modules;

Step S17, by comparing the size of integer element and the relation up and down of the left and right location positioning integer element corresponding module of integer element in simple sequence in simple sequence;

Step S18, determines the route of whole network-on-chip NoC according to GXY routing algorithm;

Step S19, according to four syntople figure judge modules are adjacent up and down;

Step S20, according to the distance between the adjacent judged result determination module of module, the route acquisition power consumption of the network-on-chip based on definite.

2. the mapping optimization method of the topological structure of network-on-chip as claimed in claim 1, is characterized in that: described step S17 determines that the method for the relation up and down of the corresponding module of integer element is:

In simple sequence SS, by comparing the size of integer element and the relation up and down of the left and right location positioning integer element corresponding module of integer element in simple sequence SS in simple sequence SS, concrete is set as follows:

(1) in simple sequence SS, integer element a is when the right while of integer element b a<b, and the module that integer element a is corresponding is positioned at the top of the module that integer element b is corresponding;

(2) in simple sequence SS integer element a on the left side of integer element b a>b simultaneously, the module that integer element a is corresponding be positioned at module that integer element b is corresponding below;

(3) in simple sequence SS, integer element a is at the left side while of integer element b a<b, and the module that integer element a is corresponding is positioned at the left side of the module that integer element b is corresponding;

(4) in simple sequence SS, integer element a is at the right while of integer element b a>b, and the module that integer element a is corresponding is positioned at the right of the module that integer element b is corresponding.

3. the mapping optimization method of the topological structure of network-on-chip as claimed in claim 1, is characterized in that: the method that described step S15 obtains the title sequence NS that optimizes mapping is:

According to the mapping relations of simple sequence SS and module collection, determine title sequence: the element in simple sequence SS forms with element in module collection M, and any to shine upon one by one corresponding a kind of layout be title sequence NS.

4. the mapping optimization method of the topological structure of network-on-chip as claimed in claim 1, is characterized in that: the determination methods of described step S14 syntople is:

Setting module M _ithe numeral being mapped in simple sequence SS is S _i, module M _jthe numeral being mapped in simple sequence SS is S _j, two modules are adjacent is:

1) in right syntople figure, S _ifirst abutment points in abutting connection with chained list be S _j, M _iat M _jthe left side and be adjacent;

2) in left syntople figure, S _ifirst abutment points in abutting connection with chained list be S _j, M _iat M _jthe right and be adjacent;

3) in lower syntople figure, S _ifirst abutment points in abutting connection with chained list be S _j, M _iat M _jtop and be adjacent;

4) in upper syntople figure, S _ifirst abutment points in abutting connection with chained list be S _j, M _iat M _jbelow and be adjacent.

5. the mapping optimization method of the topological structure of network-on-chip as claimed in claim 1, is characterized in that: described step S18 determines that according to GXY routing algorithm the concrete grammar of the route of whole network-on-chip NoC is:

It is module M that setting route plays point module _s, terminal module is module M _g, concrete route step is:

Step1: determination module M _swith module M _grelative position relation: module M _sat module M _gupper right side;

Step2: make module M _sroute one step left, and new module is designated as to module M _s; Make module M _groute one step upwards, and new module is designated as to M _g;

Step3: constantly repeat step2, until run into joining module M _cross;

Step4: by module M in step2 _swith module M _gthe Path Connection of route gets up, and the path of connection is module M _sto module M _grouting plan.

6. the mapping optimization method of the topological structure of network-on-chip as claimed in claim 1, is characterized in that: the concrete grammar of the route acquisition power consumption of the network-on-chip of described step S20 based on definite is:

Definition 1IP core communication task figure G (V, C) is a directed graph, and each vertex v ∈ V, represents an IP module, every directed edge c _ij∈ C, represents the communication task from i IP kernel to j IP kernel, weight w _ijrepresent communication task c _ijdata traffic, unit is flit, traffic is directly proportional to flit number;

Definition 2NoC topology diagram P (R, L) is an oriented complete graph, and each summit r ∈ R represents a resource node, every directed edge l _ij∈ L, represents the path from node i to node j, its weights t _ijthe power consumption size of expression from flit of node i transmission to node j;

Given IP kernel communication task figure G and NoC topology diagram P, find processing unit T to the mapping function Φ of resource node R, and the target function of NoC power consumption is:

Constraints is:

Wherein, constraints (2) and (3) show that each processing unit can only be assigned on a resource node, and each resource node can only distribute a processing unit;

Wherein, the total power consumption that E is NoC, w _ijrepresent that i IP kernel is to the data traffic of the communication task of j IP kernel,

expression is from resource node r _itransmit a data flow control to resource node r _jpower consumption, particularly:

Wherein, e _noderepresent the energy that 1 flit data of each switch processes consume, e _linkrepresent the energy that each flit data consumes through a passage, N _nodethe number of switches that represents process in routing procedure, D _linkexpression is from node r _ito node r _jroute distance;

If i IP module is adjacent with j IP module, the distance between two modules adopts manhatton distance; If i IP module and j IP module are non-conterminous, by routed path, again i IP module, a j IP module and the module between two modules are numbered: i, i+1 ..., j-1, j, now the distance between two modules is:

Wherein, d _krepresent the manhatton distance between k IP module and k+1 IP module, the power consumption size of obtaining thus between i IP module and j IP module is:

By formula (1), calculate total power consumption again.

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