CN101834153B - Method for enhancing pressure resistance capacity of chip in packaging process and chip thereof - Google Patents
Method for enhancing pressure resistance capacity of chip in packaging process and chip thereof Download PDFInfo
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- CN101834153B CN101834153B CN201010153707.8A CN201010153707A CN101834153B CN 101834153 B CN101834153 B CN 101834153B CN 201010153707 A CN201010153707 A CN 201010153707A CN 101834153 B CN101834153 B CN 101834153B
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Abstract
The invention relates to a method for enhancing the pressure resistance capacity of a chip in the packaging process and the chip thereof. The method comprises the following steps of: additionally arranging patterns used for forming through holes in a redundancy region of each metal interlayer insulation layer mask and a redundancy region of each metal interconnect mask, wherein the pattern additionally arranged in the redundancy region at the nth metal interconnect mask corresponds to the pattern additionally arranged in the redundancy region of the nth metal interlayer insulation layer mask, and the pattern additionally arranged in the redundancy region of the (n+1)th metal interlayer insulation layer mask corresponds to the pattern additionally arranged in the redundancy region of the nth metal interconnect mask, wherein n is 1, 2, 3 till N. The method for enhancing the pressure resistance capacity of the chip in the packaging process and the chip thereof can improve the pressure resistance capacity of the chip, thereby improving the manufacturing reliability of the chip.
Description
Technical field
The present invention relates to semiconductor fabrication, particularly relate to a kind of method and the chip thereof that strengthen pressure resistance capacity of chip in packaging process.
Background technology
Below the manufacturing process of below 65nm semiconductor device is simply introduced:
As shown in Figure 1A, lining base 101 is formed the isolation channel 102 of source region and active area, interval, described active area comprises the grid that is formed on described lining base 101 surface and is formed at described lining base 101 lower face, the source region of described grid both sides and drain region, described isolation channel 102 is positioned at described lining base 101 lower face, and the both sides of described grid are formed with side wall 106;
In figure ia, grid 103a, source region 104a and drain region 105a form p type field effect transistor, and grid 103b, source region 104b and drain region 105b form n type field effect transistor;
As shown in Figure 1B, insulating barrier 107 between deposit the first metal layer on the surface of described lining base 101, isolation channel 102, grid and side wall 106, between this first metal layer of polishing, insulating barrier 107 makes the surface of insulating barrier 107 between described the first metal layer smooth;
As shown in Figure 1 C, by photoetching, etching, between described the first metal layer, etch through hole 108 (vias) in insulating barrier 107, described through hole 108 is for the formation of the metal closures being connected with source region and metal interconnecting wires;
As shown in figure ip, depositing metal fills described through hole 108, and this metal covers the surface of insulating barrier 107 between described the first metal layer, then metal described in polishing, until expose insulating barrier 107 between described the first metal layer, between described the first metal layer, form metal closures 109 in insulating barrier 107;
Described metal is copper;
As referring to figure 1e, between described the first metal layer insulating barrier 107 and metallic copper plug 109 surface on deposit first insulating medium layer 110, this first insulating medium layer 110 of polishing makes the surface of described first insulating medium layer 110 smooth;
As shown in fig. 1f, by photoetching, etching, in described first insulating medium layer 110, etch through hole 111, described through hole 111 is for the formation of metal interconnecting wires, and described metal interconnecting wires is for connecting the element on described lining base 101;
As shown in Figure 1 G, depositing metal copper fills described through hole 111, metallic copper described in polishing, until expose described first insulating medium layer 110, in described first insulating medium layer 110, forms the first metal interconnecting wires 112;
As shown in fig. 1h, deposit second metal interlevel insulating barrier 113, this second metal interlevel insulating barrier 113 of polishing makes the surface of described second metal interlevel insulating barrier 113 smooth;
As shown in Figure 1 I, by photoetching, etching, in described second metal interlevel insulating barrier 113, etch through hole 114, described through hole 114 is for connecting described first metal interconnecting wires 112 and next metal interconnecting wires;
As shown in figure ij, depositing metal copper fills described through hole 114, metallic copper described in polishing, until expose described second metal interlevel insulating barrier 113, in described second metal interlevel insulating barrier 113, forms metallic copper plug 115;
As shown in figure ik, same procedure is adopted to make the second insulating medium layer and the second interior metal interconnecting wires, the 3rd metal interlevel insulating barrier and interior metallic copper plug thereof, the 3rd insulating medium layer and the 3rd interior metal interconnecting wires, the 4th metal interlevel insulating barrier and interior metallic copper plug thereof, the 4th insulating medium layer and the 4th interior metal interconnecting wires 116 thereof, deposit one passivation layer 117 again, this passivation layer covers whole surface.
For reducing dielectric coefficient (dielectric coefficient), in the manufacturing process of the semiconductor device of below 65nm, every one deck metal interlevel insulating barrier (intermetal dielectric, IMD) and insulating medium layer is formed by deposit amorphous materials (amorphous materials).There is cavity in it in the metal interlevel insulating barrier IMD formed by amorphous materials deposit and insulating medium layer, therefore, such metal interlevel insulating barrier IMD and insulating medium layer very fragile, anti-pressure ability is poor, when follow-up chip package (chippackage) bonding wire, fragile metal interlevel insulating barrier IMD and insulating medium layer easily cave under pressure, thus make chip rejection.
Summary of the invention
The object of the present invention is to provide a kind of method and the chip thereof that strengthen pressure resistance capacity of chip in packaging process, chip compressive resistance ability can be improved, thus improve the reliability (reliability) of chip manufacturing.
To achieve the above object, the invention provides a kind of method strengthening pressure resistance capacity of chip in packaging process, the pattern for the formation of through hole is set up in the redundant area of each metal interlevel insulating layer mask version and the redundant area of each metal interconnecting wires mask, the pattern set up in the redundant area of the n-th metal interconnecting wires mask is corresponding with the pattern set up in the redundant area of the n-th metal interlevel insulating layer mask version, the pattern set up in the redundant area of the (n+1)th metal interlevel insulating layer mask version is corresponding with the pattern set up in the redundant area of the n-th metal interconnecting wires mask, wherein, n=1, 2, 3, N.
The method of above-mentioned enhancing pressure resistance capacity of chip in packaging process, wherein, this chip comprises a lining base, multiple alternately stacked metal interlevel insulating barrier and insulating medium layer and a passivation layer successively, use described n-th metal interlevel insulating layer mask version to etch through hole in the redundant area of chip n-th metal interlevel insulating barrier, use described n-th metal interconnecting wires mask to etch through hole in the redundant area of chip n-th insulating medium layer.
The method of above-mentioned enhancing pressure resistance capacity of chip in packaging process, wherein, through hole in the redundant area of the described n-th insulating medium layer through hole corresponding in the redundant area of described n-th metal interlevel insulating barrier communicates, through hole in the redundant area of the described (n+1)th metal interlevel insulating barrier through hole corresponding in the redundant area of described n-th insulating medium layer communicates, wherein, and n=1,2,3 ..., N.
The method of above-mentioned enhancing pressure resistance capacity of chip in packaging process, wherein, the through hole in the redundant area of described metal interlevel insulating barrier and the through hole in the redundant area of described insulating medium layer alternately superpose successively and extend to described passivation layer from described lining base.
The method of above-mentioned enhancing pressure resistance capacity of chip in packaging process, wherein, each through hole in the redundant area of described n-th metal interlevel insulating barrier is mutually isolated, and each through hole in the redundant area of described n-th insulating medium layer is mutually isolated.
Another technical scheme provided by the invention is, a kind of chip, comprise a lining base, multiple alternately stacked metal interlevel insulating barrier and insulating medium layer and a passivation layer successively, at least one metal pillar is provided with in the redundant area of this chip, described metal pillar extends to described passivation layer from described lining base, and this metal pillar is provided with earth terminal in described lining base.
Said chip, wherein, other circuit electric isolation of described metal pillar and this chip.
Said chip, wherein, described metal pillar alternately to be superposed successively with the metal wire in the redundant area of described insulating medium layer by the metal closures in the redundant area of described metal interlevel insulating barrier and is formed.
Said chip, wherein, described metal pillar is copper pillar.
The method of enhancing pressure resistance capacity of chip in packaging process of the present invention and chip thereof, copper pillar in chip redundancy district plays a supportive role in the process of chip package bonding wire, protect each metal interlevel insulating barrier IMD and insulating medium layer not to cave in, improve the reliability of below 65nm chip manufacturing;
The method of enhancing pressure resistance capacity of chip in packaging process of the present invention and chip thereof, do not need additionally to increase mask, only needs the pattern of the mask to prior art slightly to make an amendment, do not increase cost of manufacture;
The method of enhancing pressure resistance capacity of chip in packaging process of the present invention and chip thereof, each copper pillar in chip redundancy district extends to described passivation layer from described lining base always, effectively prevents less desirable electric capacity, affects chip electric property.
Accompanying drawing explanation
Method and the chip thereof of enhancing pressure resistance capacity of chip in packaging process of the present invention are provided by following embodiment and accompanying drawing.
Figure 1A ~ Fig. 1 K is the process chart manufacturing below 65nm semiconductor device in prior art.
Fig. 2 A ~ Fig. 2 I is the process chart that the method using the present invention to strengthen pressure resistance capacity of chip in packaging process manufactures below 65nm semiconductor device
Embodiment
Below with reference to Fig. 2 A ~ Fig. 2 I, the method for enhancing pressure resistance capacity of chip in packaging process of the present invention and chip thereof are described in further detail.
The present invention strengthens the method for pressure resistance capacity of chip in packaging process, the pattern for the formation of through hole is set up in the redundant area of each metal interlevel insulating layer mask version and the redundant area of each metal interconnecting wires mask, the pattern set up in the redundant area of the n-th metal interconnecting wires mask is corresponding with the pattern set up in the redundant area of the n-th metal interlevel insulating layer mask version, the pattern set up in the redundant area of the (n+1)th metal interlevel insulating layer mask version is corresponding with the pattern set up in the redundant area of the n-th metal interconnecting wires mask, wherein, n=1,2,3,, N.
See Fig. 2 I, chip of the present invention comprises a lining base 201, multiple alternately stacked metal interlevel insulating barrier and insulating medium layer and a passivation layer 217 successively, be provided with at least one metal pillar 224 in the redundant area of this chip, described metal pillar 224 extends to described passivation layer 217 from described lining base 201.
Still for the manufacturing process of below 65nm semiconductor device, describe method and chip thereof that the present invention strengthens pressure resistance capacity of chip in packaging process in detail:
See Fig. 2 A, the surface of lining base 201 is formed with grid, the both sides of described grid are formed with side wall 206, source region and drain region is formed in the both sides of described lining base 201 lower face, described grid, in Fig. 2 A, grid 203a, source region 204a and drain region 205a form p type field effect transistor, and grid 203b, source region 204b and drain region 205b form n type field effect transistor;
Also be formed with isolation channel 202 in the lower face of described lining base 201, described isolation channel 202 is for isolating the element (e.g., field-effect transistor) on described lining base 201;
Insulating barrier 207 between deposit the first metal layer on the surface of described lining base 201, isolation channel 202, grid and side wall 206, between this first metal layer of polishing, insulating barrier 207 makes the surface of insulating barrier 207 between described the first metal layer smooth;
Next between described the first metal layer, through hole will be made in insulating barrier 207, in prior art, the object of making through hole is the metal closures for the element on formation connection lining base and metal interconnecting wires, and in the present invention, between described the first metal layer in insulating barrier 207, except the through hole that making is used for Connection Element and metal interconnecting wires, also between described the first metal layer insulating barrier 207 redundant area (dummy area) in make some through holes, the through hole in described redundant area is not used in Connection Element and metal interconnecting wires;
In the present invention, the step making through hole between described the first metal layer in insulating barrier 207 is, between described the first metal layer insulating barrier 207 surface on spin coating one deck photoresist 301, in mask aligner, pattern in insulating layer mask version 302 between the first metal layer is copied on described photoresist 301, as shown in Figure 2 B, between described the first metal layer, insulating layer mask version 302 adds the pattern for the formation of through hole in its redundant area, in Fig. 2 B, pattern 303a between described the first metal layer in insulating layer mask version 302, 303b, 303c, 303d, 303e, 303f and 303g is for the formation of the through hole (mask of prior art is also provided with these patterns) of Connection Element and metal interconnecting wires, pattern 304 between described the first metal layer in insulating layer mask version 302 redundant area forms through hole (mask of prior art not being provided with this pattern) in the redundant area of insulating barrier 207 between described the first metal layer, in Fig. 2 B, between described the first metal layer insulating layer mask version 302 redundant area in illustrate only a pattern for the formation of through hole, in fact, between described the first metal layer insulating layer mask version 302 redundant area in can comprise multiple pattern for the formation of through hole, pattern between described the first metal layer in insulating layer mask version 302 copies to after on described photoresist 301, by development, etching, through hole is etched in insulating barrier 207 between described the first metal layer, then the photoresist 301 on insulating barrier 207 surface between described the first metal layer is removed, complete the step making through hole between described the first metal layer in insulating barrier 207, as shown in Figure 2 C,
In fig. 2 c, through hole 208a, 208b, 208c, 208d, 208e, 208f and 208g are used for Connection Element and metal interconnecting wires, and the effect of through hole 218 in redundant area does not lie in Connection Element and metal interconnecting wires;
See Fig. 2 D, depositing metal copper fills all through holes between described the first metal layer in insulating barrier 207, metallic copper described in polishing, until expose insulating barrier 207 between described the first metal layer, between described the first metal layer, forms metallic copper plug in insulating barrier 207;
In Fig. 2 D, the metallic copper plug corresponding to described through hole 208a, 208b, 208c, 208d, 208e, 208f and 208g is 209a, 209b, 209c, 209d, 209e, 209f and 209g respectively, and the metallic copper plug corresponding to described through hole 218 is 219;
See Fig. 2 E, between described the first metal layer insulating barrier 207 and metallic copper plug surface on deposit first insulating medium layer 210, this first insulating medium layer 210 of polishing makes the surface of described first insulating medium layer 210 smooth;
Then through hole to be made in described first insulating medium layer 210, in prior art, in described first insulating medium layer 210, make through hole is to form metal interconnecting wires, the metal interconnecting wires formed is for connecting the element on described lining base 201, and in the present invention, in described first insulating medium layer 210, except making the through hole for the formation of the metal interconnecting wires of Connection Element, also in the redundant area of described first insulating medium layer 210, make some through holes, each through hole in described first insulating medium layer 210 redundant area is both not connected, also do not communicate with the through hole in nonredundancy district (in nonredundancy district, some through hole communicates),
The step making through hole in described first insulating medium layer 210 is, spin coating one deck photoresist 401 on the surface of described first insulating medium layer 210, in mask aligner, pattern on first metal interconnecting wires mask 402 is copied on described photoresist 401, as shown in Figure 2 F, described first metal interconnecting wires mask 402 adds the pattern for the formation of through hole in its redundant area, in Fig. 2 F, pattern 403a on described first metal interconnecting wires mask 402, 403b, 403c, 403d, 403e, 403f and 403g is for the formation of the through hole (mask of prior art is also provided with these patterns) of the metal interconnecting wires of Connection Element, pattern 404 in described first metal interconnecting wires mask 402 redundant area forms through hole (mask of prior art not being provided with this pattern) in the redundant area at described first insulating medium layer 210, pattern on described first metal interconnecting wires mask 402 copies to after on described photoresist 401, by development, etching, through hole is etched in described first insulating medium layer 210, then the photoresist 401 on described first insulating medium layer 210 surface is removed, complete the step making through hole in described first insulating medium layer 210, as shown in Figure 2 G,
In fig 2g, through hole 211a, 211b, 211c, 211d, 211e, 211f and 211g are for the formation of the metal interconnecting wires of Connection Element, and the effect of through hole 220 in redundant area does not lie in the metal interconnecting wires forming Connection Element;
In Fig. 2 G, the through hole 220 in described first insulating medium layer 210 redundant area communicates with the metallic copper plug 219 in insulating barrier 207 redundant area between described the first metal layer;
See Fig. 2 H, depositing metal copper fills all through holes in described first insulating medium layer 210, metallic copper described in polishing, until expose described first insulating medium layer 210, metal interconnecting wires 212a is formed in the nonredundancy district of described first insulating medium layer 210, 212b, 212c, 212d, 212e, 212f and 212g, metal wire 221 is formed in the redundant area of described first insulating medium layer 210, described metal interconnecting wires 212a, 212b, 212c, 212d, 212e, 212f with 212g is for being connected the element on described lining base 201, described metal wire 221 communicates with described metallic copper plug 219, the effect of described metal wire 221 does not lie in the element connected on described lining base 201,
Afterwards, make the second metal interlevel insulating barrier and interior metallic copper plug thereof, the method making the second metal interlevel insulating barrier and interior metallic copper plug thereof is identical with the method making insulating barrier and interior metallic copper plug thereof between the first metal layer, similarly, the pattern for the formation of through hole is increased in the redundant area of the second metal interlevel insulating layer mask version, form metallic copper plug 222 in the redundant area of described second metal interlevel insulating barrier, this metallic copper plug 222 communicates with described metal wire 221;
The method making the second insulating medium layer and interior metal interconnecting wires/metal wire thereof is identical with the method making the first insulating medium layer and interior metal interconnecting wires/metal wire thereof, similarly, the pattern for the formation of through hole is increased in the redundant area of the second metal interconnecting wires mask, in the redundant area of described second insulating medium layer, form metal wire 223, described metal wire 223 communicates with metallic copper plug 222;
Same procedure is adopted to produce the 3rd metal interlevel insulating barrier and interior metallic copper plug, the 3rd insulating medium layer and interior metal interconnecting wires/metal wire thereof, the 4th metal interlevel insulating barrier and interior metallic copper plug, the 4th insulating medium layer and interior metal interconnecting wires/metal wire thereof, deposit one passivation layer 217 again, this passivation layer covers whole surface, as shown in figure 2i;
The material of each metal interlevel insulating barrier and each insulating medium layer all adopts amorphous materials.
Each metallic copper plug in same metal interlevel insulating barrier redundant area is both not connected, does not also communicate with the metallic copper plug in same metal interlevel insulating barrier nonredundancy district; Each metal wire in same insulating medium layer redundant area is both not connected, does not also communicate with the metal wire in same insulating medium layer nonredundancy district; Each metal wire in n-th insulating medium layer redundant area metallic copper plug corresponding in the n-th metal interlevel insulating barrier redundant area communicates, and each metal wire corresponding in the n-th insulating medium layer redundant area in the (n+1)th metal interlevel insulating barrier redundant area communicates, wherein n=1,2,3 ..., N; As shown in figure 2i, copper pillar 224 (see Fig. 2 I dotted line circle) is one by one formed like this in the redundant area of chip, electrical connection is not formed between each copper pillar in described chip redundancy district, namely not connected between each copper pillar, each copper pillar in described chip redundancy district is electrically connected with not formed between the metallic copper plug in chip nonredundancy district, metal interconnecting wires, not connected between the metallic copper plug namely in each copper pillar and chip nonredundancy district, metal interconnecting wires; Each copper pillar in described chip redundancy district extends to described passivation layer 217 from described lining base 201 always.
Each copper pillar in described chip redundancy district is equipped with earth terminal in described lining base 201, prevents from producing less desirable electric capacity between each copper pillar, affects chip electric property.
Each copper pillar in described chip redundancy district plays the effect of supporting chip, greatly strengthen the compressive resistance ability of chip, in the process of follow-up chip package bonding wire, owing to there is the supporting role of copper pillar, each metal interlevel insulating barrier IMD and insulating medium layer can not cave in, also would not make chip rejection, improve the reliability of below 65nm chip manufacturing.
The copper pillar made in chip redundancy district does not need additionally to increase mask, only needs the pattern of the mask to prior art slightly to make an amendment, therefore, can not increase cost of manufacture.
Claims (8)
1. one kind strengthens the method for pressure resistance capacity of chip in packaging process, it is characterized in that, this chip comprises a lining base, multiple alternately stacked metal interlevel insulating barrier and insulating medium layer and a passivation layer successively, use the n-th metal interlevel insulating layer mask version to etch through hole in the redundant area of chip n-th metal interlevel insulating barrier, use the n-th metal interconnecting wires mask to etch through hole in the redundant area of chip n-th insulating medium layer;
The pattern for the formation of through hole is set up in the redundant area of each metal interlevel insulating layer mask version and the redundant area of each metal interconnecting wires mask, the pattern set up in the redundant area of the n-th metal interconnecting wires mask is corresponding with the pattern set up in the redundant area of the n-th metal interlevel insulating layer mask version, the pattern set up in the redundant area of the (n+1)th metal interlevel insulating layer mask version is corresponding with the pattern set up in the redundant area of the n-th metal interconnecting wires mask, wherein, n=1,2,3,, N.
2. the method strengthening pressure resistance capacity of chip in packaging process as claimed in claim 1, it is characterized in that, through hole in the redundant area of the described n-th insulating medium layer through hole corresponding in the redundant area of described n-th metal interlevel insulating barrier communicates, through hole in the redundant area of the described (n+1)th metal interlevel insulating barrier through hole corresponding in the redundant area of described n-th insulating medium layer communicates, wherein, and n=1,2,3 ..., N.
3. the method strengthening pressure resistance capacity of chip in packaging process as claimed in claim 2, it is characterized in that, the through hole in the redundant area of described metal interlevel insulating barrier and the through hole in the redundant area of described insulating medium layer alternately superpose successively and extend to described passivation layer from described lining base.
4. strengthen the method for pressure resistance capacity of chip in packaging process as claimed in claim 2 or claim 3, it is characterized in that, each through hole in the redundant area of described n-th metal interlevel insulating barrier is mutually isolated, and each through hole in the redundant area of described n-th insulating medium layer is mutually isolated.
5. a chip, comprise a lining base, multiple alternately stacked metal interlevel insulating barrier and insulating medium layer and a passivation layer successively, it is characterized in that, at least one metal pillar is provided with in the redundant area of this chip, described metal pillar extends to described passivation layer from described lining base, and this metal pillar is provided with earth terminal in described lining base.
6. chip as claimed in claim 5, is characterized in that, other circuit electric isolation of described metal pillar and this chip.
7. the chip as described in claim 5 or 6, is characterized in that, described metal pillar alternately to be superposed successively with the metal wire in the redundant area of described insulating medium layer by the metal closures in the redundant area of described metal interlevel insulating barrier and formed.
8. chip as claimed in claim 7, it is characterized in that, described metal pillar is copper pillar.
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| CN201010153707.8A CN101834153B (en) | 2010-04-22 | 2010-04-22 | Method for enhancing pressure resistance capacity of chip in packaging process and chip thereof |
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| CN112400220B (en) * | 2018-06-29 | 2022-04-22 | 华为技术有限公司 | Integrated circuit and interconnection structure thereof |
| EP4044214A4 (en) * | 2019-11-12 | 2022-11-02 | Huawei Technologies Co., Ltd. | Semiconductor device |
| CN112151485A (en) * | 2020-09-25 | 2020-12-29 | 杰华特微电子（杭州）有限公司 | Packaging structure of semiconductor device and packaging method thereof |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1314710A (en) * | 2000-03-17 | 2001-09-26 | 国际商业机器公司 | Method and structure of pole interconnection |
| CN1531755A (en) * | 2001-03-28 | 2004-09-22 | ��ķ�о�����˾ | Semiconductor structure implementing sacrificial material and methods for making and implementing same |
| CN101241861A (en) * | 2006-06-01 | 2008-08-13 | Amitec多层互连技术有限公司 | Novel multilayered coreless support structure and their fabrication method |
| CN101359620A (en) * | 2007-07-31 | 2009-02-04 | 国际商业机器公司 | Semiconductor structure for reducing resistance of metallic circuit and method of manufacturing same |
-
2010
- 2010-04-22 CN CN201010153707.8A patent/CN101834153B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1314710A (en) * | 2000-03-17 | 2001-09-26 | 国际商业机器公司 | Method and structure of pole interconnection |
| CN1531755A (en) * | 2001-03-28 | 2004-09-22 | ��ķ�о�����˾ | Semiconductor structure implementing sacrificial material and methods for making and implementing same |
| CN101241861A (en) * | 2006-06-01 | 2008-08-13 | Amitec多层互连技术有限公司 | Novel multilayered coreless support structure and their fabrication method |
| CN101359620A (en) * | 2007-07-31 | 2009-02-04 | 国际商业机器公司 | Semiconductor structure for reducing resistance of metallic circuit and method of manufacturing same |
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