CN101826457A - Production method of grid and MOS transistor - Google Patents
Production method of grid and MOS transistor Download PDFInfo
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- CN101826457A CN101826457A CN200910046892A CN200910046892A CN101826457A CN 101826457 A CN101826457 A CN 101826457A CN 200910046892 A CN200910046892 A CN 200910046892A CN 200910046892 A CN200910046892 A CN 200910046892A CN 101826457 A CN101826457 A CN 101826457A
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- corrosion barrier
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Abstract
The invention relates to a production method of a grid and a MOS transistor. The production method of the grid comprises the following steps that: a grid dielectric layer, a polysilicon layer and a corrosion barrier layer are sequentially formed on a semiconductor substrate; a T-shaped masking method is used for etching the corrosion barrier layer until the polysilicon layer is exposed so as to form a reverse-trapezoid rid pattern; and the corrosion barrier layer is used as a mask film, the polysilicon layer is etched along the reverse-trapezoid grid pattern until the grid dielectric layer is exposed so as to form a grid. The production method reduces the error of the critical dimension of the grid, and improves the quality of the grid.
Description
Technical field
The present invention relates to field of manufacturing semiconductor devices, relate in particular to the manufacture method of grid and MOS transistor.
Background technology
Develop rapidly along with semiconductor fabrication, semiconductor device is in order to reach arithmetic speed faster, bigger memory data output and more function, integrated circuit (IC) wafer develops towards higher component density, high integration direction, and the grid size of semiconductor device becomes more and more thinner and length becomes shorter.
In the prior art, the formation of the grid of MOS transistor is mask with the patterning photoresist layer, adopts corrosion barrier layer and polysilicon layer on the dry etching method etching gate dielectric layer, forms grid.Concrete technology as shown in Figure 1, forms gate dielectric layer 102 referring to figs. 1 to Fig. 5 on Semiconductor substrate 100, the method for described formation gate dielectric layer 102 is thermal oxidation method or chemical vapour deposition technique; With chemical vapour deposition technique deposit spathic silicon layer 104 on gate dielectric layer 102; Form amorphous carbon layer 105 with physical vapour deposition (PVD) or chemical gaseous phase depositing process on polysilicon layer 104, it act as the problem that solves the following technology photoresistance of 90nm thickness deficiency; Form corrosion barrier layer 106 with physical vapour deposition (PVD) or chemical gaseous phase depositing process on amorphous carbon layer 105, the material of described corrosion barrier layer 106 is silicon nitride or silicon oxynitride etc., in order in etching process the protection its below rete be not corroded; On corrosion barrier layer 106, form photoresist layer 108 with spin-coating method,, define gate patterns through exposure imaging technology.
As shown in Figure 2, be mask with photoresist layer 108, along gate patterns, with dry etching method etching corrosion barrier layer 106 to exposing amorphous carbon layer 105.Then, adopt ashing method to remove photoresist layer 108.
As shown in Figure 3, be mask with corrosion barrier layer 106, with dry etching method etching amorphous carbon layer 105 to exposing polysilicon layer 104.Then, remove corrosion barrier layer 106 with wet process, be specially aciding, the acid etching solution of employing is phosphoric acid.
As shown in Figure 4, be mask with amorphous carbon layer 105, the etch polysilicon layer forms grid 104a to exposing gate dielectric layer 102.
As shown in Figure 5, adopt the wet etching method to remove amorphous carbon layer 105.
In application number is 200410093459 Chinese patent application, can also find more information relevant with technique scheme, form the method for grid structure.
Along with constantly reducing of the critical dimension of semiconductor device, the thickness of photoresist can not be too thick, and the following institute of 90nm technology is relatively more fragile with photoresist, when exposure, cause the photoresist both sides more coarse easily, coarse like this figure can form the quality that influences grid in the gate process in subsequent etching, as shown in Figure 6, the existing making in the gate process, because line edge roughness (LER, line edge roughness) the influence and the anisotropy of lithographic method, make the critical dimension error of device increasing, and then cause device performance to reduce.
Summary of the invention
The problem that the present invention solves provides the manufacture method of a kind of grid and MOS transistor, prevents that the critical dimension error of device is big.
For addressing the above problem, the invention provides a kind of manufacture method of grid, comprise the following steps: on Semiconductor substrate, to form successively gate dielectric layer, polysilicon layer and corrosion barrier layer; Adopt T type masking method etching corrosion barrier layer to exposing polysilicon layer, form and fall trapezoidal gate patterns; With the corrosion barrier layer is mask, along falling trapezoidal gate patterns etch polysilicon layer to exposing gate dielectric layer, forms grid.
The present invention also provides a kind of manufacture method of MOS transistor, comprising: form gate dielectric layer, polysilicon layer and corrosion barrier layer on Semiconductor substrate successively; Adopt T type masking method etching corrosion barrier layer to exposing polysilicon layer, form and fall trapezoidal gate patterns; With the corrosion barrier layer is mask, along falling trapezoidal gate patterns etch polysilicon layer to exposing gate dielectric layer, forms grid; After removing corrosion barrier layer, in the Semiconductor substrate of grid both sides, form the source-drain electrode extension area successively, form side wall, in the Semiconductor substrate of grid both sides, form source/drain in the grid both sides.
Compared with prior art, the present invention has the following advantages: adopt T type masking method, the etching corrosion barrier layer forms and falls trapezoidal gate patterns; And then, form grid along falling trapezoidal gate patterns etch polysilicon layer.This T type mask can reduce or eliminate fully the transmission of photoresist both sides roughness, makes the roughness at edge terminate in the top top of trapezoidal grid shape figure (promptly fall) of T type mask, reduces the error of gate cd, improves the quality of grid.
Description of drawings
Fig. 1 to Fig. 5 is the schematic diagram that existing technology is made grid;
Fig. 6 is the design sketch of line edge in the existing technology gate process of making;
Fig. 7 is the embodiment flow chart that the present invention makes grid;
Fig. 8 is the embodiment flow chart that the present invention makes MOS transistor;
Fig. 9 to Figure 15 is the embodiment schematic diagram that the present invention makes MOS transistor.
Embodiment
Fig. 7 is the embodiment flow chart that the present invention makes grid.As shown in Figure 7, execution in step S101 forms gate dielectric layer, polysilicon layer and corrosion barrier layer successively on Semiconductor substrate;
The material of described corrosion barrier layer can be silicon nitride or silicon oxynitride etc., and the formation method can be physical vaporous deposition or chemical vapour deposition technique.
Another execution mode after forming polysilicon layer, forms silicon oxide layer with chemical vapour deposition technique on polysilicon layer, it act as the transmission that alleviates follow-up photoresist edge roughness; And then on silicon oxide layer, form corrosion barrier layer.
Also have an execution mode, after forming polysilicon layer, form amorphous carbon layer with chemical vapour deposition technique on polysilicon layer, it act as the deficiency that overcomes follow-up photoresist thickness; Then, form silicon oxide layer with chemical vapour deposition technique on amorphous carbon layer, it act as the transmission that alleviates follow-up photoresist edge roughness; Then, on silicon oxide layer, form corrosion barrier layer again.
Also having an execution mode is after forming polysilicon layer, forms amorphous carbon layer with chemical vapour deposition technique on polysilicon layer, and it act as the deficiency that overcomes follow-up photoresist thickness; And then on amorphous carbon layer, form corrosion barrier layer.
Execution in step S102 adopts T type masking method etching corrosion barrier layer to exposing polysilicon layer, forms to fall trapezoidal gate patterns;
Another execution mode is if be formed with silicon oxide layer between polysilicon layer and corrosion barrier layer; Should adopt T type masking method etching corrosion barrier layer to exposing silicon oxide layer earlier, form and fall trapezoidal gate patterns; Be mask with the corrosion barrier layer then, the etching oxidation silicon layer is to exposing polysilicon layer.
Another execution mode is if be formed with amorphous carbon layer and silicon oxide layer successively between polysilicon layer and corrosion barrier layer; Should adopt T type masking method etching corrosion barrier layer to exposing silicon oxide layer earlier, form and fall trapezoidal gate patterns; Be mask with the corrosion barrier layer then, etching oxidation silicon layer and amorphous carbon layer are to exposing polysilicon layer.
Another execution mode is if be formed with amorphous carbon layer between polysilicon layer and corrosion barrier layer; Should adopt T type masking method etching corrosion barrier layer to exposing amorphous carbon layer earlier, form and fall trapezoidal gate patterns; Be mask with the corrosion barrier layer then, the etching amorphous carbon layer is to exposing polysilicon layer.
Execution in step S103 is a mask with the corrosion barrier layer, along falling trapezoidal gate patterns etch polysilicon layer to exposing gate dielectric layer, forms grid.
Fig. 8 is the embodiment flow chart that the present invention makes MOS transistor.As shown in Figure 8, execution in step S201 forms gate dielectric layer, polysilicon layer and corrosion barrier layer successively on Semiconductor substrate; Execution in step S202 adopts T type masking method etching corrosion barrier layer to exposing polysilicon layer, forms to fall trapezoidal gate patterns; Execution in step S203 is a mask with the corrosion barrier layer, along falling trapezoidal gate patterns etch polysilicon layer to exposing gate dielectric layer, forms grid; Execution in step S204 behind the removal corrosion barrier layer, forms the source-drain electrode extension area successively in the Semiconductor substrate of grid both sides, form side wall in the grid both sides, forms source/drain in the Semiconductor substrate of grid both sides.
The present invention adopts T type masking method, and the etching corrosion barrier layer forms trapezoidal gate patterns; And then, form grid along falling trapezoidal gate patterns etch polysilicon layer.This T type mask can reduce or eliminate fully the transmission of photoresist both sides roughness, makes the roughness at edge terminate in the top top of trapezoidal grid shape figure (promptly fall) of T type mask, reduces the error of gate cd, improves the quality of grid.
Below in conjunction with accompanying drawing the specific embodiment of the present invention is described in detail.
As shown in Figure 9, provide Semiconductor substrate 200, be formed with isolated area (not shown) and the active area between isolated area in the described Semiconductor substrate 200; Form gate dielectric layer 202 on Semiconductor substrate 200, the material of described gate dielectric layer 202 can be silica or silica-silicon-nitride and silicon oxide, and the method that forms gate dielectric layer 202 is thermal oxidation method or chemical vapour deposition technique; With chemical vapour deposition technique deposit spathic silicon layer 204 on gate dielectric layer 202; Form amorphous carbon layer 205 with physical vapour deposition (PVD) or chemical gaseous phase depositing process on polysilicon layer 204, the thickness of described amorphous carbon layer 205 is 500 dusts～1500 dusts, and it act as the deficiency that overcomes follow-up photoresist thickness; Form silicon oxide layer 206 with chemical vapour deposition technique on amorphous carbon layer 205, the thickness of silicon oxide layer 206 is 200 dusts～2500 dusts, act as the transmission that alleviates follow-up photoresist edge roughness; Form corrosion barrier layer 207 with physical vapour deposition (PVD) or chemical gaseous phase depositing process on silicon oxide layer 206, the material of described corrosion barrier layer 207 is silicon nitride or silicon oxynitride etc., in order in etching process the protection its below rete be not corroded; On corrosion barrier layer 206, form photoresist layer 208 with spin-coating method,, on photoresist layer 208, define gate patterns through exposure imaging technology.
As shown in figure 10, be mask with photoresist layer 208, adopt T type masking method,, form and fall trapezoidal gate patterns to exposing silicon oxide layer 206 along gate patterns etching corrosion barrier layer 207.Described lithographic method is a dry etching method, and the gas of employing is the mist of carbon tetrafluoride, argon gas and oxygen, and wherein the flow-rate ratio of carbon tetrafluoride, argon gas and oxygen is 1: 3: 2, and the time that feeds gas is 10 seconds～30 seconds.
As shown in figure 11, remove photoresist layer 208, and then remove residual photoresist layer 208 with the wet etching method with ashing method.With corrosion barrier layer 207 is mask, along falling trapezoidal gate patterns etching oxidation silicon layer 206 and amorphous carbon layer 205 to exposing polysilicon layer 204, the silicon oxide layer 206 after the etching and the size of amorphous carbon layer 205 with fall the minor face of trapezoidal gate patterns and grow consistent.
In the present embodiment, described lithographic method is a dry etching method, and the gas of employing is the mist of carbon tetrafluoride, argon gas and oxygen, and wherein the flow-rate ratio of carbon tetrafluoride, argon gas and oxygen is 1: 3: 2, and the time that feeds gas is 10 seconds～30 seconds.
As shown in figure 12, remove corrosion barrier layer 207 and silicon oxide layer 206 with dry etching method.
Continuation is mask with reference to Figure 12 with amorphous carbon layer 205, to exposing gate dielectric layer 202, forms grid 204a with dry etching method etch polysilicon layer.
In the present embodiment, the gas that the dry etching polysilicon layer is adopted is chlorine and oxygen combination; The flow-rate ratio of described chlorine and oxygen is 1～4, and feeding the gas time is 5s～15s.
As shown in figure 13, remove amorphous carbon layer 205 with the dry etching method, the gas that is adopted in the removal process is O
2And N
2H
2, O
2And N
2H
2Ratio 1: 2.
Continuation is mask with reference to Figure 13 with grid 204a, carries out ion and inject formation source/drain electrode extension area 210 in the Semiconductor substrate 200 of grid 204a both sides.Then, carry out annealing process, make the ions diffusion of injection even.
In the present embodiment, forming the PMOS transistor area, what inject in Semiconductor substrate 200 is p type ion, and described p type ion can be the boron ion; The scope of described p type ion implantation energy value is 500eV～1keV, and p type ion implantation dosage scope is 3E14cm
-2～7E14cm
-2
In the present embodiment, forming nmos transistor region, what inject in Semiconductor substrate 200 is n type ion, and described n type ion can be phosphonium ion or arsenic ion; The scope of described n type ion implantation energy value is 1keV～3keV, and n type ion implantation dosage scope is 5E14～1E15cm
-2
Described annealing process can be annealed and be adopted rapid thermal annealing, pulse annealing or laser annealing.The temperature range of annealing is 1000 ℃～1070 ℃, and the time is 1 second～30 seconds.
In the present embodiment, behind formation source/drain electrode extension area 210, can also continue with grid 204a is mask, carries out the processing step that bag shape is injected (Pocket implant) in the Semiconductor substrate 200 of grid 204a both sides.
With reference to accompanying drawing 14, form side wall 212 in grid 204a both sides, the material of described side wall can for a kind of in silica, silicon nitride, the silicon oxynitride or they constitute.Optimize execution mode for one as present embodiment, described side wall is that silica-silicon-nitride and silicon oxide is formed jointly, and concrete technology is: forming first silicon oxide layer, silicon nitride layer and second silicon oxide layer successively with chemical vapour deposition technique or physical vaporous deposition on the Semiconductor substrate 200 and on the grid 204a; Then, that adopts dry etching eat-backs (etch-back) method etching second silicon oxide layer, silicon nitride layer and first silicon oxide layer to exposing Semiconductor substrate 200 and grid 204a surface, forms side wall 212.
As shown in figure 15, be mask with grid 204a and side wall 212, in the Semiconductor substrate 200 of grid 204a both sides, carry out ion and inject formation source/drain electrode 214.At last, carry out annealing in process, make the ions diffusion of injection even.
In the present embodiment, forming the PMOS transistor area, what inject in Semiconductor substrate 200 is p type ion, and as the boron ion etc., the scope of described ion implantation energy value is 500eV～700eV; The scope of described ion implantation dosage value is 5E14cm
-2～7E14cm
-2
In the present embodiment, forming nmos transistor region, what inject in Semiconductor substrate 200 is n type ion, and as phosphonium ion or arsenic ion etc., the scope of described ion implantation energy value is 1keV～3keV; The scope of described ion implantation dosage value is 5E14cm
-2～1E15cm
-2
Though the present invention with preferred embodiment openly as above; but it is not to be used for limiting the present invention; any those skilled in the art without departing from the spirit and scope of the present invention; can make possible change and modification, so protection scope of the present invention should be as the criterion with the scope that claim of the present invention was defined.
Claims (12)
1. the manufacture method of a grid is characterized in that, comprises the following steps:
On Semiconductor substrate, form gate dielectric layer, polysilicon layer and corrosion barrier layer successively;
Adopt T type masking method etching corrosion barrier layer, expose polysilicon layer, form and fall trapezoidal gate patterns;
With the corrosion barrier layer is mask, along falling trapezoidal gate patterns etch polysilicon layer to exposing gate dielectric layer, forms grid.
2. according to the manufacture method of the described grid of claim 1, it is characterized in that the material of described corrosion barrier layer is silicon nitride or silicon oxynitride.
3. according to the manufacture method of the described grid of claim 2, it is characterized in that the method that forms corrosion barrier layer is physical vapour deposition (PVD) or chemical gaseous phase depositing process.
4. according to the manufacture method of the described grid of claim 1, it is characterized in that, form before the corrosion barrier layer, also comprise: on polysilicon layer, form silicon oxide layer, wherein follow-uply expose polysilicon layer by the etching oxidation silicon layer.
5. according to the manufacture method of the described grid of claim 1, it is characterized in that, form before the corrosion barrier layer, also comprise: on polysilicon layer, form amorphous carbon layer, wherein follow-uply expose polysilicon layer by the etching amorphous carbon layer.
6. according to the manufacture method of the described grid of claim 1, it is characterized in that, form before the corrosion barrier layer, also comprise: on polysilicon layer, form amorphous carbon layer;
On amorphous carbon layer, form silicon oxide layer.
7. the manufacture method of a MOS transistor is characterized in that, comprising:
On Semiconductor substrate, form gate dielectric layer, polysilicon layer and corrosion barrier layer successively;
Adopt T type masking method etching corrosion barrier layer, expose polysilicon layer, form and fall trapezoidal gate patterns;
With the corrosion barrier layer is mask, along falling trapezoidal gate patterns etch polysilicon layer to exposing gate dielectric layer, forms grid;
After removing corrosion barrier layer, in the Semiconductor substrate of grid both sides, form the source-drain electrode extension area successively, form side wall, in the Semiconductor substrate of grid both sides, form source/drain in the grid both sides.
8. according to the manufacture method of the described MOS transistor of claim 7, it is characterized in that the material of described corrosion barrier layer is silicon nitride or silicon oxynitride.
9. the manufacture method of described MOS transistor according to Claim 8 is characterized in that, the method that forms corrosion barrier layer is physical vapour deposition (PVD) or chemical gaseous phase depositing process.
10. according to the manufacture method of the described MOS transistor of claim 7, it is characterized in that, form before the corrosion barrier layer, also comprise: on polysilicon layer, form silicon oxide layer, wherein follow-uply expose polysilicon layer by the etching oxidation silicon layer.
11. the manufacture method according to the described MOS transistor of claim 7 is characterized in that, forms before the corrosion barrier layer, also comprises: on polysilicon layer, form amorphous carbon layer, wherein follow-uply expose polysilicon layer by the etching amorphous carbon layer.
12. the manufacture method according to the described MOS transistor of claim 7 is characterized in that, forms before the corrosion barrier layer, also comprises: form amorphous carbon layer on polysilicon layer;
On amorphous carbon layer, form silicon oxide layer.
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| CN102184962A (en) * | 2011-04-26 | 2011-09-14 | 复旦大学 | Metal oxide semiconductor (MOS) device and manufacturing method thereof |
| CN102412303A (en) * | 2011-11-03 | 2012-04-11 | 中国电子科技集团公司第五十八研究所 | Layout reinforcement structure of large-head strip-shaped grid MOS (metal oxide semiconductor) tube with total-dose radiation effect resistance |
| CN102412128A (en) * | 2010-09-17 | 2012-04-11 | 中芯国际集成电路制造(上海)有限公司 | Manufacturing methods of reversed trapeziform alternative gate and reversed trapeziform metal gate electrode |
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Family Cites Families (4)
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| US5256580A (en) * | 1992-04-06 | 1993-10-26 | Motorola, Inc. | Method of forming a light emitting diode |
| CN1046823C (en) * | 1995-10-24 | 1999-11-24 | 台湾茂矽电子股份有限公司 | Method for manufacturing MOS transistor with low dosed drain and upside-down T shape grid and its structure |
| US8168372B2 (en) * | 2006-09-25 | 2012-05-01 | Brewer Science Inc. | Method of creating photolithographic structures with developer-trimmed hard mask |
| CN100517577C (en) * | 2006-09-30 | 2009-07-22 | 中芯国际集成电路制造(上海)有限公司 | Manufacturing method for grid of semiconductor device |
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| CN102412128A (en) * | 2010-09-17 | 2012-04-11 | 中芯国际集成电路制造(上海)有限公司 | Manufacturing methods of reversed trapeziform alternative gate and reversed trapeziform metal gate electrode |
| CN102184962A (en) * | 2011-04-26 | 2011-09-14 | 复旦大学 | Metal oxide semiconductor (MOS) device and manufacturing method thereof |
| CN102446727A (en) * | 2011-08-29 | 2012-05-09 | 上海华力微电子有限公司 | Etching method of etching hard mask layer containing silicon nitride |
| CN102412303A (en) * | 2011-11-03 | 2012-04-11 | 中国电子科技集团公司第五十八研究所 | Layout reinforcement structure of large-head strip-shaped grid MOS (metal oxide semiconductor) tube with total-dose radiation effect resistance |
| CN103681501A (en) * | 2012-09-12 | 2014-03-26 | 中芯国际集成电路制造(上海)有限公司 | Method for manufacturing semiconductor device |
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| CN103151253A (en) * | 2013-02-22 | 2013-06-12 | 北京京东方光电科技有限公司 | Method for making signal wire, thin film transistor, array substrate and display device |
| CN103151253B (en) * | 2013-02-22 | 2015-07-22 | 北京京东方光电科技有限公司 | Method for making signal wire, thin film transistor, array substrate and display device |
| US9484253B2 (en) | 2013-02-22 | 2016-11-01 | Boe Technology Group Co., Ltd. | Signal line fabrication method, array substrate fabrication method, array substrate and display device |
| CN117082958A (en) * | 2023-10-17 | 2023-11-17 | 致真存储(北京)科技有限公司 | Manufacturing method of magnetic tunnel junction unit and memory |
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