CN101819945B - Manufacturing method of semiconductor device with fuse module - Google Patents
Manufacturing method of semiconductor device with fuse module Download PDFInfo
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- CN101819945B CN101819945B CN 200910118513 CN200910118513A CN101819945B CN 101819945 B CN101819945 B CN 101819945B CN 200910118513 CN200910118513 CN 200910118513 CN 200910118513 A CN200910118513 A CN 200910118513A CN 101819945 B CN101819945 B CN 101819945B
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- interlayer dielectric
- dielectric layer
- fuse assembly
- etching
- assembly
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Abstract
The invention discloses a manufacturing method of a semiconductor device with a fuse module, which comprises the steps: providing a semiconductor structure, which includes a first module region and a second module region; forming the fuse module on the semiconductor structure in the first module region; forming a first interlayer dielectric layer on the fuse module and the semiconductor structure; sequentially forming an etching stopping layer and a second interlayer dielectric layer on the first interlayer dielectric layer; forming a pad on the second dielectric layer in the second module region; forming a protective layer to cover the pad and the second interlayer dielectric layer; forming, in the protective layer, a first opening and a second opening, which are positioned on the fuse module and the pad respectively; exposing the top surface and a part of sidewalls of the etching stopping layer on the fuse module; and leaving another compliant protective layer on the fuse module and the semiconductor structure adjacent to the fuse module.
Description
Technical field
The invention relates to semiconductor fabrication, and a kind of manufacture method with semiconductor device of fuse assembly (fuse element) particularly.
Background technology
In semiconductor device, use fuse assembly (fuse element) at present widely to ressemble storage circuit and gate.For instance, in DRAM (Dynamic Random Access Memory) (DRAM) and static random access memory (SRAM), then can activate a replacement circuit by the fuse assembly that blocks in (blow up) its line related at defective memory cell or circuit, and then form new circuit.The circuit of the fuse assembly that employing can be blocked coiling situation helps the improvement of product yields, thereby can reduce the situation of scrapping of wafer with defective workmanship.
Fuse assembly normally is integrated in an one an of layer of metallized film in the semiconductor device, and it is provided with one to several interlayer dielectric layers (interlayer dielectric layer) and the protective layer (passivation layer) that is positioned at the superiors.Therefore; when adopting laser reconditioning (laser trimming) mode when blocking this fuse assembly; just need partly to remove protective layer and the interlayer dielectric layer that is positioned on the fuse assembly, be the fuse assembly that interlayer dielectric layer was covered of specific thicknesses to form laser importing opening (laser access window) and to expose in advance.Above-mentioned to be covered in the interlayer dielectric layer that laser imports on the fuse assembly that opening exposes be that the protection fuse assembly avoids being subjected to corrosion or damage, and its thickness is relevant with the laser power of blocking fuse assembly.
Because laser imports opening and forms after the protective layer that forms the superiors' layer of metallized film and the superiors usually, it is to form simultaneously when adopting etching mode patterning the superiors protective layer with formation opening in it and exposing weld pad (bond pad).
Therefore; not only etching has penetrated outside the superiors' protective layer when forming the etching of laser importing opening; therefore also etching has penetrated one or more interlayer dielectric layer that is positioned at the below, thicknesses of layers and the uniformity of left interlayer dielectric layer on the wayward fuse assembly that exposes for laser importing opening.
Therefore, import after opening forms in laser, will make and probably can't block the fuse assembly that it covers fully in the follow-up laser reconditioning program if stay blocked up interlayer dielectric layer on the fuse assembly.In addition, if in staying dielectric layer between thin layer on the fuse assembly, then fuse assembly is feared in the preceding corrosion that is subjected to environmental air and aqueous vapor already of accepting follow-up laser reconditioning program, or has been subjected to forming the damage that laser imports the etching program of opening.So unfavorable situation probably can influence the reliability of the semiconductor device with this fuse assembly.
Summary of the invention
In view of this, just need a kind of manufacture method with semiconductor device of fuse-wires structure, preferably to control thickness and the evenness of membranous layer that its inner laser imports interlayer dielectric layer residual in the opening, in order to the carrying out of follow-up laser reconditioning program.
According to an embodiment, the invention provides a kind of manufacture method with semiconductor device of fuse assembly, comprising:
Semiconductor structure is provided, has one first assembly district and one second assembly district; Form on the described semiconductor structure of a fuse assembly in the described first assembly district; Form one first interlayer dielectric layer, conformably cover described fuse assembly and described semiconductor structure; Form an etching stop layer, conformably cover described first interlayer dielectric layer, wherein said etching stop layer comprises silicon oxynitride; Form one second interlayer dielectric layer, the described etching stop layer of smooth covering with covering, wherein said second interlayer dielectric layer has a flat surfaces, and described second interlayer dielectric layer comprises silica; Form on described second interlayer dielectric layer of a weld pad in the described second assembly district; Form a protective layer, conformably cover described weld pad and described second interlayer dielectric layer; Implement the one first etching program that adopts etching gas, the described protective layer of patterning, form one first opening and in the described second assembly district, form one second opening respectively at the described first assembly district, wherein said first opening is positioned on the described fuse assembly and described second interlayer dielectric layer of exposed portions serve, and described second opening on described weld pad and part expose described weld pad; Implement to adopt and contain C
4F
8, CO, Ar and O
2One second etching program of etching gas, remove described second interlayer dielectric layer that exposes for described first opening, end face and the partial sidewall of exposing the described etching stop layer on the described fuse assembly, after the described second etching program was implemented, this second interlayer dielectric layer that stays in this first opening was lower than the end face of its this contiguous etching stop layer and apart from the distance of end face 4000～10000 dusts of its contiguous this second interlayer dielectric layer part of removing without this second etching program; And the execution employing contains CF
4, CHF
3, Ar and O
2One the 3rd etching program of etching gas; remove described first interlayer dielectric layer of described second interlayer dielectric layer that exposes for described first opening, described etching stop layer and part, stay another protective layer of complying with on the described semiconductor structure of the described fuse assembly in described first opening and vicinity thereof.
The circuit of the fuse assembly that employing can be blocked coiling situation helps the improvement of product yields, thereby can reduce the situation of scrapping of wafer with defective workmanship.
Description of drawings
Fig. 1～Fig. 6 is a series of profiles, has shown the manufacture method according to the semiconductor device with fuse assembly of one embodiment of the invention.
Drawing reference numeral
100～semiconductor structure;
102,110～conductive layer;
104,108～interlayer dielectric layer;
106～etching stop layer;
112～protective layer;
114,120,124～etching program;
Opening in 116～assembly district A;
Opening in 118～assembly district B;
A, B～assembly district;
The end face of H1～interlayer dielectric layer 108 is apart from the distance of the end face of conductive layer 102;
The interlayer dielectric layer 108 of H2～stay through etching in opening 116 is apart from the distance of the end face of its contiguous interlayer dielectric layer 108;
The residual interlayer dielectric layer 108 of H3～opening 116 is apart from the distance of the end face of conductive layer 102; And
The residual interlayer dielectric layer 108 of H4～opening 116 is apart from the distance of the end face of semiconductor structure 100.
Embodiment
The present invention will be by hereinafter and cooperate the accompanying drawing of Fig. 1～Fig. 6 and explained orally.Please refer to Fig. 1～a series of profiles shown in Figure 6, shown the enforcement situation according to different phase in the manufacture method of the semiconductor device with fuse assembly of one embodiment of the invention respectively.
Please refer to Fig. 1, semiconductor structure 100 at first is provided, definition has two different assembly district A and assembly district B on it.At this, in order to simplify the purpose of accompanying drawing, semiconductor structure 100 is to illustrate to having the structure of a flat surface, the person skilled in the art can comprise and is arranged at the suprabasil a plurality of semiconductor devices of semiconductor and interconnect structure when understanding semiconductor structure 100, and above-mentioned semiconductor device comprises as the aggressive device of transistor AND gate diode and/or as the passive device of electric capacity, resistance and inductance, and above-mentioned interconnect structure then comprises by interlayer dielectric layer isolation and the multiple film layer metallization structure that supports.In present embodiment, assembly district A is an assembly district that is used for arranging fuse assembly (fuse element), and assembly district B is for being used for arranging an assembly district of weld pad (bond pad).
Then go up formation one conductive layer 102 for one one of the semiconductor structure 100 in assembly district A, with the usefulness as fuse assembly.Conductive layer 102 for example is the single rete of aluminum metal material, or for forming a composite film by aluminium copper (AlCu) and titanium nitride metal material institute storehouses such as (TiN).Conductive layer 102 can form by known metal lead technology, and is not described in detail in this its making.As shown in Figure 1, conductive layer 102 is to illustrate to along extending perpendicular to drawing and be the plain conductor of single rete form, but is not limited the present invention with situation shown in Figure 1.What conductive layer 102 also can have other arranges situation and rete kenel.
Please refer to Fig. 2, then respectively at forming an interlayer dielectric layer 104 on the semiconductor structure 100 in assembly district A and the B.At this, interlayer dielectric layer 104 is the conformably conductive layer 102 in the covering assemblies district A and contiguous semiconductor structure 100 thereof, and the semiconductor structure 100 in the covering assemblies district B.Then respectively at forming an etching stop layer 106 on the interlayer dielectric layer 104 in assembly district A and the B.At this, etching stop layer 106 is interlayer dielectric layers 104 in the covering assemblies district A conformably.
In an embodiment, interlayer dielectric layer 104 can comprise the insulation material as silica, its thickness is approximately between 2000～8000 dusts, and it can form by the combination as ion growth form chemical vapor deposition (PECVD) method, inferior atmospheric pressure chemical vapor deposition method (SACVD) or said method.106 of etching stop layers can comprise the insulation material as silicon oxynitride (SiON), and its thickness is approximately between 100～700 dusts, and it can be by forming as ion growth form chemical vapor deposition (PECVD) method.
Please refer to Fig. 3, the then smooth long-pending insulating material that forms in Shen, ground that covers on structure as shown in Figure 2, with the etching stop layer 106 in covering assemblies district A and the B and then the execution of the planarization program (not shown) by the cmp program go up formation one interlayer dielectric layer 108 with this insulating material of planarization with the etching stop layer 106 in assembly district A and B.At this, interlayer dielectric layer 108 has a flat surfaces.Interlayer dielectric layer 108 can comprise the insulating material as silica, and it can be by forming as ion growth form chemical vapor deposition (PECVD) method.After planarization, the end face of interlayer dielectric layer 108 apart from the end face of conductive layer 102 approximately between a distance H 1 of 2000～8000 dusts.
Then form a conductive layer 110 in the portion of one of surface of the interlayer dielectric layer 108 in assembly district B, with the usefulness as weld pad.Conductive layer 110 for example is the single rete of aluminum metal material, or is a composite film that is formed by aluminium copper (AlCu) and titanium nitride metal material institute storehouses such as (TiN).Conductive layer 110 can form so be not described in detail in this its making by known metal lead technology.
Please refer to Fig. 4, then form a protective layer 112 on the interlayer dielectric layer 108 in assembly district A and B.At this, protective layer 112 is conformably to have covered interlayer dielectric layer 108 and be positioned at conductive layer 110 on the interlayer dielectric layer 108 of assembly district B.Protective layer 112 can comprise the insulation material as silicon nitride (SiN), and its thickness is approximately between 2000～1000 dusts, and it can form by the program as ion growth form chemical vapor deposition (PECVD) method.
Then implement an etching program 114, by using the use of suitable mask pattern (not shown), with patterning protective layer 112 and respectively at forming an opening 116 and another opening 118 in assembly district A and the assembly district B.As shown in Figure 4, opening 116 is positioned at substantially as conductive layer 102 tops of fuse assembly and part and exposes the end face of interlayer dielectric layer 108, opening 118 then only part expose the end face of the conductive layer of using as weld pad 110.At this, etching program 114 for example is a dry etching program, and it adopts and contains CF
4, CHF
3, SF
6With the etching gas of Ar with the protective layer 112 of removing part and stop on the interlayer dielectric layer 108.
Please refer to Fig. 5; then implement another etching program 120; be etch mask with the patterned protective layer 112 shown in Fig. 4, remove interlayer dielectric layer 108 that the opening 116 for assembly district A exposes exposes the etching stop layer 106 that is positioned at conductive layer 102 tops until part end face and partial sidewall.Above-mentioned etching program 120 for example is a dry etching program, and it can adopt and contain C
4F
8, CO, Ar and O
2Etching gas to remove interlayer dielectric layer 108 and to stop on the etching stop layer 106.In etching program 120, more comprise an overetch step, guarantee that the interlayer dielectric layer 108 on the end face of etching stop layer 106 can be removed fully.Therefore, last interlayer dielectric layer 108 left in opening 116 will be a little less than the end face of its contiguous etching stop layer 106 and apart from the distance H 2 of its vicinity without about 4000～10000 dusts of end face of interlayer dielectric layer 108 parts of etching removal.
Please refer to Fig. 6; then implement another etching program 124; adopting patterned protective layer 112 is etch mask; with the etching stop layer 106 in the opening 116 of removing assembly district A, on the semiconductor structure 100 of conductive layer 102 surfaces and vicinity thereof, to stay the interlayer dielectric layer 104 through the etching thinning.
At this, above-mentioned etching program 124 for example is a dry etching program, and it adopts and contains CF
4, CHF
3, Ar and O
2Etching gas to remove the etching stop layer 108 in the opening 116 and to be positioned at part interlayer dielectric layer 108 on the etching stop layer 106, and in this etching program 124, more comprise an overetch technology, remove interlayer dielectric layer 104 parts in the opening 116 with part, therefore in the residual interlayer dielectric layer 108 of opening 116 respectively apart from the end face of the end face of conductive layer 102 and semiconductor structure 100 approximately between 2000～6000 dusts and between distance H 3 and the H4 of 0～5000 dust.
At this moment; laser when the laser reconditioning program (not shown) that opening 116 is follow-up execution is used imports opening; and be that interlayer dielectric layer 104 parts that opening 116 exposes are the usefulness as fuse assembly (being conductive layer 102) top protective layer, and owing to be positioned on conductive layer 102 end faces and the thickness of contiguous semiconductor structure 100 first-class parts then can be by being controlled in the thickness between 2000～7000 dusts respectively as the execution of the etching program of the multiple step of Fig. 4～shown in Figure 6.Therefore; owing to be positioned on conductive layer 102 end faces and interlayer dielectric layer 104 thickness of contiguous semiconductor structure 100 first-class parts are close; help to produce the protective layer of the fuse assembly with preferable uniform film thickness degree, thereby help the execution of follow-up laser reconditioning program and have the yields of semiconductor device of this fuse assembly and the lifting of reliability.
Though the present invention discloses as above with preferred embodiment; so it is not in order to limit the present invention; any those skilled in the art; without departing from the spirit and scope of the present invention; when can being used for a variety of modifications and variations, so protection scope of the present invention is as the criterion when looking claim scope institute confining spectrum.
Claims (9)
1. the manufacture method with semiconductor device of fuse assembly is characterized in that, described method comprises:
Semiconductor structure is provided, has one first assembly district and one second assembly district;
Form on the described semiconductor structure of a fuse assembly in the described first assembly district;
Form one first interlayer dielectric layer, conformably cover described fuse assembly and described semiconductor structure;
Form an etching stop layer, conformably cover described first interlayer dielectric layer, wherein said etching stop layer comprises silicon oxynitride;
Form one second interlayer dielectric layer, the described etching stop layer of smooth covering with covering, wherein said second interlayer dielectric layer has a flat surfaces, and described second interlayer dielectric layer comprises silica;
Form on described second interlayer dielectric layer of a weld pad in the described second assembly district;
Form a protective layer, conformably cover described weld pad and described second interlayer dielectric layer;
Implement the one first etching program that adopts etching gas, the described protective layer of patterning, form one first opening and in the described second assembly district, form one second opening respectively at the described first assembly district, wherein said first opening is positioned on the described fuse assembly and described second interlayer dielectric layer of exposed portions serve, and described second opening on described weld pad and part expose described weld pad;
Implement to adopt and contain C
4F
8, CO, Ar and O
2One second etching program of etching gas, remove described second interlayer dielectric layer that exposes for described first opening, end face and the partial sidewall of exposing the described etching stop layer on the described fuse assembly, after the described second etching program was implemented, this second interlayer dielectric layer that stays in this first opening was lower than the end face of its this contiguous etching stop layer and apart from the distance of end face 4000～10000 dusts of its contiguous this second interlayer dielectric layer part of removing without this second etching program; And
Implement to adopt and contain CF
4, CHF
3, Ar and O
2One the 3rd etching program of etching gas; remove described first interlayer dielectric layer of described second interlayer dielectric layer that exposes for described first opening, described etching stop layer and part, stay another protective layer of complying with on the described semiconductor structure of the described fuse assembly in described first opening and vicinity thereof.
2. the manufacture method with semiconductor device of fuse assembly as claimed in claim 1 is characterized in that, described first interlayer dielectric layer comprises silica, and described protective layer comprises silicon nitride.
3. the manufacture method with semiconductor device of fuse assembly as claimed in claim 1 is characterized in that, the described first etching program contains CF for adopting
4, CHF
3, SF
6Dry etching program with the etching gas of Ar.
4. the manufacture method with semiconductor device of fuse assembly as claimed in claim 1 is characterized in that, the described second etching program is a dry etching program.
5. the manufacture method with semiconductor device of fuse assembly as claimed in claim 1; it is characterized in that; after described the 3rd etching program is implemented, stay described another protective layer of complying with on the described fuse assembly in described first opening and the contiguous described semiconductor structure thereof in having between the thickness of 0～5000 dust on the surface of described fuse-wires structure and on described semiconductor structure, having thickness between 2000～6000 dusts.
6. the manufacture method with semiconductor device of fuse assembly as claimed in claim 1 is characterized in that, described fuse assembly comprises aluminium.
7. the manufacture method with semiconductor device of fuse assembly as claimed in claim 1 is characterized in that, described fuse assembly comprises aluminium copper and titanium nitride.
8. the manufacture method with semiconductor device of fuse assembly as claimed in claim 1 is characterized in that, described weld pad comprises aluminium.
9. the manufacture method with semiconductor device of fuse assembly as claimed in claim 1 is characterized in that, described weld pad comprises aluminium copper and titanium nitride.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200910118513 CN101819945B (en) | 2009-02-26 | 2009-02-26 | Manufacturing method of semiconductor device with fuse module |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200910118513 CN101819945B (en) | 2009-02-26 | 2009-02-26 | Manufacturing method of semiconductor device with fuse module |
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|---|---|
| CN101819945A CN101819945A (en) | 2010-09-01 |
| CN101819945B true CN101819945B (en) | 2013-08-07 |
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Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2013168491A (en) * | 2012-02-15 | 2013-08-29 | Semiconductor Components Industries Llc | Manufacturing method of semiconductor device |
| CN104576603A (en) * | 2013-10-28 | 2015-04-29 | 北大方正集团有限公司 | Integrated circuit including laser fuse wire and manufacturing method thereof |
| CN108878404A (en) * | 2018-06-29 | 2018-11-23 | 上海华虹宏力半导体制造有限公司 | Chip Internal fuse structure |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1499603A (en) * | 2002-11-04 | 2004-05-26 | 台湾积体电路制造股份有限公司 | Fuse wire possessing cover layer and forming method |
| CN101211779A (en) * | 2006-12-29 | 2008-07-02 | 联华电子股份有限公司 | Method for forming fuse window on semiconductor substrate web by two- stage etching mode |
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2009
- 2009-02-26 CN CN 200910118513 patent/CN101819945B/en active Active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1499603A (en) * | 2002-11-04 | 2004-05-26 | 台湾积体电路制造股份有限公司 | Fuse wire possessing cover layer and forming method |
| CN101211779A (en) * | 2006-12-29 | 2008-07-02 | 联华电子股份有限公司 | Method for forming fuse window on semiconductor substrate web by two- stage etching mode |
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| CN101819945A (en) | 2010-09-01 |
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