CN101819537B - False-alarm simulation method for built-in test of circuit - Google Patents
False-alarm simulation method for built-in test of circuit Download PDFInfo
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- CN101819537B CN101819537B CN 201010103319 CN201010103319A CN101819537B CN 101819537 B CN101819537 B CN 101819537B CN 201010103319 CN201010103319 CN 201010103319 CN 201010103319 A CN201010103319 A CN 201010103319A CN 101819537 B CN101819537 B CN 101819537B
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Abstract
The invention discloses a false-alarm simulation method for a built-in test of a circuit, which comprises the following steps of: 1, building a false-alarm simulation section model; 2, building a sub-circuit model of a false-alarm activating event; 3, accessing the false-alarm activating event; 4, performing false-alarm simulation; and 5, analyzing false-alarm simulation results. In the invention, the false-alarm simulation analysis is completed by building the false-alarm simulation section model and the false-alarm activating event and allowing the false-alarm activating event to access the circuit BIT simulation model under the control of time, so the method can be used for the false-alarm rejection capability analysis and the false-alarm mechanical analysis in the circuit design and research and also can be used for the post false-alarm analysis in the using stage of the circuit to perform false-alarm recurrence. The false-alarm simulation method for the built-in test of the circuit has a significant application value in the aspect of improving the circuit BIT false-alarm design capability and overcomes the defect that the BIT false-alarm estimation only depends on the test and the use experience and the defect of lacking simulation analysis means.
Description
Technical field
The present invention relates to a kind of false-alarm simulation method of built-in test of circuit, belong to electronic system testability technical field.
Background technology
(Built-In Test BIT) is meant the detection that electronic product inside provides and the automatic test capability of isolated fault, is the ingredient of electronic product in built-in test.BIT is main method and the means that improve the testability level, also is the important content of testability design analysis.Along with the raising of product complexity, BIT has become a kind of important channel of improving the electronic product diagnosis capability.Utilize BIT to detect automatically and isolated fault, the MTTR of electronic product is significantly reduced, improve the availability of electronic product; Utilize BIT can reduce the maintenance personal quantity, reduce technical merit requirement to the maintenance personal, and then reduce and use and the guarantee expense.
False-alarm is the phenomenon that BIT indicates to be had fault and in fact do not have fault.The fault detect of BIT and isolation rate are high more, and the BIT range of application is many more, and the false-alarm that then possibly cause taking place is many more.The appearance of false-alarm makes correct indication rate and the validity of BIT descend, and causes too much maintenance and wastes test and keep in repair resource, in task, might cause ignoring true fault to cause serious consequence, influences security.Engineering practice history both domestic and external shows that all false-alarm is the obstacle that always exists in BIT application and the development course, and the adverse effect that false-alarm produces mainly contains:
(1) in the electronic product course of work, the existence of false-alarm has reduced the correct indication fault number of BIT shared ratio in the sum that breaks down, and causes correct indication rate and the validity of BIT decline is all arranged.
(2) in the electronic product course of work, false-alarm causes the operator still need take measures to deal with in trouble-free situation, and is concrete as adopt back-up job pattern, degradation work, switch operating remaining even quit work etc.If false alarm rate is too high, the operator can lose confidence to BIT, can ignore even no matter BIT indication, this is very dangerous in task, might cause serious adverse consequences when for example true fault occurring, even influence safety.
(3) in the electronic product course of work, if BIT is the indication of breaking down, the correction maintenance personnel just need test and task after check.Take place before if false-alarm then can cause invalid maintenance, also can reduce the availability of system.If false alarm rate is too high, has then lost BIT and improved system maintenance property and the effect of simplifying maintenance.
Because false-alarm betides field trial or actual operational phase mostly; Measure with record all comparatively difficult; Add the more and mechanism reproduction difficulty of the reason that causes false-alarm to occur; So up to now, still not having effective ways and means to be implemented in the design phase carries out false-alarm analysis, reproduction to BIT and predicts.At present in the public technology data about BIT false-alarm problem, have only adopt reliability test method and through product in kind try out, make the technical method that is used for finding the BIT false-alarm, do not utilize emulation to carry out the method that the BIT false-alarm is analyzed.
Summary of the invention
The objective of the invention is in order to address the above problem; A kind of false-alarm simulation method of built-in test of circuit is proposed; Mainly bring out incident, and it is linked in the electronic circuit BIT realistic model, realize the simulation analysis and the reproduction of false-alarm through setting up false-alarm simulation section model and false-alarm.
The false-alarm simulation method of a kind of built-in test of circuit of the present invention comprises following step:
Step 1: set up the false-alarm simulation section model;
1), sets the composition of operation profile model and false-alarm simulation section model;
(1) composition of operation profile model;
Operation profile model P
MFor:
P
M＝(D，HT，EL，t
M) (1)
In the formula: D---the disturbance set in the operation profile model, D={d
i| i=1～n}, di are the circuit the i time disturbance that receives in service; N is the total degree of disturbance; The time of origin set of HT---disturbance, HT={ (ht
i, ct
i) | i=1～n}, ht
iIt is the start time of i disturbance; Ct
iIt is the duration of i disturbance; EL---disturbance is to the impact position set of circuit, EL={el
i| i=1～n}, el
iThe concrete impact position of table an i disturbance in circuit; t
M---the task duration that the operation profile model is corresponding;
(2) composition of false-alarm simulation section model;
False-alarm simulation section model P
FAFor:
P
FA＝(E，T，L，t
S) (2)
In the formula: E---false-alarm is brought out event sets, E={e
j| j=1～h}, e
jJ false-alarm in the expression set brought out incident; H representes that the false-alarm that comprises in the false-alarm simulation section model brings out incident quantity; (S), y representes that false-alarm brings out event type to e=for y, m; M representes that false-alarm brings out the analog form of incident; S representes that false-alarm brings out the event argument set of incident; T---time value set, T={ (rt
j, ot
j) | j=1～h}, rt
jRepresent that j false-alarm bring out value turn-on time of incident; Ot
jRepresent that j false-alarm bring out value post-set time of incident; L---access point set, L={l
j| j=1～h}, l
jRepresent that j the false-alarm incident of bringing out is linked into the position in the circuit; t
S---false-alarm simulation section model corresponding simulation duration;
2), according to operation profile modelling false-alarm simulation section model;
A, confirm that according to the disturbance in the operation profile model false-alarm in the false-alarm simulation section model brings out incident;
Each disturbance in the operation profile model is all set up the false-alarm of a correspondence and is brought out incident, confirms that false-alarm brings out the event type of incident, analog form and event argument;
B, confirm that according to the impact position of disturbance false-alarm brings out the access point of incident;
The impact position of disturbance is that disturbance is incorporated into the position in the circuit in the operation profile model, should insert false-alarm at the correspondence position of circuit model and bring out incident, and correspondence position promptly is the access point that false-alarm is brought out incident in the circuit model;
C, confirm the time parameter in the false-alarm simulation section model according to the time parameter in the operation profile model;
According to the task duration in the operation profile model, disturbance start time, disturbance duration; Through Time Compression, determine the emulation duration in the corresponding false-alarm simulation section model, the turn-on time that false-alarm is brought out incident, the post-set time that false-alarm is brought out incident;
Through Time Compression, reduce the time loss of emulation;
D, the false-alarm simulation section model is carried out integral body describe;
After the incident of bringing out, access point and the event argument of having confirmed the false-alarm simulation section model, need carry out integral body to the false-alarm simulation section model and describe; The whole description combines operation profile model and false-alarm simulation section model, describes content and is:
The operation profile model comprises task duration, disturbance, disturbance start time, disturbance duration, disturbing influence position;
The false-alarm simulation section model comprises emulation duration, Case Number, event type, event simulation mode, event argument, turn-on time, post-set time, access point;
Described Case Number is for to be provided with numbering to the false-alarm incident of bringing out;
Set up the sub circuit model that false-alarm is brought out incident according to event type, analog form and event argument, sub circuit model set inside ground connection externally has only the single face point, and the circuit between ground connection and point of interface has event simulation mode and event argument function;
False-alarm is brought out the corresponding sub circuit model of incident be linked in the realistic model of circuit, the sub circuit model that h false-alarm brought out incident is connected with access point accordingly through the interface of correspondence;
The function of interface comprises: inserted automatically by the incident of control turn-on time; Automatically withdrawed from by the incident of control post-set time;
Operation emulation; The length of simulation time should be set to the emulation duration of appointment in the false-alarm simulation section model;
Step 5, false-alarm simulation interpretation of result;
After emulation finishes, obtain the timing waveform of BIT indication, carry out the analysis and the judgement of BIT false-alarm according to this waveform; If the false-alarm incident of bringing out causes the BIT indication fault, false-alarm has then taken place;
Comprehensive false-alarm simulation section model and analysis result are described false-alarm simulation result's integral body through form, and content comprises: false-alarm is brought out Case Number, event type, the false-alarm number of times that BIT indicates, incident is corresponding of incident correspondence, the total false-alarm number of times of false-alarm simulation section model in the false-alarm simulation section model.
The invention has the advantages that:
(1) the present invention is through setting up false-alarm simulation section model, false-alarm and bring out incident and incident being linked in the realistic model of circuit BIT by time control; Accomplish the simulation analysis of false-alarm; The false-alarm that both can be used for circuit design research suppresses capability analysis, false-alarm Analysis on Mechanism; Also can be used for the analysis of false-alarm afterwards of circuit operational phase, carry out the false-alarm reproduction;
(2) the present invention has significant application value to the anti-false-alarm designed capacity of the BIT that improves circuit, and has remedied the deficiency that can only rely on test and use discovery and assessment BIT false-alarm at present, lack the simulation analysis means.
Description of drawings
Fig. 1 is a method flow diagram of the present invention;
Fig. 2 is that the present invention is according to operation profile modelling false-alarm simulation section model synoptic diagram;
Fig. 3 is a Time Compression synoptic diagram of the present invention;
Fig. 4 is the general sub circuit model that false-alarm of the present invention is brought out incident;
Fig. 5 is the access way synoptic diagram that false-alarm of the present invention is brought out event model;
Fig. 6 is an interface synoptic diagram of the present invention;
Fig. 7 is the circuit model of the embodiment of the invention;
Fig. 8 is that embodiment of the invention false-alarm is brought out the incident sub circuit model;
Fig. 9 is the circuit model of embodiment of the invention false-alarm simulation section model;
Figure 10 is the simulation result curve map of the embodiment of the invention.
Embodiment
To combine accompanying drawing and embodiment that the present invention is done further detailed description below.
The present invention is a kind of false-alarm simulation method of built-in test of circuit, and flow process is as shown in Figure 1, comprises following step:
Step 1: set up the false-alarm simulation section model;
When side circuit is worked under specific operation profile model environment, can receive specific disturbance, thereby cause BIT false-alarm to occur, operation profile is different, and its quantity that false-alarm occurs is also different.When carrying out circuit BIT false-alarm simulation; False-alarm simulation section model that need be corresponding according to the operation profile modelling of circuit; Emulation to circuit applies disturbance, judges whether BIT false-alarm occurs, thus the BIT false-alarm number of times that statistics false-alarm simulation section model causes.
1, sets the composition of operation profile model and false-alarm simulation section model;
(1) composition of operation profile model;
The operation profile model is to describe according to disturbance and sequential relationship thereof that the operation demand of circuit is confirmed.Operation profile model P
MFormula be:
P
M＝(D，HT，EL，t
M) (1)
In the formula: D---the disturbance set in the operation profile model, D={d
i| i=1～n}, di are the circuit the i time disturbance that receives in service; N is the total degree of disturbance; The time of origin set of HT---disturbance, HT={ (ht
i, ct
i) | i=1～n}, ht
iIt is the start time of i disturbance; Ct
iIt is the duration of i disturbance; EL---disturbance is to the impact position set of circuit, EL={el
i| i=1～n}, the concrete impact position of i disturbance of eli table the in circuit; t
M---the task duration that the operation profile model is corresponding.
(2) composition of false-alarm simulation section model;
The false-alarm simulation section model is according to the operation profile modelling of circuit, and the false-alarm that is used for the BIT false-alarm simulation brings out incident and sequential relationship is described.False-alarm simulation section model P
FAFormula following:
P
FA＝(E，T，L，t
S) (2)
In the formula: E---false-alarm is brought out event sets, E={e
j| j=1～h}, e
jJ false-alarm in the expression set brought out incident; H representes that the false-alarm that comprises in the false-alarm simulation section model brings out incident quantity; (S), y representes that false-alarm brings out event type to e=for y, m; M representes that false-alarm brings out the analog form of incident; S representes that false-alarm brings out the event argument set of incident; T---time value set, T={ (rt
j, ot
j) | j=1～h}, rt
jRepresent that j false-alarm bring out value turn-on time of incident; Ot
jRepresent that j false-alarm bring out value post-set time of incident; L---access point set, L={l
j| j=1～h}, l
jRepresent that j the false-alarm incident of bringing out is linked into the position in the circuit; t
S---false-alarm simulation section model corresponding simulation duration.
2, according to operation profile modelling false-alarm simulation section model;
Relation between operation profile model and the false-alarm simulation section model is as shown in Figure 2, and is following according to the step of operation profile modelling false-alarm simulation section model:
(1) confirms that according to the disturbance in the operation profile model false-alarm in the false-alarm simulation section model brings out incident;
Each disturbance in the operation profile model is all set up the false-alarm of a correspondence and is brought out incident.The type, analog form and the event argument that when setting up false-alarm and bring out incident, also need clear and definite incident.
The type that false-alarm is brought out incident depends on the disturbance type in the operation profile model.The disturbance type is divided into the load action and disturbs two types, and the type that therefore corresponding false-alarm is brought out incident is respectively load disturbance and interference.
The analog form that false-alarm is brought out incident is load disturbance and two big types of interference by the disturbance classification of type also.Wherein, load disturbance can be selected following analog form: resistive load, inductive load, capacitive load, the SP combination load of resistive, perceptual, capacitive.Interference can be selected following analog form: sine wave signal, square-wave signal, triangular signal, voltage source, current source, the combination of various types of signal.
After having confirmed that false-alarm is brought out the analog form of incident, also need determine the event argument relevant with level of disruption.The content of event argument is directly related with the analog form of incident, brings out the event simulation load disturbance as adopting resistive load as false-alarm, should determine the resistance value of resistive load according to loading condition, and this resistance value promptly is an event argument.
(2) confirm that according to the impact position of disturbance false-alarm brings out the access point of incident;
The impact position of disturbance is that disturbance is incorporated into the position in the circuit in the operation profile model, in false-alarm simulation, need insert false-alarm at the correspondence position of circuit model and bring out incident.According to the impact position of disturbance, the correspondence position in circuit model confirms that false-alarm brings out the access point of incident.
(3) confirm the time parameter in the false-alarm simulation section model according to the time parameter in the operation profile model;
When carrying out the BIT false-alarm simulation, need carry out Time Compression, to reduce the time loss of emulation.According to the task duration in the operation profile model, disturbance start time, disturbance duration; Through Time Compression, determine the emulation duration in the corresponding false-alarm simulation section model, the turn-on time that false-alarm is brought out incident, the post-set time that false-alarm is brought out incident.
The method of carrying out Time Compression is:
Because the BIT false-alarm only possibly occur in noisy state, carry out the vast scale compression working time after therefore disappearing for interference.If interference can cause the BIT false-alarm, then usually after interference applies, false-alarm will take place, and disturbs the time length that continues only to influence the time length that the BIT false-alarm exists, and therefore as required duration of disturbance is compressed.For example, as shown in Figure 3, first disturbs corresponding first false-alarm to bring out incident ... N disturbs corresponding n false-alarm to bring out incident; Circuit boil down to working time first false-alarm between first interference is disturbed to second is brought out incident to the second false-alarm and is brought out the simulation time between the incident ... Circuit boil down to working time n-1 false-alarm between the n-1 interference is disturbed to n is brought out incident to the n false-alarm and is brought out the simulation time between the incident; Duration boil down to first false-alarm of first interference is brought out the simulation time of incident ... The duration boil down to n false-alarm that n disturbs is brought out the simulation time of incident.So far, just the false-alarm simulation time of the circuit boil down to working time below arrow representative of top arrow representative.
(4) the false-alarm simulation section model being carried out integral body describes;
After the incident of bringing out, access point and the event argument of having confirmed the false-alarm simulation section model, need carry out integral body to the false-alarm simulation section model and describe.The whole description combines operation profile model and false-alarm simulation section model, describes content and is:
The operation profile model comprises task duration, disturbance, disturbance start time, disturbance duration, disturbing influence position;
The false-alarm simulation section model comprises emulation duration, Case Number, event type, event simulation mode, event argument, turn-on time, post-set time, access point;
Wherein, the Case Number letter, "-" number that bring out event type by representative with represent the numeral of sequence number to form.For load disturbance, adopt F to represent, for interference, adopt alphabetical G to represent.For example, the F-1 false-alarm of explaining the 1st load disturbance type is brought out incident.
Describe in integral body on the basis of content, the form shown in the employing table 1 is expressed.
The description form of table 1 false-alarm simulation section model
In the false-alarm simulation section model according to the operation profile modelling, clear and definite false-alarm is brought out type, pattern mode and the event argument of incident.In order the false-alarm incident of bringing out to be converted into the model of emulation, need set up the sub circuit model that concrete false-alarm is brought out incident according to event type, analog form and event argument.
It is as shown in Figure 4 that false-alarm is brought out the general sub circuit model of incident; Described false-alarm is brought out incident sub circuit model set inside ground connection and is provided with; Externally have only single point of interface, between ground connection and point of interface, accomplish sub circuit model with event simulation mode and event argument function.
The setting of analog form and event argument is specially in the sub circuit model of the present invention:
Resistive load adopts resistance to realize that event argument corresponds to resistance value;
Inductive load adopts inductance to realize that event argument corresponds to inductance value;
Capacitive load adopts electric capacity to realize that event argument corresponds to capacitance;
Combination load adopts resistance, inductance, electric capacity SP to realize that event argument corresponds to resistance value, inductance value, capacitance;
Sine wave signal adopts sine wave source to realize that event argument corresponds to sinusoidal wave peak-to-peak value, frequency;
Square-wave signal adopts square-wave signal source to realize that event argument corresponds to square wave amplitude, frequency, dutycycle;
Triangular signal adopts triangular wave signal source to realize that event argument corresponds to triangular wave peak-to-peak value, frequency, rise time, fall time;
Voltage signal adopts voltage source to realize that event argument corresponds to interchange, dc voltage value;
Current signal adopts current source to realize that event argument corresponds to interchange, DC current values.
For the false-alarm incident of bringing out can be exerted an influence to circuit, false-alarm is brought out the corresponding sub circuit model of incident be linked in the realistic model of circuit.
It is as shown in Figure 5 that each false-alarm incident of bringing out in the false-alarm simulation section model is linked into the synoptic diagram of circuit model, and the sub circuit model that n false-alarm brought out incident is connected with n access point of appointment through n interface of correspondence.
The function of interface comprises: inserted automatically by the incident of control turn-on time; Automatically withdrawed from by the incident of control post-set time.
The time control switch that can once move and the time control pass switch that adopt conventional EDA emulation tool generally to provide carry out tandem compound realization interface function.
Be set to the automatic turn-on time that switch is closed in time control the turn-on time that false-alarm is brought out incident, and false-alarm is brought out the automatic cutout time that is set to the time control switch post-set time of incident.
The circuit form of interface is as shown in Figure 6, and K switch is closed in time control
1Default conditions for breaking off, put auto-closing in the turn-on time that is provided with; The time control K switch
2Default conditions be closed, automatic cutout post-set time that is being provided with.Through the tandem compound of this two kinds of switches, realize false-alarm bring out incident sub circuit model automatic access and withdraw from.
After the false-alarm incident of bringing out in the false-alarm simulation section model is linked into breadboardin, operation emulation.Through carrying out time-domain-simulation, obtain the timing waveform of BIT monitor signal and indication.The length of simulation time should be set to the emulation duration of appointment in the false-alarm simulation section model.
Step 5, false-alarm simulation interpretation of result;
Each false-alarm in the emulation section model is brought out incident and all may be exerted an influence to the BIT indication.After emulation finishes, obtain the timing waveform of BIT indication, carry out the analysis and the judgement of BIT false-alarm according to this waveform.If the false-alarm incident of bringing out causes the BIT indication fault, false-alarm has then taken place.
False-alarm simulation result's integral body is described and is combined false-alarm simulation section model and analysis result; Content comprises: Case Number, event type, the corresponding BIT of incident indicate (fault/non-fault), the false-alarm number of times of incident correspondence, the total false-alarm number of times of false-alarm simulation section model, and the false-alarm simulation form shown in the employing table 2 is as a result expressed.
Table 2 false-alarm simulation result's through engineering approaches form
In the table 2, the result of BIT indication beats " √ " in " fault ", " non-fault " hurdle; The false-alarm number of times is filled in the false-alarm number of times of corresponding BIT; " total " filled in the false-alarm sum of BIT.
Below in conjunction with the typical circuit instance this method invention is explained further details.
The schematic diagram of certain switching power supply circuit and BIT thereof is as shown in Figure 7.The first half is the switching power supply circuit among the figure, and the latter half is the BIT circuit.Adopt the general EDA OrCAD PSPICE of simulation software to carry out the false-alarm simulation of circuit BIT.
Step 1: set up the false-alarm simulation section model;
According to the expection operation profile model of this switching power supply circuit, set up the false-alarm simulation section model of circuit, as shown in table 3.
Table 3 false-alarm simulation section model is represented example
In the operation profile model of circuit, 6 disturbances are arranged, comprise that 4 load disturbances and 2 signals disturb, the time and the duration of its generation all list in table 3 in detail.According to the disturbance in the operation profile model, set up corresponding false-alarm simulation section model, bring out incident comprising the false-alarm of 6 correspondences, settings such as its event simulation mode, event argument, time value, access point are all listed in table 4 in detail.Wherein, access point OUTPUT, NOISE3 indicate in Fig. 8.
According to the false-alarm simulation section model of setting up, it is as shown in Figure 8 that 6 false-alarms of the components and parts modelling that employing OrCAD software provides are brought out the incident electronic circuit.
Wherein, F-1, F-2, F-3, F-4 load action in RF-1, RF-2, RF-3, the RF-4 difference correspondence table 3, G-1, G-2 in VG-1, the VG-2 difference correspondence table 3 disturb.
Employing is based on the interface circuit design of time switch, and the realization false-alarm is brought out the access of incident sub circuit model.False-alarm simulation section model circuit model after the access is as shown in Figure 9.Wherein, each false-alarm bring out time switch make-and-break time value in the incident sub circuit model be in the table 3 turn-on time and post-set time value.Aspect access point, OUTPUT is the access point of F-1, F-2, F-3, four load disturbances of F-4, and NOISE3 is the access point of G-1, two interference incidents of G-2.
In the circuit model of the false-alarm simulation section model of setting up, accomplished the connection that false-alarm in the power circuit model is brought out the incident electronic circuit through the setting of access point, can carry out time-domain-simulation this moment, and simulation time length is the 60ms of regulation.
Step 5, false-alarm simulation interpretation of result;
Emulation obtains the simulation result waveform after finishing, and shown in figure 10, among the figure, FA is the BIT indicative curve; The circuit output voltage curve that V (OUTPUT) detects for BIT; V (U5A:+) is a BIT detection threshold higher limit; V (U6A:-) is a BIT detection threshold lower limit.
Waveform according to Figure 10 is analyzed, and obtains the result of false-alarm simulation, and is as shown in table 4.Obtain from table 4, under this false-alarm simulation section model, false-alarm has taken place 9 times in the BIT of this switching power supply circuit altogether.
Table 4 false-alarm simulation is table as a result
Claims (4)
1. the false-alarm simulation method of a built-in test of circuit is characterized in that, comprises following step:
Step 1: set up the false-alarm simulation section model;
1), sets the composition of operation profile model and false-alarm simulation section model;
(1) composition of operation profile model;
Operation profile model P
MFor:
P
M＝(D,HT,EL,t
M) (1)
In the formula: D---the disturbance set in the operation profile model, D={d
i| i=1～n}, d
iThe i time disturbance that receives for circuit is in service; N is the total degree of disturbance; The time of origin set of HT---disturbance, HT={ (ht
i, ct
i) | i=1～n}, ht
iIt is the start time of i disturbance; Ct
iIt is the duration of i disturbance; EL---disturbance is to the impact position set of circuit, EL={el
i| i=1～n}, el
iThe concrete impact position of table an i disturbance in circuit; t
M---the task duration that the operation profile model is corresponding;
(2) composition of false-alarm simulation section model;
False-alarm simulation section model P
FAFor:
P
FA＝(E,T,L,t
S) (2)
In the formula: E---false-alarm is brought out event sets, E={e
j| j=1～h}, e
jJ false-alarm in the expression set brought out incident; H representes that the false-alarm that comprises in the false-alarm simulation section model brings out incident quantity; (S), y representes that false-alarm brings out event type to e=for y, m; M representes that false-alarm brings out the analog form of incident; S representes that false-alarm brings out the event argument set of incident; T---time value set, T={ (rt
j, ot
j) | j=1～h}, rt
jRepresent that j false-alarm bring out value turn-on time of incident; Ot
jRepresent that j false-alarm bring out value post-set time of incident; L---access point set, L={l
j| j=1～h}, l
jRepresent that j the false-alarm incident of bringing out is linked into the position in the circuit; t
S---false-alarm simulation section model corresponding simulation duration;
2), according to operation profile modelling false-alarm simulation section model;
A, confirm that according to the disturbance in the operation profile model false-alarm in the false-alarm simulation section model brings out incident;
Each disturbance in the operation profile model is all set up the false-alarm of a correspondence and is brought out incident, confirms that false-alarm brings out the event type of incident, analog form and event argument;
B, confirm that according to the impact position of disturbance false-alarm brings out the access point of incident;
The impact position of disturbance is that disturbance is incorporated into the position in the circuit in the operation profile model, brings out incident in the correspondence position access false-alarm of circuit model, and then the false-alarm of having confirmed in circuit model is brought out the access point of incident;
C, confirm the time parameter in the false-alarm simulation section model according to the time parameter in the operation profile model;
According to the task duration in the operation profile model, disturbance start time, disturbance duration; Through Time Compression, determine the emulation duration in the corresponding false-alarm simulation section model, the turn-on time that false-alarm is brought out incident, the post-set time that false-alarm is brought out incident;
The task duration is carried out Time Compression, reduce the time loss of emulation;
D, describe the carrying out of false-alarm simulation section model is whole;
After the incident of bringing out, access point and the event argument of having confirmed the false-alarm simulation section model, need carry out integral body to the false-alarm simulation section model and describe; The whole description combines operation profile model and false-alarm simulation section model, describes content and is:
The operation profile model comprises task duration, disturbance, disturbance start time, disturbance duration, disturbing influence position;
The false-alarm simulation section model comprises emulation duration, Case Number, event type, event simulation mode, event argument, turn-on time, post-set time, access point;
Described Case Number is for to be provided with numbering to the false-alarm incident of bringing out;
Step 2, set up the sub circuit model that false-alarm is brought out incident;
Set up the sub circuit model that false-alarm is brought out incident according to event type, analog form and event argument, sub circuit model set inside ground connection externally has only the single face point;
Step 3, false-alarm are brought out the access of incident;
False-alarm is brought out the corresponding sub circuit model of incident be linked in the realistic model of circuit, the sub circuit model that h false-alarm brought out incident is connected with access point accordingly through the interface of correspondence;
The function of interface comprises: inserted automatically by the incident of control turn-on time; Automatically withdrawed from by the incident of control post-set time;
Step 4, carry out false-alarm simulation;
Operation emulation; The length of simulation time should be set to the emulation duration of appointment in the false-alarm simulation section model;
Step 5, false-alarm simulation interpretation of result;
After emulation finishes, obtain the timing waveform of BIT indication, carry out the analysis and the judgement of BIT false-alarm according to this waveform; If the false-alarm incident of bringing out causes the BIT indication fault, false-alarm has then taken place;
Comprehensive false-alarm simulation section model and analysis result are described false-alarm simulation result's integral body through form, and content comprises: false-alarm is brought out Case Number, event type, the false-alarm number of times that BIT indicates, incident is corresponding of incident correspondence, the total false-alarm number of times of false-alarm simulation section model in the false-alarm simulation section model.
2. the false-alarm simulation method of a kind of built-in test of circuit according to claim 1 is characterized in that, the disturbance type of the operation profile model described in the step 1 is the load action and disturbs that the type that corresponding false-alarm is brought out incident also is load disturbance and interference.
3. the false-alarm simulation method of a kind of built-in test of circuit according to claim 1 is characterized in that, the analog form that the false-alarm described in the step 1 is brought out incident is load disturbance and interference by the disturbance classification of type; Wherein, the analog form of load disturbance is: resistive load, inductive load, capacitive load, resistive, the perceptual perhaps SP combination load of capacitive; The analog form that disturbs is: sine wave signal, square-wave signal, triangular signal, voltage source, the combination of current source and signal.
4. the false-alarm simulation method of a kind of built-in test of circuit according to claim 1 is characterized in that, the false-alarm described in the step 1 is brought out the event argument of incident and confirmed according to the analog form of incident.
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| CN105446164B (en) * | 2015-11-27 | 2018-05-11 | 中国人民解放军63908部队 | A kind of semi-hardware type simulation test system |
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| US7203881B1 (en) * | 2004-06-29 | 2007-04-10 | Sun Microsystems, Inc. | System and method for simulating system operation |
| CN101477588A (en) * | 2009-01-13 | 2009-07-08 | 中国人民解放军国防科学技术大学 | Simulation method for equipment maintenance and guarantee based on Petri network model |
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| US7203881B1 (en) * | 2004-06-29 | 2007-04-10 | Sun Microsystems, Inc. | System and method for simulating system operation |
| CN101477588A (en) * | 2009-01-13 | 2009-07-08 | 中国人民解放军国防科学技术大学 | Simulation method for equipment maintenance and guarantee based on Petri network model |
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