CN101814578B - A semiconductor element and a fabricating method thereof - Google Patents
A semiconductor element and a fabricating method thereof Download PDFInfo
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- CN101814578B CN101814578B CN2010101291650A CN201010129165A CN101814578B CN 101814578 B CN101814578 B CN 101814578B CN 2010101291650 A CN2010101291650 A CN 2010101291650A CN 201010129165 A CN201010129165 A CN 201010129165A CN 101814578 B CN101814578 B CN 101814578B
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Abstract
This invention provides a phase-change memory and a fabricating method thereof. Said phase-change memory includes a phase-change material layer disposed by adding dewatering process. The hydrophoby of the phase-change material change the attaching force between the phase-change material and the mask layer located on the phase-change material. Said phase-change material can be treated by using plasma , for example containing nitrogen, ammonia, argon, helium, oxygen, hydrogen or the same.
Description
Technical field
The present invention is about a kind of semiconductor structure, particularly about a kind of semiconductor element that utilizes phase-change material.
Background technology
Phase change technique (phase change technology) is a desirable for follow-on storage arrangement.It uses chalcogenide (chalcogenide) semiconductor to come storing state and digital information.Chalcogenide is also referred to as phase-change material, has a crystalline substance (crystalline) attitude and an amorphous (amorphous) attitude.When crystalline state, phase-change material has low-resistivity; And when in amorphous state, it has high resistivity.Usually all greater than 1000: 1, also therefore phase change memory component unlikely makes a mistake when reading state the resistivity ratio of phase-change material when amorphous state and crystalline state.Crystalline state and the amorphous state of sulfur family compound semiconductor in certain temperature range all is stable, and can utilize electric pulse (electric pulse) transition back and forth between two states.
Phase change memory component forms through between two electrodes, phase-change material being set usually.Write operation is also referred to as programming operation (programming operation), is that electric pulse is applied on the storage arrangement; And read operation is in order to the resistance of measurement phase transition storage, and these two kinds of operations are all accomplished through two electrodes.In general, write operation utilizes a set pulse (set pulse) and a reset pulse (reset pulse).Set pulse is heated above the temperature of crystallization with phase-change material but is lower than the temperature of fusing, and the time of heating is longer than the required time of crystallization just can make crystallization take place.Reset pulse converts phase-change material to amorphous state, must phase-change material be heated above the temperature of fusing.Be enough to reduce or prevent crystallization as long as the time of heating is short to, then temperature just can be reduced to below the crystallization temperature soon.The heating of phase-change material is to have utilized the control one electric current electric conducting material of flowing through, and generally can be called heater (heater).This heater comprises an electric conducting material, because its resistance characteristic, its temperature will rise when applying a sufficiently high voltage difference.
Usually can a protective layer be arranged on the chalcogenide material,, avoid bearing because of changing the infringement that state produced of these chalcogenide material to protect these materials and material on every side.Yet protective layer, for example silicon nitride layer is not to be attached to so easily on the chalcogenide material, usually can delamination.
In order to reduce such delamination, there is trial between chalcogenide and protective layer, to establish a resilient coating or adhesion layer.The material that can be used as suitable resilient coating between chalcogenide and the protective layer is limited and usually can in photoetching process, throws into question.
Therefore, need a kind of protective layer, can be arranged on the phase-change material and can reduce or eliminate such delamination.
Summary of the invention
Utilization provides the various embodiments of the present invention of the semiconductor element that uses phase-change material, solves or has prevented these or other problem and reached technical advantage.
According to one embodiment of the invention, semiconductor element is provided.Semiconductor element comprises a phase change layer, and this phase change layer is electrically coupled to a top electrode and a bottom electrode.This phase change layer is formed by phase-change material, and has a surface, and this surface Treatment Design becomes a more hydrophobic surface.One mask (mask) layer is formed on this phase change layer, and wherein one of this mask layer and this phase change layer adjacency at the interface atom concentration is greater than the regional atom concentration in one outside this interface.Processing method can comprise, for example uses the Cement Composite Treated by Plasma of nitrogen (nitrogen), ammonia (ammonia), argon (argon), helium (helium), oxygen (oxygen), hydrogen (hydrogen) or its similar gas.
According to another embodiment of the present invention, a kind of manufacturing approach of semiconductor element is provided.On a substrate, a phase change layer is formed on the one layer or more dielectric layer.One surface of handling this phase change layer is to improve this surperficial adhesive force.Afterwards, on phase change layer, form a mask layer, wherein mask layer is adjacent to the phase change layer place and has the atom concentration of uprushing.Processing method can comprise, for example uses the Cement Composite Treated by Plasma of nitrogen, ammonia, argon, helium, oxygen, hydrogen or its similar gas.
According to yet another embodiment of the invention, the method that forms semiconductor element is provided.Provide one have an one layer or more dielectric layer substrate.One phase change layer is formed on this one layer or more dielectric layer, and a surface of this phase change layer is adjusted to has more hydrophobicity.The method on adjustment phase change layer surface can be, and for example uses the Cement Composite Treated by Plasma of nitrogen, ammonia, argon, helium, oxygen, hydrogen or its similar gas.
What one skilled in the art should appreciate that is that it can utilize present disclosure as the basis easily, designs or retouch other technology and structure, to realize identical purpose and/or to reach the advantage identical with specific embodiment or notion.Those skilled in the art it will be appreciated that also the reciprocity framework of this type does not break away from the spirit and the scope of present disclosure, as after attach scope required for protection.
Description of drawings
For letting above and other objects of the present invention, characteristic, advantage and the embodiment can be more obviously understandable, will combine accompanying drawing to do following description.The explanation of accompanying drawing is following:
Fig. 1-5 shows the method according to formation one phase transition storage of one embodiment of the invention.
Fig. 6 shows according to the treated and undressed energy spectrum analysis chart of the composition of the phase change layer of one embodiment of the invention.
It below is the description of reference numerals of main element.
100: 110: the first dielectric layers of wafer
120: top electrode 122: bottom electrode
210: phase change layer 212: processing layer
310: protective layer 510: etching stopping layer
Dielectric layer 514 in 512: the three: contact
Embodiment
The applicating adn implementing of preferred embodiment will be in following detailed disclosure.Yet, it is understandable that the present invention provides many innovation concepts of supplying usefulness, these innovation concepts can embody in various specific backgrounds.The specific embodiment of being discussed is only made and application ad hoc fashion of the present invention in order to illustrate, not in order to limit scope of the present invention.
Fig. 1 to 5 illustrates the interstage of a kind of novel phase-change element of manufacturing of one embodiment of the invention.Some embodiments of the present invention can specificly be used to make phase transition storage (phase change memory; PCM) device.Yet other embodiments of the invention also can be used for the device of other type.In the embodiment that different viewpoints of the present invention and following conduct are given an example, specify similar element with the component symbol or the label that repeat.
Please,, show that the part of wafer 100 has first dielectric layer 110 and second dielectric layer 112 according to one embodiment of the invention earlier with reference to Fig. 1.First dielectric layer 110 and second dielectric layer 112 can be, for example one layer or more interlayer dielectric layer (inter-layer dielectric layer; The ILD layer) and/or metal intermetallic dielectric layer (inter-metal dielectric layer; The IMD layer).Usually interlayer dielectric layer and metal intermetallic dielectric layer and relevant metal level thereof are used for interconnecting each other with circuit unit (electrical circuitry) (not shown) that is formed at down on the laminar substrate (not shown), and external electric connection is provided.
First dielectric layer 110 and second dielectric layer 112 can be formed by for example low-K dielectric material, for example phosphorosilicate glass (phosphosilicate glass; PSG), boron-phosphorosilicate glass (borophosphosilicateglass; BPSG), fluorine silex glass (fluorinated silicate glass; PSG), the hydrocarbon of silicon (SiOxCy) (wherein x and y represent the ratio of each number), spin-on glasses (spin-on-glass; SOG), spin-coating polymer (spin-on-polymer; SOP), silicon carbon material, its compound, its composition, its mixture or its homologue; Any suitable known method capable of using, for example spin-coating method (spinning), chemical vapour deposition technique (CVD) and plasma enhanced chemical vapor deposition method (PECVD).It should be noted that each layer in first dielectric layer 110 and second dielectric layer 112 can comprise multilayer dielectric layer.
Should also be noted that also and can one layer or more etch stop layer (for example etch stop layer 114) be arranged between the dielectric layer of adjacency, for example between first dielectric layer 110 and second dielectric layer 112 of Fig. 1.Usually etch stop layer provides a kind of mechanism, can when forming via hole (vias), contact (contacts) or forming the electrode here, stop etched technology.Etch stop layer can be formed by the dielectric material that adjoining course is had different etching selectivities.In one embodiment; Etch stop layer can be by silicon nitride (SiN), fire sand (SiCN), silicon oxide carbide (SiCO), carbonitride (CN), its bond or its homologue, with chemical vapour deposition (CVD) or plasma enhanced chemical vapor deposition deposition techniques and form.
Circuit can comprise mutual connection to accomplish different N type metal oxide semiconductors (the N-type metal-oxide semiconductor of one or more function; NMOS) with and/or P-type mos (PMOS) device, for example transistor, electric capacity, resistance, diode, optical diode, fuse or its homologue.These functions can comprise memory construction, Processing Structure, transducer, amplifier (amplifiers), distribution system (power distribution), imput output circuit or its homologue.Those skilled in the art should be apprehensible be, the aforementioned example that is used to provide explanation the object of the invention is only just further explained application of the present invention and is not in order to restriction the present invention.Other circuit that is fit to also can be applicable to the present invention.
For example, embodiment as shown in Figure 1, bottom electrode 122 contacts 124 capable of using are electrically coupled to a transistorized source/drain regions, and this transistor is formed on the substrate that is positioned under it.Like this, transistor can in order to the control phase-change material (after step in form) set and reset with and/or read the state of phase-change material.
The material that forms top electrode 120 and bottom electrode 122 can be any suitable electric conducting material; For example a high conduction, low-resistance metal, metal element, transition metal or its homologue comprise and are selected from aluminium, aluminum bronze, copper, titanium, titanium nitride, tungsten and mutually metallike metal or metal alloy thereof.Moreover top electrode 120 can comprise a resistance barrier/adhesion layer with bottom electrode 122, to avoid spreading and providing preferable adhesive force between top electrode 120/ bottom electrode 122 and the dielectric layer on every side.
For example can utilizing, physical vaporous deposition (PVD), atomic layer deposition method (ALD), spin-coating sedimentation (spin-on deposition) or other method that is fit to form top electrode 120 and bottom electrode 122.Cmp (CMP) technology can be used to remove the surface of excessive electric conducting material and planarization second dielectric layer 112 and top electrode 120 and bottom electrode 122.
Fig. 2 illustrates the formation according to a phase change layer 210 of one embodiment of the invention.In one embodiment, phase change layer 210 comprises chalcogenide, for example Ge-Sb-Te sulfide alloy (Ge
xSb
yTe
z), wherein x, y and z represent the ratio of each number.For example, phase change layer can be by germanium antimony tellurium alloy (Ge
1Sb
4Te
7), germanium antimony tellurium alloy (Ge
2Sb
2Te
5), germanium antimony tellurium alloy (Ge
1Sb
2Te
4) or its homologue form.Also can use other material, for example add the eutectic antimony tellurium alloy (Sb of metal
69Te
31), wherein metal is silver (Ag), indium (In), germanium (Ge), tin (Sn) or its phase metallike.In one embodiment, phase change layer 210 has a thickness between about 1 nanometer (nm) and about 100 nanometers, for example between about 5 nanometers and about 30 nanometers.The amorphous state resistivity of phase change layer 210 and the ratio of crystalline resistance rate can be up to 5 powers, and is a little low even this grade has.In an example embodiment, between about 1 ohmcm (Ω cm) and about 100 ohmcms, same material is between about 0.00001 ohmcm and about 0.005 ohmcm in the resistivity of crystalline state to phase change layer 210 in amorphous resistivity.In other embodiments, phase-change material can use Ge
xSb
yTe
zM is used as representative, and wherein x, y and z represent the ratio of each number, and M is the material that is selected from one of silver, tin, indium and bond thereof.
Fig. 2 also illustrates according to an embodiment of the invention and in phase change layer 210 at least partly, forms processing layer 212.What found is, the material that is used for making phase change layer 210 exists water-wet behavior, and because hydrophily possibly be difficult to form the cover layer (overlying layer) that enough adhesive force is arranged with phase change layer 210.In order to increase the adhesive force of 210 of phase change layers, at least one surface of handling phase change layer 210 is adjusted to the hydrophily with material and has more hydrophobic tendency.Therefore hydrophobic tendency has increased the adhesive force between phase change layer 210 and cover layer, reduces or has eliminated delamination.
In one embodiment, processing comprises a nitrogen plasma treatment (N
2Plasma treatment).For example handle can comprise use inert gas helium, neon, argon, krypton, xenon and radon with and combine the carrier gas (carrier gas) and a process gas nitrogen of gas.Process conditions can comprise uses one to be lower than the temperature that the temperature of gas is removed in the phase-change material heating, for example between pressure, one power and one the process time between about 10 second and about 180 second between between about 100 watt and about 1000 watt between of the temperature between about 100 and 300 degree Celsius approximately, between about 1 millitorr (mtorr) and about 1 holder (torr).Also can use other process gas, for example ammonia, argon, helium, oxygen, hydrogen or its similar gas.
Fig. 3 illustrates a mask or the formation of protective layer 310 on phase change layer 210 and the processing layer 212 that is formed at according to one embodiment of the invention.Protective layer 310 provides the protection to cladding material, makes its influence of avoiding the heating of phase change layer, also after step in a mask layer is provided.In one embodiment, protective layer 310 is layered masks, and it comprises mononitride layer and monoxide layer.Nitride layer can be the silicon nitride layer (Si that is formed on the oxide skin(coating)
3N
4).CVD technology capable of using forms silicon nitride layer (Si
3N
4), and with silane and ammonia as process gas, and the depositing temperature scope from 100 to 900 degree Celsius.Oxide skin(coating) can be the silicon dioxide layer that forms with thermal oxidation or chemical vapour deposition technique, and with tetraethyl orthosilicate salt (tetra-ethyl-ortho-silicate; TEOS) and oxygen as predecessor.Another nitride layer, for example silicon oxynitride layer can be formed on the oxide skin(coating).Also can use the mask or the protective layer of other type, comprise the individual layer mask or the layered mask that use identical or other material.
As previously mentioned; Since processing layer 212 compared to the material that is untreated of phase change layer 210 be have more hydrophobic; So have more adhesive force at phase change layer 210 and 310 of protective layers, therefore can reduce or eliminate the delamination phenomenon between phase change layer 210 and the protective layer 310.Had been found that a kind of for example foregoing technology has caused in protective layer 310, having the high concentration silicon atom along interface zone as shown in Figure 6, Fig. 6 is energy spectrum analysis (EDX) figure of one embodiment of the invention.Thinkable is that the processing of phase change layer has caused the attraction bigger to the silicon atom of protective layer 310; Therefore cause atom concentration in interface zone to be higher than in the protective layer 310, make 210 of protective layer 310 and phase change layers that preferable adhesive force arranged away from the atom concentration of interface zone.
Fig. 4 illustrates the patterning (patterning) of phase change layer 210, processing layer 212 and protective layer 310.Usually can use photoetching technique to come patterning phase change layer 210, processing layer 212 and protective layer 310, make phase change layer 210 be formed on the top electrode 12 and bottom electrode 122 at least partly.So, can be through between top electrode 120 and bottom electrode 122, the state that phase change layer 210 was controlled and read to a voltage difference being set.The electric current and the resistance characteristic that flow through the material of phase change layer 210 cause the material of phase change layer 210 to be heated, and therefore make the material of phase change layer 210 can be made as crystalline state or amorphous state.Can be worse than between top electrode 120 and the bottom electrode 122 through a voltage is set, and measure the state that resistance value between them is confirmed phase change layer 210.
Then, as shown in Figure 5, according to one embodiment of the invention, can form etching stopping layer/sealant 510 and the 3rd dielectric layer 512.Etching stopping layer 510 can be for example forms by silicon nitride or to other material that material around has different etch-rates.In one embodiment, protective layer 310 comprises the upper strata of silicon oxynitride, preferably before the etching stopping layer 510 that forms silicon nitride, removes silicon oxynitride layer.Can use with first dielectric layer 110 and second dielectric layer 112 as previously mentioned similarly technology form the 3rd dielectric layer 512 with material, although preferably use oxygen material in addition to avoid the oxidation of phase change layer 210.Fig. 5 equally also illustrates contact 514 and is connected to top electrode 120.Contact 514 provide top electrode 120 and other circuit with and/or an external connector between be electrically connected.Can use mosaic technology with an electric conducting material, for example metal or comprise one of aluminium, aluminum bronze, copper, titanium, titanium nitride, tungsten and phase metallike thereof or many persons' metal alloy forms contact 514.
Though the present invention discloses as above with execution mode; Yet it is not in order to limit the present invention; Any those skilled in the art; Do not breaking away from the spirit and scope of the present invention, can do various changes and retouching, so protection scope of the present invention should be as the criterion with the scope that accompanying scope required for protection was defined.
In addition, the application's scope is in no way limited in the specific embodiment of the described technology of specification, machinery, manufacturing, material composition, means, method and step.Any those having an ordinary knowledge in this technical field; Can from disclosure of the present invention, recognize easily; Existing or developed in the future can carry out the essence identical functions with above-mentioned corresponding embodiment or reach the identical result's of essence technology, machinery, manufacturing, material composition, means, method or step, can be applied according to the present invention.Therefore, appended scope required for protection is in order to be encompassed in this type technology, machinery, manufacturing, material composition, means, method or step in its scope.
Claims (9)
1. semiconductor element, this semiconductor element comprises:
One phase change layer is electrically coupled to a top electrode and a bottom electrode, and this phase change layer comprises a phase-change material, and wherein a surface of this phase change layer comprises a processing section; And
One mask layer; Be positioned at this phase change layer top; One at the interface atom concentration of this mask layer and this phase change layer adjacency is greater than the atom concentration in one outside this interface zone, this of this phase change layer the adhesive force between processing section and this mask layer greater than untreated phase-change material.
2. semiconductor element as claimed in claim 1, wherein this mask layer comprises silicon nitride.
3. semiconductor element as claimed in claim 1, wherein this phase change layer at least partly is positioned at this top electrode and this bottom electrode top.
4. the manufacturing approach of a semiconductor element, this method comprises:
One substrate is provided, and this substrate has the one layer or more dielectric layer and is formed on this substrate;
One phase change layer is formed on this one layer or more dielectric layer;
Handle at least one surface of this phase change layer, the step of handling at least one surface of this phase change layer increases the adhesive force of this phase change layer, and the step of wherein handling at least one surface of this phase change layer is a Cement Composite Treated by Plasma; And
One mask layer is formed on this phase change layer, and this mask layer is adjacent to this phase change layer place and has the atom concentration of uprushing.
5. method as claimed in claim 4 also comprises a top electrode and a bottom electrode are formed in this one or more dielectric layer, and wherein this phase change layer is positioned on this top electrode and this bottom electrode at least partly.
6. method as claimed in claim 4, wherein this mask layer comprises silicon nitride.
7. the manufacturing approach of a semiconductor element, this method comprises:
One substrate is provided, and this substrate has the one layer or more dielectric layer and is formed on this substrate;
One phase change layer is formed on this one layer or more dielectric layer;
Handle a surface of this phase change layer; And
After the processing mask layer is formed on this phase change layer, this surperficial step of wherein handling this phase change layer increases the adhesive force of this mask layer to this phase change layer, and this surperficial step of handling this phase change layer is a Cement Composite Treated by Plasma.
8. method as claimed in claim 7, wherein this mask layer comprises a nitrogenous layer.
9. method as claimed in claim 7 also comprises a top electrode and a bottom electrode are formed in this one layer or more dielectric layer, and wherein this phase change layer at least partly is positioned on this top electrode and this bottom electrode.
Applications Claiming Priority (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US15412709P | 2009-02-20 | 2009-02-20 | |
| US61/154,127 | 2009-02-20 | ||
| US12/617,294 US20100213431A1 (en) | 2009-02-20 | 2009-11-12 | Treated Chalcogenide Layer for Semiconductor Devices |
| US12/617,294 | 2009-11-12 |
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| CN101814578A CN101814578A (en) | 2010-08-25 |
| CN101814578B true CN101814578B (en) | 2012-03-21 |
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Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN103624032B (en) * | 2012-08-23 | 2015-11-25 | 中芯国际集成电路制造(上海)有限公司 | A kind of monolithic cleaning method of wafer |
| CN105098066B (en) * | 2014-05-15 | 2017-05-10 | 中芯国际集成电路制造(上海)有限公司 | Phase change memory and manufacturing method thereof and electronic device |
| TWI569416B (en) * | 2015-11-26 | 2017-02-01 | 華邦電子股份有限公司 | Resistive random access memory and method of fabricating the same |
| US10693062B2 (en) | 2015-12-08 | 2020-06-23 | Crossbar, Inc. | Regulating interface layer formation for two-terminal memory |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1866533A (en) * | 2005-05-19 | 2006-11-22 | 株式会社瑞萨科技 | Semiconductor storage device and manufacturing method thereof |
| CN101335329A (en) * | 2008-08-05 | 2008-12-31 | 中国科学院上海微系统与信息技术研究所 | Construction for enhancing reliability of phase-change memory storage unit and manufacturing method thereof |
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2010
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Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1866533A (en) * | 2005-05-19 | 2006-11-22 | 株式会社瑞萨科技 | Semiconductor storage device and manufacturing method thereof |
| CN101335329A (en) * | 2008-08-05 | 2008-12-31 | 中国科学院上海微系统与信息技术研究所 | Construction for enhancing reliability of phase-change memory storage unit and manufacturing method thereof |
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