CN101807916A - Phase-locked loop system and method - Google Patents
Phase-locked loop system and method Download PDFInfo
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- CN101807916A CN101807916A CN200910007051A CN200910007051A CN101807916A CN 101807916 A CN101807916 A CN 101807916A CN 200910007051 A CN200910007051 A CN 200910007051A CN 200910007051 A CN200910007051 A CN 200910007051A CN 101807916 A CN101807916 A CN 101807916A
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Abstract
The invention provides a phase-locked loop system and a phase-locked loop method. A phase-locked loop comprises a phase detector which is configured to receive the input of a reference signal route and the input of a feedback signal route and generate a phase detector output according to the input. The phase-locked loop also comprises an oscillator which is operationally connected with the phase detector and configured to respond to the phase detector output to generate an oscillation output according to the phase detector output, wherein the oscillation output is applied to the feedback signal route. The reference signal route comprises a frequency mixer and a switching mechanism, wherein the frequency mixer is configured to mix frequencies of the reference signal and the output from a direct digital synthesizer; and the switching mechanism is configured to be selectively connected with one of a plurality of different filters between the frequency mixer and the phase detector.
Description
Technical field
The present invention relates to phase-locked loop systems and method.
Background technology
There is the multiple device that is used to test, measure and analyze numeral and analog signal.Phase-locked loop (PLL) is used in these devices usually and carries out various functions.The performance requirement of PLL depends on specific setting usually, although multiple application has benefited from having low phase noise and the high PLL that regulates resolution on wide frequency ranges.Design challenge generally stems from improves the fact that a performance parameter may cause the degradation of another parameter.For example, some scheme of optimizing phase noise can be introduced stray power in output signal.
In addition, performance requirement usually need with the consideration balance of cost, size, encapsulation and power consumption.For example, specific design may provide optimum mix of properties, but consumes too many electric power and can not implement in battery powered mancarried device.
Summary of the invention
One aspect of the present invention provides a kind of low phase noise and test of wide adjusting PLL handheld electronic and measurement mechanism, comprising: shell; Battery connector places shell and is configured to hold battery; Input is configured to receive interested signal; Phase-locked loop (PLL) subsystem, place shell and be configured to battery-powered, this PLL subsystem comprises reference signal route, this reference signal route operatively links to each other with input and is configured to receive the reference signal that obtains from interested signal, wherein the PLL subsystem also comprises: phase detectors, operatively link to each other with feedback signal path, and be configured to produce phase detectors output according to the signal that is applied to phase detectors from reference signal route and feedback signal path with reference signal route; And oscillator, operatively link to each other with phase detectors, and be configured in response to and generating vibration output according to phase detectors output, and wherein vibration output is applied to feedback signal path, wherein, reference signal route comprises: frequency mixer, be configured to reference signal with from the output mixing of Direct Digital synthesizer; And switching mechanism, be configured between frequency mixer and phase detectors selectively series connection and settle in a plurality of different filters one.
In said apparatus, the Direct Digital synthesizer can be configured to make its frequency of output to be not more than about 1/8 of reference signal frequency.
In said apparatus, one in described a plurality of different filter can be configured to band pass filter, the frequency that its centre frequency equals reference signal adds the frequency of the output of Direct Digital synthesizer, and another in wherein said a plurality of different filter can be configured to band pass filter, and the frequency that its centre frequency equals reference signal deducts the frequency of the output of Direct Digital synthesizer.
In said apparatus, switching mechanism can be configured to selectively connect between frequency mixer and phase detectors and settle first filter or second filter, and wherein first filter and second filter are the band pass filters with different center frequency.
In said apparatus, first filter and second filter can be surface acoustic wave (SAW) filters.
In said apparatus, switching mechanism can be configured to come at arrangement first filter or second filter of selectively connect between frequency mixer and the phase detectors according to the operating parameter of PLL subsystem.
In said apparatus, operating parameter can be the frequency of reference signal.
In said apparatus, when switching mechanism can be configured to make frequency when reference signal in the scope of bottom and when the frequency of reference signal is in upper extent, between frequency mixer and phase detectors, connect and settle first filter, and make when in the intermediate range of frequency between bottom scope and upper extent of reference signal arrangement second filter of between frequency mixer and phase detectors, connecting.
Another aspect of the present invention provides a kind of phase-locked loop, comprising: phase detectors are configured to receive from the input of reference signal route and feedback signal path and according to these input generation phase detectors output; And oscillator, operatively link to each other with phase detectors and be configured in response to and generating vibration output according to phase detectors output, and wherein vibration output is applied to feedback signal path, wherein reference signal route comprises: frequency mixer, be configured to reference signal with from the output mixing of Direct Digital synthesizer; And switching mechanism, be configured between frequency mixer and phase detectors selectively series connection and settle in a plurality of different filters one.
In above-mentioned phase-locked loop, the Direct Digital synthesizer can be configured to make that its output frequency is not more than about 1/8 of reference signal frequency.
In above-mentioned phase-locked loop, one in described a plurality of different filter can be configured to band pass filter, the frequency that its centre frequency equals reference signal adds the frequency of the output of Direct Digital synthesizer, and another in wherein said a plurality of different filter can be configured to band pass filter, and the frequency that its centre frequency equals reference signal deducts the frequency of the output of Direct Digital synthesizer.
In above-mentioned phase-locked loop, switching mechanism can be configured to selectively connect between frequency mixer and phase detectors and settle first filter or second filter, and wherein first filter and second filter are the band pass filters with different center frequency.
In above-mentioned phase-locked loop, first filter and second filter can be surface acoustic wave (SAW) filters.
In above-mentioned phase-locked loop, switching mechanism can be configured to come at arrangement first filter or second filter of selectively connect between frequency mixer and the phase detectors according to the operating parameter of phase-locked loop.
In above-mentioned phase-locked loop, operating parameter can be the frequency of reference signal.
In above-mentioned phase-locked loop, when switching mechanism can be configured to make frequency when reference signal in the scope of bottom and when the frequency of reference signal is in upper extent, between frequency mixer and phase detectors, connect and settle first filter, and make when in the intermediate range of frequency between bottom scope and upper extent of reference signal arrangement second filter of between frequency mixer and phase detectors, connecting.
Another aspect of the present invention provides a kind of phase-locked loop method, comprising: the vibration output along feedback signal path self-oscillation in the future device is fed to phase detectors; In reference signal route, the adjusting reference signal generates and comprises a plurality of signals through overregulating that extract the centre of part; Selection can be extracted in the part; And come to generate phase detectors output from phase detectors in response to vibration output and described of can extract in the part.
In said method, regulate the signal through overregulate of reference signal in the middle of generating and to comprise reference signal and output mixing from the Direct Digital synthesizer.
In said method, selection can be extracted in the part one and can be comprised bandpass filtering is carried out in the output from the mixing of the output of reference signal and Direct Digital synthesizer.
In said method, selection can be extracted in the part one and can be comprised and will be outputted to first filter or second filter from the mixing of the output of reference signal and Direct Digital synthesizer.
Description of drawings
Fig. 1 schematically shows the electronic installation that is used to test, measure and/or analyze the signal of telecommunication, comprises the phase locked loop subsystems that places in this device.
Fig. 2 schematically shows other examples of the phase locked loop subsystems that can adopt in the device of Fig. 1 to Fig. 4.
Fig. 5 shows the example data that can be used for the control strategy that will use is assessed and draws in the reference signal route of phase locked loop subsystems example shown in Figure 4.
Fig. 6 shows exemplary phase-locked ring method.
Embodiment
Fig. 1 shows the electronic installation 10 that can be used to test, measure and/or analyze signal of telecommunication Fin.Described exemplary device is of portable form (for example hand-held), comprises the PLL subsystem 14 that places in the shell 16 and power by battery 18.As described here, PLL subsystem 14 can be optimized to help using in mancarried device, shown in this example, but is understandable that described PLL subsystem can use in other devices.
In many setting, expectation be that oscillator 36 is embodied as the wide voltage controlled oscillator of adjustable range (VCO), and PLL has low phase noise.In order to reduce the sideband phase noise, can select element to widen loop bandwidth.And, in many setting, can adopt commercial synthesizer to obtain low-power consumption, this expects in hand-held or other battery powered mancarried devices.Yet such combination may cause synthesizer to generate undesired high phase noise.
Correspondingly, offer the comparison frequency of phase detectors 34, can obtain reducing of synthesizer noise contribution by increase.In integer frequency ratio PLL, can increase comparison frequency by the adjusting stride that increases PLL.This being reduced on resolution will be unacceptable in many application, and therefore may be desirably in employing Direct Digital synthetic (DDS) in the reference signal route.DDS can provide the very fine resolution frequency with utmost point low phase noise to regulate.
Fig. 2 provides another example embodiment of PLL subsystem 14, has wherein adopted DDS in reference signal route 30.Specifically, described example reference signal path 30 comprises DDS module 40, low pass filter 42 and the divider 44 that is fed to phase detectors 34.Phase detectors output comes driving oscillator 36 (for example, VCO), to generate vibration output Fout by loop filter 46.Feedback signal path 32 can also comprise divider 48, and it can be selected in combination with divider 44, with the frequency multiplication that expectation is provided and/or other aspects of regulating the PLL performance.
Fig. 3 provides like the example class with Fig. 2 that another enables the example of DDS, and just pectination signal generator 60 is attached to provides in the feedback signal path 32 synchronously and output stability.
The example of Fig. 2 and Fig. 3 provides wide tuning range and high-resolution thus, has reduced phase noise simultaneously.Yet these structures may easier to generate undesired frequency in the PLL output spectrum spuious than other structures.Especially, the use of the DDS described in Fig. 2 and Fig. 3 may generate n*Fref+/-m*Fdds is spuious.The DDS output frequency is high more with respect to the reference frequency of Fref, and spurious level is just high more.
In order to use lower DDS output frequency and to keep the comparison frequency of phase detectors to be height, an embodiment can use DDS incoming frequency up-conversion DDS output frequency, yet, in some embodiments, may use different signal sources.For example, in one approach, mark synthesizer or the more complicated alternative DDS of system, yet, for obtaining similarly low spurious level, may still need up-conversion.
Fig. 4 shows another example embodiment of PLL subsystem 14.As will be descr, the example of this accompanying drawing can obtain the many of other examples or all advantages, also eliminates simultaneously or has reduced undesired spuious in the output spectrum.Especially, the example of Fig. 4 consider in reference signal route 30, to handle and/or Signal Regulation to obtain a plurality of extractible (for example, can select) part by filtering.According to operating condition, the clutter noise in part and/or other performance conditions will or more not expected relatively than the relatively more expectation of experiencing with other parts.Preferred part subsequently can selected (for example, through filtering) to pass through to phase detectors 34.
Specifically, as shown in Figure 4, PLL reference signal Fref can be separated at 70 places in reference signal route 30, makes Fref drive DDS module 72 and frequency mixer 74.After low pass filter 76, DDS exports in frequency mixer 74 places and Fref mixing.Place the switching mechanism 80 between frequency mixer 74 and the phase detectors 34, the filter that the arrangement that is configured to selectively to connect is wanted between the benchmark input of frequency mixer output and phase detectors 34.
Aspect other, described example can be similar to reference to Fig. 2 and the described example of Fig. 3 various.Except phase detectors 34, the main loop further of described embodiment comprises loop filter 46 and VCO 36, and its output (Fout) is fed back to phase detectors.In addition, as in foregoing example, divider 44 and 48 may be provided in the signal path of phase detectors so that frequency multiplication and adjusting function suitably otherwise to be provided.
A kind of method that reduces spurious level in described example comprises the output frequency that DDS module 72 is set with respect to the frequency of Fref.Especially, determined that 1/8 the scope that output frequency with the DDS module is set to high frequency to Fref can reduce spurious level effectively, but other embodiment are so limited.Frequency mixer 74 is used to increase the comparison frequency at 34 places subsequently.In this example, be set to the about 1/8 of Fref frequency, less than 8 rank, also provide wide tuning range simultaneously the minimum exponent number of mixing that keeps DDS and Fref by output frequency with the DDS module.Because the mixing at 74 places obtains two frequency bands in the signal through overregulating of centre: (1) Fref+Fdds and (2) Fref-Fdds.In described example, have only a frequency band to be used as the clock of phase detectors 34, and switching mechanism 80 is used to select suitable frequency band.
Select suitable frequency band to have multiple possibility.In this example, adopt filter 82 and 84.In some embodiments, filter 82 and 84 can be in the various band pass filters any one.In a special embodiment, filter 82 and 84 can be surface acoustic wave (SAW) filter.Other embodiment are not the filter that is so limited and can uses other to be fit to.In the filter 82 and 84 one or another operation by switch 86 and 88 are activated, and settle selected filter thereby connect between frequency mixer and phase detectors.In some embodiment of the integer synthesizer of commodity in useization, can limit the highest power detector frequency.For the purpose of illustrating, if pre-frequency dividing ratio is P, the frequency dividing ratio on the feedback signal path is N=B*P+A so, B＞A.In this way, Fref+Fdds path and Fref-Fdds path described here can be used to optimize PLL for the optimum phase noise.
Especially, regulate frequency band by using two, described topological structure is regulated whole DDS and is played phase noise and the spuious characteristic of leverage so that optimization to be provided.This designs simplification HFS and allow to carry out filtering in low relatively frequency.And example embodiment can realize under the situation such as YlG VCO and GaAs frequency divider and phase detectors not using high power consumption element.In fact, the inventor has designed whole pll system as described herein, and its power consumption is less than 1.5W.This ability that realizes design with the low-power consumption element makes it be suitable for portable premium quality product.
Can determine the controlled condition of switch 86 and 88 in every way.According to a kind of method, a plurality of reference signals of striding operational frequency range can be applied to PLL subsystem 14 in succession with experience ground observation spurious response, other aspects of phase noise and PLL performance.Can only utilize filter 82 execution to stride first scanning of frequency range.Carry out second scanning for another filter 84 subsequently.Resulting data are compared comparison or the zonal comparison of carrying out pointwise subsequently, are identified for the filter that is fit under the different condition.
For example Fig. 5 shows when using filter 82 and 84, the contrast of the exemplary performance of the PLL subsystem of Fig. 4.The right side longitudinal axis is represented the minimum exponent number of mixing between Fref and the Fdds, and the left side longitudinal axis is represented phase noise.Substantially, along with the reduction of mixing exponent number, spuious characteristic increases.When phase noise increased, an embodiment can switch to another frequency band and keep phase noise low relatively, keeps the mixing exponent number greater than 8 simultaneously.In the example shown in Figure 5, frequency band switches to filter 84 from filter 82 near near the horizontal dotted line 5700 on the X-axis.
Other aspects of PLL performance can be assessed to determine the suitable control of switch 86 and 88 similarly.For example, phase noise characteristic can, be depicted as the frequency or the function of another parameter of each in filter 82 and 84.Spurious level and phase noise only are two examples, can count a lot of aspect other of PLL performance in the control of switch 86 and 88.
According to top described, should be understood that except described structure, this specification also comprises the method for configuration and/or operation phase-locked loop.Fig. 6 shows the illustrative methods 600 that is used to operate phase-locked loop.602, this method comprises along feedback signal path the vibration of oscillator output is fed to phase detectors.604, this method is included in regulates reference signal in the reference signal route and produces and comprise a plurality of signals through overregulating that extract the centre of part.Select to extract in the part one in step 606.608, this method comprises in response to vibration output and the selected part of extracting to be exported from phase detectors generation phase detectors.
According to top described, should be understood that, can to produce a plurality of frequency band parts in the signal, carry out the adjusting that 604 places mention by mixing is carried out in the output of PLL reference signal and DDS module.In this case, can act on frequency mixer output, carry out the selection at 606 places by selectively controlling enabling of different filters.
It is to be further understood that structure described here and/or method are exemplary in itself, and these specific embodiments or example should not be understood that to have certain restriction, this is because might carry out various modification.Particular routine described here or method can be represented one or more any amount of processing policies.As referred, can according to shown in order, the various operations shown in carrying out according to other order, side by side or under some abridged situation.Similarly, the order of any above-mentioned processing is also nonessential for feature that realizes said embodiment and/or result, but provides for the ease of explaining and describing.Theme of the present disclosure comprise various processing, system and structure all novelties with non-obvious combination and sub-portfolio, and other features, function, operation and/or characteristic disclosed herein, and any and all equivalents in them.
Claims (20)
1. test of a low phase noise and wide adjusting PLL handheld electronic and measurement mechanism comprise
Shell;
Battery connector places shell and is configured to hold battery;
Input is configured to receive interested signal;
Phase-locked loop (PLL) subsystem, place shell and be configured to battery-powered, this PLL subsystem comprises reference signal route, and this reference signal route operatively links to each other with input and is configured to receive the reference signal that obtains from interested signal, and wherein the PLL subsystem also comprises:
Phase detectors operatively link to each other with feedback signal path with reference signal route, and are configured to produce phase detectors output according to the signal that is applied to phase detectors from reference signal route and feedback signal path; And
Oscillator operatively links to each other with phase detectors, and be configured in response to and generating vibration output according to phase detectors output, and wherein vibration output is applied to feedback signal path,
Wherein, reference signal route comprises:
Frequency mixer, be configured to reference signal with from the output mixing of Direct Digital synthesizer; And
Switching mechanism is configured between frequency mixer and phase detectors selectively series connection and settles in a plurality of different filters one.
2. device as claimed in claim 1, wherein the Direct Digital synthesizer is configured to make its frequency of output to be not more than about 1/8 of reference signal frequency.
3. device as claimed in claim 2, one in wherein said a plurality of different filter is configured to band pass filter, the frequency that its centre frequency equals reference signal adds the frequency of the output of Direct Digital synthesizer, and another in wherein said a plurality of different filter is configured to band pass filter, and the frequency that its centre frequency equals reference signal deducts the frequency of the output of Direct Digital synthesizer.
4. device as claimed in claim 2, wherein switching mechanism is configured to selectively connect between frequency mixer and phase detectors and settles first filter or second filter, and wherein first filter and second filter are the band pass filters with different center frequency.
5. device as claimed in claim 4, wherein first filter and second filter are surface acoustic wave (SAW) filters.
6. device as claimed in claim 4, wherein switching mechanism is configured to come at arrangement first filter or second filter of selectively connect between frequency mixer and the phase detectors according to the operating parameter of PLL subsystem.
7. device as claimed in claim 6, wherein operating parameter is the frequency of reference signal.
8. device as claimed in claim 7, when wherein switching mechanism is configured to make frequency when reference signal in the scope of bottom and when the frequency of reference signal is in upper extent, between frequency mixer and phase detectors, connect and settle first filter, and make when in the intermediate range of frequency between bottom scope and upper extent of reference signal arrangement second filter of between frequency mixer and phase detectors, connecting.
9. a phase-locked loop comprises
Phase detectors are configured to receive from the input of reference signal route and feedback signal path and according to these input generation phase detectors output; And
Oscillator, operatively link to each other with phase detectors and be configured in response to and generating vibration output according to phase detectors output, and wherein vibration output is applied to feedback signal path,
Wherein reference signal route comprises:
Frequency mixer, be configured to reference signal with from the output mixing of Direct Digital synthesizer; And
Switching mechanism is configured between frequency mixer and phase detectors selectively series connection and settles in a plurality of different filters one.
10. phase-locked loop as claimed in claim 9, wherein the Direct Digital synthesizer is configured to make that its output frequency is not more than about 1/8 of reference signal frequency.
11. phase-locked loop as claimed in claim 10, one in wherein said a plurality of different filter is configured to band pass filter, the frequency that its centre frequency equals reference signal adds the frequency of the output of Direct Digital synthesizer, and another in wherein said a plurality of different filter is configured to band pass filter, and the frequency that its centre frequency equals reference signal deducts the frequency of the output of Direct Digital synthesizer.
12. phase-locked loop as claimed in claim 9, wherein switching mechanism is configured to selectively connect between frequency mixer and phase detectors and settles first filter or second filter, and wherein first filter and second filter are the band pass filters with different center frequency.
13. phase-locked loop as claimed in claim 12, wherein first filter and second filter are surface acoustic wave (SAW) filters.
14. phase-locked loop as claimed in claim 12, wherein switching mechanism is configured to come at arrangement first filter or second filter of selectively connect between frequency mixer and the phase detectors according to the operating parameter of phase-locked loop.
15. phase-locked loop as claimed in claim 14, wherein operating parameter is the frequency of reference signal.
16. phase-locked loop as claimed in claim 15, when wherein switching mechanism is configured to make frequency when reference signal in the scope of bottom and when the frequency of reference signal is in upper extent, between frequency mixer and phase detectors, connect and settle first filter, and make when in the intermediate range of frequency between bottom scope and upper extent of reference signal arrangement second filter of between frequency mixer and phase detectors, connecting.
17. a phase-locked loop method comprises:
Vibration output along feedback signal path self-oscillation in the future device is fed to phase detectors;
In reference signal route, the adjusting reference signal generates and comprises a plurality of signals through overregulating that extract the centre of part;
Selection can be extracted in the part; And
Described one in response to vibration output and in can extracting partly to generate phase detectors output from phase detectors.
18. method as claimed in claim 17 is wherein regulated the signal through overregulate of reference signal in the middle of generating and is comprised reference signal and output mixing from the Direct Digital synthesizer.
19. method as claimed in claim 18 is wherein selected to extract in the part one and is comprised bandpass filtering is carried out in the output from the mixing of the output of reference signal and Direct Digital synthesizer.
20. method as claimed in claim 18 is wherein selected to extract in the part one and is comprised and will be outputted to first filter or second filter from the mixing of the output of reference signal and Direct Digital synthesizer.
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| CN200910007051A CN101807916A (en) | 2009-02-09 | 2009-02-09 | Phase-locked loop system and method |
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| CN200910007051A CN101807916A (en) | 2009-02-09 | 2009-02-09 | Phase-locked loop system and method |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103888135A (en) * | 2012-12-20 | 2014-06-25 | 北京普源精电科技有限公司 | Radio-frequency signal source having stray-reducing function |
| CN104836581A (en) * | 2015-05-21 | 2015-08-12 | 南京熊猫电子股份有限公司 | High-performance broadband frequency source generation circuit employing multi-harmonic reference, and generation method |
-
2009
- 2009-02-09 CN CN200910007051A patent/CN101807916A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103888135A (en) * | 2012-12-20 | 2014-06-25 | 北京普源精电科技有限公司 | Radio-frequency signal source having stray-reducing function |
| CN103888135B (en) * | 2012-12-20 | 2018-01-16 | 北京普源精电科技有限公司 | It is a kind of that there is the radio-frequency signal source for reducing spuious function |
| CN104836581A (en) * | 2015-05-21 | 2015-08-12 | 南京熊猫电子股份有限公司 | High-performance broadband frequency source generation circuit employing multi-harmonic reference, and generation method |
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Application publication date: 20100818 |