CN101807800A - Novel grid-connected bridge inverter free of dead time effect - Google Patents

Novel grid-connected bridge inverter free of dead time effect Download PDF

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Publication number
CN101807800A
CN101807800A CN 201010123733 CN201010123733A CN101807800A CN 101807800 A CN101807800 A CN 101807800A CN 201010123733 CN201010123733 CN 201010123733 CN 201010123733 A CN201010123733 A CN 201010123733A CN 101807800 A CN101807800 A CN 101807800A
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CN
China
Prior art keywords
signal
circuit
main control
control unit
inverter circuit
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Pending
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CN 201010123733
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Chinese (zh)
Inventor
梅烨
吕晓东
朱晟
苏祥伟
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TAIYANG ELECTRIC CO Ltd ZHEJIANG UNIV HANGZHOU
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TAIYANG ELECTRIC CO Ltd ZHEJIANG UNIV HANGZHOU
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Priority to CN 201010123733 priority Critical patent/CN101807800A/en
Publication of CN101807800A publication Critical patent/CN101807800A/en
Pending legal-status Critical Current

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Abstract

A novel grid-connected bridge inverter free of dead time effect comprises an intelligent main control unit, a signal locking circuit and an inverter circuit; the intelligent main control unit is connected with the signal locking circuit that is connected with the inverter circuit; the intelligent main control unit transmits a high-frequency pulse trigger signal and a locking signal to the signal locking circuit; the signal locking circuit carries out logic operation to the PWM signal and the locking signal transmitted by the intelligent main control unit and then transmits the signals to the gate of a switching power tube in the inverter circuit so as to control the on and off of the switching power tube; the inverter circuit converts DC power to AC power with the same frequency and the same phase as the grid, and then feeds back to the grid. In the invention, since the additional hardware circuit is simply structured without adding dead time compensation algorithm in a control program, thereby improving the utilization rate of DC bus voltage and greatly reducing the harmonic content of output current.

Description

The grid-connected bridge inverter of novel free of dead time effect
Technical field
The present invention relates to a kind of grid-connected bridge inverter.
Background technology
In inverter circuit, because switching device and nonideal switching device, in the time-delay of opening and turn-offing certain hour, in order to guarantee the situation that is not short-circuited between the upper and lower brachium pontis, between adjacent switch periods, need to set the time that a upper and lower brachium pontis turn-offs simultaneously, to guarantee the not conducting simultaneously of upper and lower brachium pontis, the time that the upper and lower brachium pontis of this section turn-offs simultaneously is called Dead Time.In Dead Time, because the existence of fly-wheel diode, inverter still can output current, but the adding in dead band also brings the waveform of output voltage and electric current to produce and contains problems such as the industrial frequency harmonic, the fundamental voltage amplitude that are difficult to filtering descend, the utilance of DC bus-bar voltage is lower in distortion, the output current.
Solve the method that dead-time problem mainly adopts compensation at present, divide both direction: a kind of is hardware compensating, and this compensation needing relatively to obtain the voltage signal of compensation by output virtual voltage and reference voltage level.Another kind is a software compensation, adopts the method for pure software, adds the algorithm of dead area compensation in control program, realizes the compensation to the dead band influence.
Summary of the invention
The present invention avoids the defective of dead area compensation, and a kind of grid-connected bridge inverter of novel free of dead time effect is provided.
The technical solution used in the present invention:
The grid-connected bridge inverter of novel free of dead time effect, it is characterized in that: comprise intelligent main control unit, signal lockout circuit, inverter circuit, described intelligent main control unit links to each other with the signal lockout circuit, described signal lockout circuit links to each other with inverter circuit, and described intelligent main control unit carries high-frequency impulse triggering signal and locking signal to give the signal lockout circuit; Described signal lockout circuit will be carried out logical operation by pwm signal and the locking signal that intelligent main control unit is carried, and signal is delivered to the gate pole of switching power tube in the inverter circuit, opening and turn-offing with the control switch power tube the most at last; Described inverter circuit is converted into direct current energy and the AC energy of electrical network with the frequency homophase, sends back in the electrical network.
Further, described signal lockout circuit comprises three couples of arithmetic logic unit U1A, U1B, U2A, U2B, U3A, U3B and not gate logical block U4, U5 and U6;
Described inverter circuit comprises switching power tube T1, T2, T3, T4, T5 and T6, and described switching power tube all connects in the mode of half-bridge.
Perhaps, described signal lockout circuit comprises a pair of arithmetic logic unit U7A, U7B and not gate logical block U8;
Described inverter circuit comprises switching power tube Q1 and Q2.
Further, string has the element of voltage detecting on the half-bridge of described inverter circuit.
Intelligent main control unit of the present invention adopts 16 or higher DSP or MCU or single-chip microcomputer as main control chip.
String has the element of voltage detecting on the half-bridge of inverter circuit of the present invention, detected output voltage signal is passed in the intelligent main control unit, use for internal algorithm, and intelligent main control unit is according to the correct locking signal of detected voltage direction output on the main circuit, to shield the gate pulse triggering signal of one of them switching power tube on each half-bridge, only export the gate pulse triggering signal of another switching power tube.
For bridge circuit, in fact in a switch periods, difference according to the sense of current, electric current only flows through the body of one of them from the pair of switches power tube, and to another switching power tube, then be from it anti-and diode flow through, turning on and off of diode is not need control signal, therefore as long as, can shield the gate pulse triggering signal of a switching power tube, only export the gate pulse triggering signal of a switching power tube by detecting the brachium pontis sense of current.In this case, the change of current of upper and lower brachium pontis realizes automatically by diode, therefore also just no longer needs Dead Time also can guarantee the reliable change of current.
The load that the present invention is mainly used in inverter is an AC network, so power network current is identical with voltage-phase, because power network current is difficult to detect its zero crossing, the voltage detecting zero crossing is then comparatively convenient, replace current zero-crossing point to detect so the present invention adopts voltage over zero to detect, realize the phase identification of line voltage electric current.
Advantage of the present invention: the hardware circuit of interpolation is simple, does not need in the control program to add the dead area compensation algorithm, has improved the utilance of DC bus-bar voltage, greatly reduces the harmonic content of output current.
Description of drawings
Fig. 1 is a structured flowchart of the present invention.
Fig. 2 is the circuit diagram of the embodiment of the invention one.
Fig. 3 is the circuit diagram of the embodiment of the invention two.
Fig. 4 is sine wave modulation of the present invention and s operation control schematic diagram.
Embodiment
Embodiment one
With reference to Fig. 1, Fig. 2, the grid-connected bridge inverter of novel free of dead time effect, comprise intelligent main control unit 1, signal lockout circuit 2, inverter circuit 3, described intelligent main control unit 1 links to each other with signal lockout circuit 2, described signal lockout circuit 2 links to each other with inverter circuit 3, and described intelligent main control unit 1 carries high-frequency impulse triggering signal and locking signal to give the signal lockout circuit; Described signal lockout circuit 2 will be carried out logical operation by pwm signal and the locking signal that intelligent main control unit is carried, and signal is delivered to the gate pole of switching power tube in the inverter circuit 3, opening and turn-offing with the control switch power tube the most at last; Described inverter circuit 3 is converted into direct current energy and the AC energy of electrical network with the frequency homophase, sends back in the electrical network.
Described signal lockout circuit 2 comprises three couples of arithmetic logic unit U1A, U1B, U2A, U2B, U3A, U3B and not gate logical block U4, U5 and U6;
Described inverter circuit 3 comprises switching power tube T1, T2, T3, T4, T5 and T6, and described switching power tube all connects in the mode of half-bridge.
String has the element of voltage detecting on the half-bridge of described inverter circuit 3.
Intelligent main control unit of the present invention 1 adopts 16 or higher DSP or MCU or single-chip microcomputer as main control chip.
String has the element of voltage detecting on the half-bridge of inverter circuit 3 of the present invention, detected output voltage signal is passed in the intelligent main control unit 1, use for internal algorithm, and intelligent main control unit 1 is according to the correct locking signal of detected voltage direction output on the main circuit, to shield the gate pulse triggering signal of one of them switching power tube on each half-bridge, only export the gate pulse triggering signal of another switching power tube.
The chip that arithmetic logic unit adopts in the signal lockout circuit 2 in the present embodiment is 74HCl4D and 74HC08D, to handle the pwm signal and the locking signal of intelligent main control unit 1 output.Logical operation by the signal lockout circuit forms on three groups of gate pulse triggering signals control inverter circuit 3 brachium pontis three groups the opening and turn-offing of switching power tube up and down.
Embodiment two
With reference to Fig. 1, Fig. 3, the difference of present embodiment and embodiment one is that described signal lockout circuit 2 comprises a pair of arithmetic logic unit U7A, U7B and not gate logical block U8; Described inverter circuit 3 comprises switching power tube Q1 and Q2.All the other 26S Proteasome Structure and Functions are identical.
With reference to Fig. 4, the control ring of this algorithm is output as sinusoidal given signal, this given signal is by comparing with triangular carrier, generate pwm signal and one group of locking signal of one group of complementation, these two groups of signals produce the work of the upper and lower brachium pontis switching power tube of gate pole pulse triggering signal control inverter circuit 3 by logical operation a pair of and door and NAND gate.
The described content of this specification embodiment only is enumerating the way of realization of inventive concept; protection scope of the present invention should not be regarded as only limiting to the concrete form that embodiment states, protection scope of the present invention also reach in those skilled in the art conceive according to the present invention the equivalent technologies means that can expect.

Claims (4)

1. the grid-connected bridge inverter of novel free of dead time effect, it is characterized in that: comprise intelligent main control unit, signal lockout circuit, inverter circuit, described intelligent main control unit links to each other with the signal lockout circuit, described signal lockout circuit links to each other with inverter circuit, and described intelligent main control unit carries high-frequency impulse triggering signal and locking signal to give the signal lockout circuit; Described signal lockout circuit will be carried out logical operation by pwm signal and the locking signal that intelligent main control unit is carried, and signal is delivered to the gate pole of switching power tube in the inverter circuit, opening and turn-offing with the control switch power tube the most at last; Described inverter circuit is converted into direct current energy and the AC energy of electrical network with the frequency homophase, sends back in the electrical network.
2. the grid-connected bridge inverter of novel free of dead time effect according to claim 1, it is characterized in that: described signal lockout circuit comprises three couples of arithmetic logic unit U1A, U1B, U2A, U2B, U3A, U3B and not gate logical block U4, U5 and U6;
Described inverter circuit comprises switching power tube T1, T2, T3, T4, T5 and T6, and described switching power tube all connects in the mode of half-bridge.
3. the grid-connected bridge inverter of novel free of dead time effect according to claim 1, it is characterized in that: described signal lockout circuit comprises a pair of arithmetic logic unit U7A, U7B and not gate logical block U8; Described inverter circuit comprises switching power tube Q1 and Q2.
4. according to the grid-connected bridge inverter of claim 2 or 3 described novel free of dead time effect, it is characterized in that: string has the element of voltage detecting on the half-bridge of described inverter circuit.
CN 201010123733 2010-03-12 2010-03-12 Novel grid-connected bridge inverter free of dead time effect Pending CN101807800A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN 201010123733 CN101807800A (en) 2010-03-12 2010-03-12 Novel grid-connected bridge inverter free of dead time effect

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Application Number Priority Date Filing Date Title
CN 201010123733 CN101807800A (en) 2010-03-12 2010-03-12 Novel grid-connected bridge inverter free of dead time effect

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103401450A (en) * 2013-07-30 2013-11-20 中国西电电气股份有限公司 Dead region compensating method

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002142465A (en) * 2000-10-31 2002-05-17 Meidensha Corp Semiconductor power converter
CN2702525Y (en) * 2004-06-16 2005-05-25 美的集团有限公司 Dead zone control driving signal generating device

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002142465A (en) * 2000-10-31 2002-05-17 Meidensha Corp Semiconductor power converter
CN2702525Y (en) * 2004-06-16 2005-05-25 美的集团有限公司 Dead zone control driving signal generating device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103401450A (en) * 2013-07-30 2013-11-20 中国西电电气股份有限公司 Dead region compensating method

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Open date: 20100818