CN101807535B - Gate oxide layer failure analysis method and used test structure - Google Patents

Gate oxide layer failure analysis method and used test structure Download PDF

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CN101807535B
CN101807535B CN2009100461454A CN200910046145A CN101807535B CN 101807535 B CN101807535 B CN 101807535B CN 2009100461454 A CN2009100461454 A CN 2009100461454A CN 200910046145 A CN200910046145 A CN 200910046145A CN 101807535 B CN101807535 B CN 101807535B
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semiconductor device
gate oxide
oxide layer
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test structure
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CN101807535A (en
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郭强
王玉科
龚斌
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Semiconductor Manufacturing International Shanghai Corp
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Abstract

本发明涉及一种用于栅氧化层失效分析的测试结构及栅氧化层失效分析方法,所述测试结构包括含有栅氧化层的待测半导体器件,以及位于所述待测半导体器件外围的在施加偏置电压后能产生光发射的至少1个半导体器件,避免了现有技术在失效定位过程中产生的叠图偏差,达到准确定位栅氧化层的失效位置的目的。

The invention relates to a test structure and a gate oxide failure analysis method for failure analysis of a gate oxide layer. The test structure includes a semiconductor device to be tested containing a gate oxide layer, and an applied At least one semiconductor device capable of producing light emission after the bias voltage avoids the overlay deviation generated in the failure location process in the prior art, and achieves the purpose of accurately locating the failure location of the gate oxide layer.

Description

栅氧化层失效分析方法及所用测试结构Gate Oxide Layer Failure Analysis Method and Test Structure Used

技术领域 technical field

本发明涉及半导体器件的制造领域,尤其涉及用于栅氧化层失效分析的测试结构及栅氧化层失效分析方法。The invention relates to the manufacturing field of semiconductor devices, in particular to a test structure for failure analysis of a gate oxide layer and a failure analysis method for a gate oxide layer.

背景技术 Background technique

随着集成电路的尺寸越来越小,半导体器件的栅氧化层的品质以及可靠性变的越来越重要。但是,由于半导体器件尺寸的减小,如何定位栅氧化层上存在的微小缺陷并理解其失效机理变的越来越困难。As the size of integrated circuits becomes smaller, the quality and reliability of gate oxide layers of semiconductor devices become more and more important. However, due to the reduction in the size of semiconductor devices, how to locate the tiny defects existing on the gate oxide layer and understand the failure mechanism becomes more and more difficult.

目前,集成电路制造领域主要采用发光显微镜(Photo EmissionMicroscopy,PEM)来定位半导体器件的失效点。对半导体器件的栅氧化层施加偏置电压,当半导体器件上存在失效点时,失效点会产生大量光发射,发光显微镜可以检测到这些光发射,形成发光点的图像。所述的失效点比如栅氧化层上存在的缺陷点,存在漏电的点等。At present, Photo Emission Microscopy (PEM) is mainly used in the field of integrated circuit manufacturing to locate failure points of semiconductor devices. Apply a bias voltage to the gate oxide layer of the semiconductor device. When there is a failure point on the semiconductor device, the failure point will generate a large amount of light emission. The light emission microscope can detect these light emissions and form an image of the light-emitting point. The failure points are, for example, defect points existing on the gate oxide layer, points where electric leakage exists, and the like.

如图1所示,为现有的含有栅氧化层的半导体器件的结构示意图,其中,1为器件的有源区,2为器件的栅极区域,通常为多晶硅,1和2交叠的区域为栅氧化层所在区域。通常,用PEM定位栅氧化层上失效点的方法包括:首先,对失效器件加偏置电压,并通过光探测器(Detector)捕捉半导体器件的栅氧化层的失效点上产生的发光点,并将所述发光点的位置显示在影像系统上,所述光探测器例如为电荷耦合器件(CCD)或者MCT(HgCdTe)探测器;其次,将光探测器捕捉到的发光点位置与通过光显微镜(Optical Microscopy)观测到的半导体器件的影像作叠图(overlay),即可确定半导体器件上失效点的位置。As shown in Figure 1, it is a schematic structural diagram of an existing semiconductor device containing a gate oxide layer, where 1 is the active region of the device, 2 is the gate region of the device, usually polysilicon, and the area where 1 and 2 overlap is the area where the gate oxide layer is located. Usually, the method of using PEM to locate the failure point on the gate oxide layer includes: first, applying a bias voltage to the failure device, and capturing the luminous point generated on the failure point of the gate oxide layer of the semiconductor device by a photodetector (Detector), and The position of the luminescent point is displayed on the imaging system, and the photodetector is, for example, a charge-coupled device (CCD) or MCT (HgCdTe) detector; secondly, the position of the luminescent point captured by the photodetector is compared with the (Optical Microscopy) Overlay the image of the semiconductor device observed to determine the location of the failure point on the semiconductor device.

由于需要把两次成像(发光点的像,与物理图像)的图做叠图处理(叠图的目的是将发光点的像,对应到实际的失效点的物理位置),叠图的精确性受两次成像的成像部件本身的标度(Calibration)的精确性限制,因此,在做叠图处理后,获取的栅氧化层上失效点的位置与实际失效点的位置不同,存在几微米的误差,导致无法准确的获取失效点,也就无法准确分析产生失效点的根本原因。如图2所示,即为实际工艺中在定位栅氧化层上失效位置时产生偏差的结构示意图,3为通过光探测器(Detector)捕捉到的半导体器件的栅氧化层的失效点所产生的发光点的位置,4为叠图处理后获取的栅氧化层的失效点的位置,从图中可以看出,存在较大的误差。随着半导体器件的尺寸越来越小,需要准确定位栅氧化层上失效点的位置,这种误差不能满足工艺可靠性设计以及良率的需要。Due to the need to overlay the images of the two images (the image of the luminous point and the physical image) (the purpose of the overlay is to map the image of the luminous point to the actual physical location of the failure point), the accuracy of the overlay Limited by the accuracy of the calibration of the imaging components themselves, after the overlay processing, the position of the failure point on the gate oxide layer obtained is different from the actual position of the failure point, and there is a difference of a few microns. Errors make it impossible to accurately obtain the failure point, and it is also impossible to accurately analyze the root cause of the failure point. As shown in Figure 2, it is a schematic diagram of the structure of the deviation when locating the failure position on the gate oxide layer in the actual process, and 3 is the failure point of the gate oxide layer of the semiconductor device captured by the photodetector (Detector). The position of the luminous point, 4 is the position of the failure point of the gate oxide layer obtained after the overlay processing, and it can be seen from the figure that there is a large error. As the size of semiconductor devices becomes smaller and smaller, it is necessary to accurately locate the failure point on the gate oxide layer, and this error cannot meet the requirements of process reliability design and yield rate.

发明内容 Contents of the invention

本发明所要解决的技术问题是提供一种用于栅氧化层失效分析的测试结构,以准确的定位半导体器件的栅氧化层上的失效点。The technical problem to be solved by the present invention is to provide a test structure for failure analysis of the gate oxide layer to accurately locate the failure point on the gate oxide layer of the semiconductor device.

为解决上述问题,本发明提供一种用于栅氧化层失效分析的测试结构,包括含有栅氧化层的待测半导体器件,以及位于所述待测半导体器件外围的在施加偏置电压后能产生光发射的至少1个半导体器件。In order to solve the above problems, the present invention provides a test structure for gate oxide layer failure analysis, including a semiconductor device to be tested containing a gate oxide layer, and a semiconductor device located on the periphery of the semiconductor device to be tested that can produce Light-emitting at least 1 semiconductor device.

可选的,所述至少1个半导体器件为MOS晶体管或者PN结。可选的,所述至少1个半导体器件为3个。可选的,所述至少1个半导体器件位于同一平面内。可选的,所述至少1个半导体器件设置在所述半导体器件外围的切割道上。Optionally, the at least one semiconductor device is a MOS transistor or a PN junction. Optionally, there are three at least one semiconductor device. Optionally, the at least one semiconductor device is located in the same plane. Optionally, the at least one semiconductor device is disposed on a scribe line around the semiconductor device.

本发明还提供一种栅氧化层失效分析方法,包括:在含有栅氧化层的待测半导体器件外围设置在施加偏置电压后能产生光发射的至少1个半导体器件;The present invention also provides a failure analysis method for a gate oxide layer, comprising: arranging at least one semiconductor device capable of emitting light after a bias voltage is applied on the periphery of a semiconductor device to be tested containing a gate oxide layer;

对所述至少1个半导体器件施加偏置电压,捕捉其产生的发光点;Applying a bias voltage to the at least one semiconductor device to capture the luminous point generated by it;

对含有栅氧化层的待测半导体器件施加偏置电压,捕捉栅氧化层的失效点上产生的发光点;Apply a bias voltage to the semiconductor device under test containing the gate oxide layer to capture the luminescent point generated on the failure point of the gate oxide layer;

计算栅氧化层的失效点上产生的发光点与至少1个半导体器件产生的发光点的相对位置;Calculating the relative position of the luminous point generated on the failure point of the gate oxide layer and the luminous point generated by at least one semiconductor device;

根据所述至少1个半导体器件的实际物理位置和计算得到的栅氧化层的失效点上产生的发光点与至少1个半导体器件产生的发光点的相对位置定位栅氧化层的失效点的实际物理位置。The actual physical location of the failure point of the gate oxide layer based on the actual physical position of the at least one semiconductor device and the calculated relative position of the luminous point generated on the failure point of the gate oxide layer and the luminous point generated by the at least one semiconductor device Location.

可选的,所述至少1个半导体器件为MOS晶体管或者PN结。可选的,所述至少1个半导体器件设置在所述半导体器件外围的切割道上。Optionally, the at least one semiconductor device is a MOS transistor or a PN junction. Optionally, the at least one semiconductor device is disposed on a scribe line around the semiconductor device.

与现有技术相比,本发明具有下列优点:Compared with the prior art, the present invention has the following advantages:

采用本发明所述的用于栅氧化层失效分析的测试结构以及栅氧化层失效分析方法,利用在施加偏置电压后能产生光发射的至少一个半导体器件与含有栅氧化层的待测半导体器件,使用一次成像,保证发光点之间的相对位置是精确的,失效点的物理位置可以使用相对位置精确定位,避免了现有工艺必须将探测器捕捉到的栅氧化层的失效位置产生的发光点与通过光显微镜(Optical Microscopy)观测到的半导体器件的影像作叠图的工艺步骤,从而避免在叠图过程中产生的偏差,达到准确定位栅氧化层的失效位置的目的。Using the test structure for failure analysis of the gate oxide layer and the failure analysis method for the gate oxide layer according to the present invention, at least one semiconductor device capable of generating light emission after applying a bias voltage and the semiconductor device to be tested containing the gate oxide layer are used , use one imaging to ensure that the relative position between the luminous points is accurate, the physical position of the failure point can be precisely positioned using the relative position, avoiding the luminescence generated by the failure position of the gate oxide layer that must be captured by the detector in the existing process The process step of overlaying the dots with the image of the semiconductor device observed through the optical microscope (Optical Microscopy), so as to avoid the deviation during the overlay process and achieve the purpose of accurately locating the failure position of the gate oxide layer.

附图说明 Description of drawings

图1为现有技术含有栅氧化层的半导体器件的结构示意图;1 is a schematic structural view of a semiconductor device containing a gate oxide layer in the prior art;

图2为现有技术实际工艺中在定位栅氧化层上失效位置时产生偏差的结构示意图;FIG. 2 is a structural schematic diagram of deviations generated when locating the failure position on the gate oxide layer in the actual process of the prior art;

图3为本发明实施例用于栅氧化层失效分析的测试结构的结构示意图;3 is a schematic structural diagram of a test structure used for failure analysis of a gate oxide layer according to an embodiment of the present invention;

图4为应用本发明实施例提供的用于栅氧化层失效分析的测试结构定位栅氧化层上失效位置的结果示意图。FIG. 4 is a schematic diagram of the result of locating the failure position on the gate oxide layer by using the test structure provided by the embodiment of the present invention for failure analysis of the gate oxide layer.

具体实施方式 Detailed ways

针对背景技术中论述的现有技术的缺陷,本发明提供一种用于栅氧化层失效分析的测试结构,通过所述测试结构进行失效分析时,可以避免采用叠图工艺,从而避免在叠图过程中产生的偏差,准确定位栅氧化层的失效位置。Aiming at the defects of the prior art discussed in the background technology, the present invention provides a test structure for failure analysis of the gate oxide layer. When performing failure analysis through the test structure, it is possible to avoid the use of the overlay process, thereby avoiding the overlay process. The deviation generated in the process can accurately locate the failure position of the gate oxide layer.

下面结合实施例对本发明提供的用于栅氧化层失效分析的测试结构进行详细说明。The test structure for failure analysis of the gate oxide layer provided by the present invention will be described in detail below with reference to the embodiments.

本实施例提供一种用于栅氧化层失效分析的测试结构,参考附图3所示,包括含有栅氧化层的待测半导体器件,图中21为待测半导体器件的有源区,22为待测半导体器件的栅极区域,通常为多晶硅,21和22交叠的区域为栅氧化层所在区域。,以及位于所述待测半导体器件外围的在施加偏置电压后能产生光发射的至少1个半导体器件23。可选的,所述至少1个半导体器件为MOS晶体管或者PN结。可选的,所述至少1个半导体器件为3个或者3个以上。所述的光发射产生的是波长范围在700~1600nm的光波,比如1100nm附近的红外光。This embodiment provides a test structure for failure analysis of the gate oxide layer. Referring to the accompanying drawing 3, it includes a semiconductor device to be tested that contains a gate oxide layer. The gate area of the semiconductor device to be tested is usually polysilicon, and the overlapping area of 21 and 22 is the area where the gate oxide layer is located. , and at least one semiconductor device 23 that can emit light after a bias voltage is applied and is located on the periphery of the semiconductor device to be tested. Optionally, the at least one semiconductor device is a MOS transistor or a PN junction. Optionally, the at least one semiconductor device is three or more. The light emission produces light waves with a wavelength in the range of 700-1600nm, such as infrared light around 1100nm.

本实施例所提供的测试结构中,所述至少一个半导体器件被加上偏置电压时,可以产生光发射,通过光探测器可以捕捉所述至少一个半导体器件产生的光发射的位置,同时,其实际物理位置是已知的,待测半导体器件上的缺陷点在被加上偏置电压时,也可以产生光发射,因此,根据至少1个半导体器件的实际物理位置和计算得到的待测半导体器件的栅氧化层的失效点上产生的发光点与至少1个半导体器件产生的发光点的相对位置,即可定位栅氧化层的失效点的实际物理位置。In the test structure provided by this embodiment, when the at least one semiconductor device is applied with a bias voltage, it can generate light emission, and the position of the light emission generated by the at least one semiconductor device can be captured by the photodetector, and at the same time, Its actual physical position is known, and the defect point on the semiconductor device to be tested can also generate light emission when a bias voltage is applied. Therefore, according to the actual physical position of at least one semiconductor device and the calculated The relative position of the luminous point generated on the failure point of the gate oxide layer of the semiconductor device and the luminous point generated by at least one semiconductor device can locate the actual physical position of the failure point of the gate oxide layer.

本实施例中,所述的偏置电压优选为同时加在所述至少1个半导体器件以及包括栅氧化层的待测半导体器件上,让产生的所有发光点一次成像,可不需要叠图计算相对位置。In this embodiment, the bias voltage is preferably applied to the at least one semiconductor device and the semiconductor device to be tested including the gate oxide layer at the same time, so that all the generated luminous points can be imaged at one time, and there is no need to calculate the relative Location.

可选的,所述的至少1个半导体器件产生的光发射的强度还可以根据同栅氧化层的失效点产生的光发射的强度进行调解,当至少1个半导体器件产生的光发射的强度与栅氧化层的失效点产生的光发射的强度相同时,可以更好的定位栅氧化层上失效点的位置。本实施例所述的强度相同,并不要求强度严格相同,同一个数量级即可,这是因为如果强度相差太大,太弱的发光点会掩盖失效点,太强的发光点会被失效点掩盖。Optionally, the intensity of the light emission generated by the at least one semiconductor device can also be adjusted according to the intensity of the light emission generated by the failure point of the same gate oxide layer, when the intensity of the light emission generated by at least one semiconductor device is the same as When the intensity of light emitted by the failure point of the gate oxide layer is the same, the location of the failure point on the gate oxide layer can be better located. The intensity described in this embodiment is the same, and it does not require that the intensity be strictly the same, and the same order of magnitude is enough. This is because if the intensity difference is too large, too weak luminous points will cover up the failure points, and too strong luminous points will be replaced by failure points. cover.

本实施例不限制所设置的MOS晶体管的数量,但是,由于不在同一直线上的3个点可以定位一个平面,因此,本实施例更加优选的技术方案为在含有栅氧化层的半导体器件周围设置3个或者3个以上的MOS晶体管或者PN结,最为优选的是设置3个MOS晶体管或者PN结。当栅氧化层上存在失效点时,通过测量失效点相对应3个MOS晶体管或者PN结产生的发光点的位置,即可以在一个平面上准确定位发光点的位置所述的至少3个MOS晶体管或者PN结应该位于同一平面内。This embodiment does not limit the number of MOS transistors provided, but since three points that are not on the same straight line can locate a plane, the more preferred technical solution of this embodiment is to arrange around the semiconductor device containing the gate oxide layer Three or more MOS transistors or PN junctions, most preferably three MOS transistors or PN junctions. When there is a failure point on the gate oxide layer, by measuring the position of the failure point corresponding to the luminous point generated by the 3 MOS transistors or the PN junction, that is, the position of the luminous point can be accurately located on a plane. The at least 3 MOS transistors Or the PN junction should be in the same plane.

为了不影响半导体器件的制作工艺,节约成本,稳定工艺,本施实例所述的1个半导体器件被设置在所述半导体器件外围的切割道(Scribe line)上,当对所述的1个半导体器件施加偏置电压时,可通过衬垫(Pad)连接到外接电源。In order not to affect the manufacturing process of the semiconductor device, save cost, and stabilize the process, the 1 semiconductor device described in the embodiment is arranged on the scribe line (Scribe line) on the periphery of the semiconductor device. When the bias voltage is applied to the device, it can be connected to an external power supply through the pad.

而且,所述的至少1个半导体器件不需要与所述的半导体器件产生点连接关系,避免了外加器件对半导体器件自身性能的影响。本实施例对所述的至少1个半导体器件之间的连接关系,以及连接与否也不做限制。Moreover, the at least one semiconductor device does not need to have a point connection relationship with the semiconductor device, which avoids the influence of external devices on the performance of the semiconductor device itself. In this embodiment, there is no limitation on the connection relationship between the at least one semiconductor device and whether it is connected or not.

通过本实施例所述的测试结构,可以快速,准确的定位栅氧化层的失效位置,从而可以快速判断半导体器件制作工艺中产生栅氧化层失效的原因,并对其进行改进,从而提高器件的可靠性,提高产品良率。Through the test structure described in this embodiment, the failure position of the gate oxide layer can be quickly and accurately located, so that the cause of the failure of the gate oxide layer in the manufacturing process of the semiconductor device can be quickly judged, and it can be improved, thereby improving the reliability of the device. Reliability, improve product yield.

参考图4,为应用本发明实施例提供的用于栅氧化层失效分析的测试结构定位栅氧化层上失效位置的结果示意图,24为通过光探测器(Detector)捕捉到的待测半导体器件的栅氧化层的失效点所产生的发光点的位置,25为采用本实施例所述的测试结构进行失效分析获得的失效点的位置,从图中可以看出,获得的失效点位置的精确度大大提高。Referring to FIG. 4 , it is a schematic diagram of the results of positioning the failure position on the gate oxide layer by applying the test structure provided by the embodiment of the present invention for failure analysis of the gate oxide layer, and 24 is the image of the semiconductor device to be tested captured by the photodetector (Detector). The position of the luminous point produced by the failure point of the gate oxide layer, 25 is the position of the failure point obtained by using the test structure described in this embodiment for failure analysis. It can be seen from the figure that the accuracy of the obtained failure point position is Greatly improve.

本实施例还提供了一种栅氧化层失效分析方法,包括:This embodiment also provides a gate oxide layer failure analysis method, including:

步骤S100,提供含有栅氧化层的待测半导体器件,在含有栅氧化层的待测半导体器件外围设置在施加偏置电压后能产生光发射的至少1个半导体器件;可选的,所述至少1个半导体器件为MOS晶体管或者PN结。Step S100, providing a semiconductor device to be tested containing a gate oxide layer, and setting at least one semiconductor device capable of emitting light after applying a bias voltage on the periphery of the semiconductor device to be tested containing a gate oxide layer; optionally, the at least One semiconductor device is a MOS transistor or a PN junction.

本实施例不限制所设置的MOS晶体管或者PN结的数量,但是,由于不在同一直线上的3个点可以定位一个平面,因此,本实施例更加优选的技术方案为在含有栅氧化层的半导体器件周围设置3个或者3个以上的MOS晶体管或者PN结,最为优选的是设置3个MOS晶体管或者PN结。当栅氧化层上存在失效点时,通过测量失效点相对应3个MOS晶体管或者PN结产生的发光点的位置,即可以在一个平面上准确定位发光点的位置所述的至少3个MOS晶体管或者PN结应该位于同一平面内。This embodiment does not limit the number of MOS transistors or PN junctions provided, but since three points that are not on the same straight line can locate a plane, the more preferred technical solution of this embodiment is to use a semiconductor with a gate oxide layer Three or more MOS transistors or PN junctions are arranged around the device, and three MOS transistors or PN junctions are most preferably arranged. When there is a failure point on the gate oxide layer, by measuring the position of the failure point corresponding to the luminous point generated by the 3 MOS transistors or the PN junction, that is, the position of the luminous point can be accurately located on a plane. The at least 3 MOS transistors Or the PN junction should be in the same plane.

为了不影响半导体器件的制作工艺,节约成本,稳定工艺,本施实例所述的1个半导体器件被设置在所述待测半导体器件外围的切割道(Scribe line)上,当对所述的1个半导体器件施加偏置电压时,可通过衬垫(Pad)连接到外接电源。In order not to affect the manufacturing process of the semiconductor device, save cost, and stabilize the process, the 1 semiconductor device described in the example of this embodiment is arranged on the scribe line (Scribe line) on the periphery of the semiconductor device to be tested. When applying a bias voltage to a semiconductor device, it can be connected to an external power supply through the pad (Pad).

而且,所述的至少1个半导体器件不需要与所述的待测半导体器件产生点连接关系,避免了外加器件对待测半导体器件自身性能的影响。本实施例对所述的至少1个半导体器件之间的连接关系,以及连接与否也不做限制。Moreover, the at least one semiconductor device does not need to have a point connection relationship with the semiconductor device to be tested, which avoids the influence of external devices on the performance of the semiconductor device to be tested. In this embodiment, there is no limitation on the connection relationship between the at least one semiconductor device and whether it is connected or not.

步骤S200,对所述在施加偏置电压后能产生光发射的至少1个半导体器件施加偏置电压,捕捉所述至少1个半导体器件产生的发光点;Step S200, applying a bias voltage to the at least one semiconductor device capable of emitting light after applying the bias voltage, and capturing the luminous point generated by the at least one semiconductor device;

步骤S300,对含有栅氧化层的待测半导体器件施加偏置电压,捕捉栅氧化层的失效点上产生的发光点;Step S300, applying a bias voltage to the semiconductor device under test containing the gate oxide layer, capturing the luminescent point generated on the failure point of the gate oxide layer;

本实施例中,步骤S200以及步骤S300是同时进行的,让产生的所有发光点一次成像,可不需要叠图计算相对位置。In this embodiment, step S200 and step S300 are performed at the same time, so that all generated light-emitting points can be imaged at one time, and the relative positions can be calculated without overlaying images.

通过调节偏置电压的大小,可以调节至少1个半导体器件产生的光发射的强度,通常,所述的至少1个半导体器件产生的光发射的强度是根据同栅氧化层的失效点产生的光发射的强度进行调解的,当至少1个半导体器件产生的光发射的强度与栅氧化层的失效点产生的光发射的强度相同时,可以更好的定位栅氧化层上失效点的位置。本实例所述的强度相同,并不要求强度严格相同,同一个数量级即可,这是因为如果强度相差太大,太弱的发光点会掩盖失效点,太强的发光点会被失效点掩盖。By adjusting the magnitude of the bias voltage, the intensity of the light emission generated by at least one semiconductor device can be adjusted. Usually, the intensity of the light emission generated by the at least one semiconductor device is based on the light generated by the failure point of the same gate oxide layer. The intensity of the emission is adjusted. When the intensity of the light emission generated by at least one semiconductor device is the same as the intensity of the light emission generated by the failure point of the gate oxide layer, the position of the failure point on the gate oxide layer can be better located. The intensity described in this example is the same, and the intensity is not required to be strictly the same, just the same order of magnitude. This is because if the intensity difference is too large, the luminous point that is too weak will cover the failure point, and the luminous point that is too strong will be covered by the failure point. .

本实施例中,所述的至少一个半导体器件的实际位置是已知的,其在施加偏置电压之后产生的发光点的位置是通过光探测器确定的,光探测器捕捉所述的至少一个半导体器件产生的发光点的位置,并将其显示在影像系统上。In this embodiment, the actual position of the at least one semiconductor device is known, and the position of the luminous point generated after the bias voltage is applied is determined by a photodetector, and the photodetector captures the at least one The position of the luminescent point generated by the semiconductor device and displayed on the imaging system.

待测半导体器件的栅氧化层的失效点上产生的发光点也是通过光探测器(Detector)进行的,捕捉到产生所述发光点的位置后,可将发光点及其位置显示在影像系统上,所述光探测器例如为电荷耦合器件(CCD)或者MCT(HgCdTe)探测器,The luminous point generated on the failure point of the gate oxide layer of the semiconductor device to be tested is also detected by a photodetector. After capturing the position where the luminous point is generated, the luminous point and its position can be displayed on the imaging system , the photodetector is, for example, a charge-coupled device (CCD) or MCT (HgCdTe) detector,

最后,进行步骤S400,计算栅氧化层的失效点上产生的发光点与至少1个半导体器件产生的发光点的相对位置;以及步骤S500,根据至少1个半导体器件的实际物理位置和计算得到的栅氧化层的失效点上产生的发光点与至少1个半导体器件产生的发光点的相对位置定位栅氧化层的失效点的实际物理位置。Finally, perform step S400, calculate the relative position of the luminous point generated on the failure point of the gate oxide layer and the luminous point generated by at least one semiconductor device; and step S500, according to the actual physical position of at least one semiconductor device and the calculated The actual physical position of the failure point of the gate oxide layer is determined by the relative position of the luminous point generated on the failure point of the gate oxide layer and the luminescence point generated by at least one semiconductor device.

由于本发明使用一次成像,保证发光点之间的相对位置是精确的,失效点的物理位置可以使用相对位置精确定位,避免了现有工艺必须将探测器捕捉到的栅氧化层的失效位置产生的发光点与通过光显微镜(OpticalMicroscopy)观测到的半导体器件的影像作叠图的工艺步骤,从而避免在叠图过程中产生的偏差,达到准确定位栅氧化层的失效位置的目的。Since the present invention uses one-time imaging, the relative position between the luminous points is guaranteed to be accurate, and the physical position of the failure point can be accurately positioned using the relative position, which avoids the generation of the failure position of the gate oxide layer that must be captured by the detector in the existing process The process step of overlaying the luminescent point of the luminous point with the image of the semiconductor device observed by the optical microscope (Optical Microscopy), so as to avoid the deviation during the overlay process and achieve the purpose of accurately locating the failure position of the gate oxide layer.

本发明虽然仅仅公开了对栅氧化层的失效分析结构以及失效分析方法,实际上,本发明的思路及其技术适用于半导体器件制作工艺中能产生光发射的缺陷分析。Although the present invention only discloses the failure analysis structure and failure analysis method of the gate oxide layer, in fact, the idea and technology of the present invention are applicable to the analysis of defects that can produce light emission in the manufacturing process of semiconductor devices.

本发明虽然以较佳实施例公开如上,但其并不是用来限定权利要求,任何本领域技术人员在不脱离本发明的精神和范围内,都可以做出可能的变动和修改,因此本发明的保护范围应当以本发明权利要求所界定的范围为准。Although the present invention is disclosed as above with preferred embodiments, it is not used to limit the claims. Any person skilled in the art can make possible changes and modifications without departing from the spirit and scope of the present invention. Therefore, the present invention The scope of protection should be based on the scope defined by the claims of the present invention.

Claims (7)

1. test structure that is used for gate oxide layer failure analysis, it is characterized in that, comprise the semiconductor device to be measured that contains gate oxide, and be positioned at described semiconductor device to be measured periphery after applying bias voltage, can produce photoemissive at least 1 semiconductor device, when testing, simultaneously described semiconductor device to be measured and described at least 1 semiconductor device are applied bias voltage, the failpoint on the described semiconductor device to be measured produces the light emission when being coupled with bias voltage.
2. test structure as claimed in claim 1 is characterized in that: described at least 1 semiconductor device is a MOS transistor.
3. test structure as claimed in claim 1 is characterized in that: described at least 1 semiconductor device is a PN junction.
4. test structure as claimed in claim 1 is characterized in that: described at least 1 semiconductor device is 3.
5. test structure as claimed in claim 1 is characterized in that: described at least 1 semiconductor device is positioned at same plane.
6. test structure as claimed in claim 1 is characterized in that: described at least 1 semiconductor device is arranged on the Cutting Road of described semiconductor device periphery.
7. gate oxide layer failure analysis method comprises:
Be arranged in the semiconductor device to be measured periphery of containing gate oxide and can produce photoemissive at least 1 semiconductor device after applying bias voltage;
Described at least 1 semiconductor device is applied bias voltage, catch the luminous point of its generation, simultaneously the semiconductor device to be measured that contains gate oxide is applied bias voltage, catch the luminous point that produces on the failpoint of gate oxide;
The relative position of the luminous point of the luminous point that produces on the failpoint of calculating gate oxide and at least 1 semiconductor device generation;
The actual physical location of the failpoint of the relative position location gate oxide of the luminous point that produces on the failpoint according to the actual physical location of described at least 1 semiconductor device and the gate oxide that calculates and the luminous point of at least 1 semiconductor device generation.
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