CN101807535B - Gate oxide layer failure analysis method and used test structure - Google Patents

Abstract

The invention relates to a test structure and a gate oxide failure analysis method for failure analysis of a gate oxide layer. The test structure includes a semiconductor device to be tested containing a gate oxide layer, and an applied At least one semiconductor device capable of producing light emission after the bias voltage avoids the overlay deviation generated in the failure location process in the prior art, and achieves the purpose of accurately locating the failure location of the gate oxide layer.

Description

Gate Oxide Layer Failure Analysis Method and Test Structure Used

technical field

The invention relates to the manufacturing field of semiconductor devices, in particular to a test structure for failure analysis of a gate oxide layer and a failure analysis method for a gate oxide layer.

Background technique

As the size of integrated circuits becomes smaller, the quality and reliability of gate oxide layers of semiconductor devices become more and more important. However, due to the reduction in the size of semiconductor devices, how to locate the tiny defects existing on the gate oxide layer and understand the failure mechanism becomes more and more difficult.

At present, Photo Emission Microscopy (PEM) is mainly used in the field of integrated circuit manufacturing to locate failure points of semiconductor devices. Apply a bias voltage to the gate oxide layer of the semiconductor device. When there is a failure point on the semiconductor device, the failure point will generate a large amount of light emission. The light emission microscope can detect these light emissions and form an image of the light-emitting point. The failure points are, for example, defect points existing on the gate oxide layer, points where electric leakage exists, and the like.

As shown in Figure 1, it is a schematic structural diagram of an existing semiconductor device containing a gate oxide layer, where 1 is the active region of the device, 2 is the gate region of the device, usually polysilicon, and the area where 1 and 2 overlap is the area where the gate oxide layer is located. Usually, the method of using PEM to locate the failure point on the gate oxide layer includes: first, applying a bias voltage to the failure device, and capturing the luminous point generated on the failure point of the gate oxide layer of the semiconductor device by a photodetector (Detector), and The position of the luminescent point is displayed on the imaging system, and the photodetector is, for example, a charge-coupled device (CCD) or MCT (HgCdTe) detector; secondly, the position of the luminescent point captured by the photodetector is compared with the (Optical Microscopy) Overlay the image of the semiconductor device observed to determine the location of the failure point on the semiconductor device.

Due to the need to overlay the images of the two images (the image of the luminous point and the physical image) (the purpose of the overlay is to map the image of the luminous point to the actual physical location of the failure point), the accuracy of the overlay Limited by the accuracy of the calibration of the imaging components themselves, after the overlay processing, the position of the failure point on the gate oxide layer obtained is different from the actual position of the failure point, and there is a difference of a few microns. Errors make it impossible to accurately obtain the failure point, and it is also impossible to accurately analyze the root cause of the failure point. As shown in Figure 2, it is a schematic diagram of the structure of the deviation when locating the failure position on the gate oxide layer in the actual process, and 3 is the failure point of the gate oxide layer of the semiconductor device captured by the photodetector (Detector). The position of the luminous point, 4 is the position of the failure point of the gate oxide layer obtained after the overlay processing, and it can be seen from the figure that there is a large error. As the size of semiconductor devices becomes smaller and smaller, it is necessary to accurately locate the failure point on the gate oxide layer, and this error cannot meet the requirements of process reliability design and yield rate.

Contents of the invention

The technical problem to be solved by the present invention is to provide a test structure for failure analysis of the gate oxide layer to accurately locate the failure point on the gate oxide layer of the semiconductor device.

In order to solve the above problems, the present invention provides a test structure for gate oxide layer failure analysis, including a semiconductor device to be tested containing a gate oxide layer, and a semiconductor device located on the periphery of the semiconductor device to be tested that can produce Light-emitting at least 1 semiconductor device.

Optionally, the at least one semiconductor device is a MOS transistor or a PN junction. Optionally, there are three at least one semiconductor device. Optionally, the at least one semiconductor device is located in the same plane. Optionally, the at least one semiconductor device is disposed on a scribe line around the semiconductor device.

The present invention also provides a failure analysis method for a gate oxide layer, comprising: arranging at least one semiconductor device capable of emitting light after a bias voltage is applied on the periphery of a semiconductor device to be tested containing a gate oxide layer;

Applying a bias voltage to the at least one semiconductor device to capture the luminous point generated by it;

Apply a bias voltage to the semiconductor device under test containing the gate oxide layer to capture the luminescent point generated on the failure point of the gate oxide layer;

Calculating the relative position of the luminous point generated on the failure point of the gate oxide layer and the luminous point generated by at least one semiconductor device;

The actual physical location of the failure point of the gate oxide layer based on the actual physical position of the at least one semiconductor device and the calculated relative position of the luminous point generated on the failure point of the gate oxide layer and the luminous point generated by the at least one semiconductor device Location.

Optionally, the at least one semiconductor device is a MOS transistor or a PN junction. Optionally, the at least one semiconductor device is disposed on a scribe line around the semiconductor device.

Compared with the prior art, the present invention has the following advantages:

Using the test structure for failure analysis of the gate oxide layer and the failure analysis method for the gate oxide layer according to the present invention, at least one semiconductor device capable of generating light emission after applying a bias voltage and the semiconductor device to be tested containing the gate oxide layer are used , use one imaging to ensure that the relative position between the luminous points is accurate, the physical position of the failure point can be precisely positioned using the relative position, avoiding the luminescence generated by the failure position of the gate oxide layer that must be captured by the detector in the existing process The process step of overlaying the dots with the image of the semiconductor device observed through the optical microscope (Optical Microscopy), so as to avoid the deviation during the overlay process and achieve the purpose of accurately locating the failure position of the gate oxide layer.

Description of drawings

1 is a schematic structural view of a semiconductor device containing a gate oxide layer in the prior art;

FIG. 2 is a structural schematic diagram of deviations generated when locating the failure position on the gate oxide layer in the actual process of the prior art;

3 is a schematic structural diagram of a test structure used for failure analysis of a gate oxide layer according to an embodiment of the present invention;

FIG. 4 is a schematic diagram of the result of locating the failure position on the gate oxide layer by using the test structure provided by the embodiment of the present invention for failure analysis of the gate oxide layer.

Detailed ways

Aiming at the defects of the prior art discussed in the background technology, the present invention provides a test structure for failure analysis of the gate oxide layer. When performing failure analysis through the test structure, it is possible to avoid the use of the overlay process, thereby avoiding the overlay process. The deviation generated in the process can accurately locate the failure position of the gate oxide layer.

The test structure for failure analysis of the gate oxide layer provided by the present invention will be described in detail below with reference to the embodiments.

This embodiment provides a test structure for failure analysis of the gate oxide layer. Referring to the accompanying drawing 3, it includes a semiconductor device to be tested that contains a gate oxide layer. The gate area of the semiconductor device to be tested is usually polysilicon, and the overlapping area of 21 and 22 is the area where the gate oxide layer is located. , and at least one semiconductor device 23 that can emit light after a bias voltage is applied and is located on the periphery of the semiconductor device to be tested. Optionally, the at least one semiconductor device is a MOS transistor or a PN junction. Optionally, the at least one semiconductor device is three or more. The light emission produces light waves with a wavelength in the range of 700-1600nm, such as infrared light around 1100nm.

In the test structure provided by this embodiment, when the at least one semiconductor device is applied with a bias voltage, it can generate light emission, and the position of the light emission generated by the at least one semiconductor device can be captured by the photodetector, and at the same time, Its actual physical position is known, and the defect point on the semiconductor device to be tested can also generate light emission when a bias voltage is applied. Therefore, according to the actual physical position of at least one semiconductor device and the calculated The relative position of the luminous point generated on the failure point of the gate oxide layer of the semiconductor device and the luminous point generated by at least one semiconductor device can locate the actual physical position of the failure point of the gate oxide layer.

In this embodiment, the bias voltage is preferably applied to the at least one semiconductor device and the semiconductor device to be tested including the gate oxide layer at the same time, so that all the generated luminous points can be imaged at one time, and there is no need to calculate the relative Location.

Optionally, the intensity of the light emission generated by the at least one semiconductor device can also be adjusted according to the intensity of the light emission generated by the failure point of the same gate oxide layer, when the intensity of the light emission generated by at least one semiconductor device is the same as When the intensity of light emitted by the failure point of the gate oxide layer is the same, the location of the failure point on the gate oxide layer can be better located. The intensity described in this embodiment is the same, and it does not require that the intensity be strictly the same, and the same order of magnitude is enough. This is because if the intensity difference is too large, too weak luminous points will cover up the failure points, and too strong luminous points will be replaced by failure points. cover.

This embodiment does not limit the number of MOS transistors provided, but since three points that are not on the same straight line can locate a plane, the more preferred technical solution of this embodiment is to arrange around the semiconductor device containing the gate oxide layer Three or more MOS transistors or PN junctions, most preferably three MOS transistors or PN junctions. When there is a failure point on the gate oxide layer, by measuring the position of the failure point corresponding to the luminous point generated by the 3 MOS transistors or the PN junction, that is, the position of the luminous point can be accurately located on a plane. The at least 3 MOS transistors Or the PN junction should be in the same plane.

In order not to affect the manufacturing process of the semiconductor device, save cost, and stabilize the process, the 1 semiconductor device described in the embodiment is arranged on the scribe line (Scribe line) on the periphery of the semiconductor device. When the bias voltage is applied to the device, it can be connected to an external power supply through the pad.

Moreover, the at least one semiconductor device does not need to have a point connection relationship with the semiconductor device, which avoids the influence of external devices on the performance of the semiconductor device itself. In this embodiment, there is no limitation on the connection relationship between the at least one semiconductor device and whether it is connected or not.

Through the test structure described in this embodiment, the failure position of the gate oxide layer can be quickly and accurately located, so that the cause of the failure of the gate oxide layer in the manufacturing process of the semiconductor device can be quickly judged, and it can be improved, thereby improving the reliability of the device. Reliability, improve product yield.

Referring to FIG. 4 , it is a schematic diagram of the results of positioning the failure position on the gate oxide layer by applying the test structure provided by the embodiment of the present invention for failure analysis of the gate oxide layer, and 24 is the image of the semiconductor device to be tested captured by the photodetector (Detector). The position of the luminous point produced by the failure point of the gate oxide layer, 25 is the position of the failure point obtained by using the test structure described in this embodiment for failure analysis. It can be seen from the figure that the accuracy of the obtained failure point position is Greatly improve.

This embodiment also provides a gate oxide layer failure analysis method, including:

Step S100, providing a semiconductor device to be tested containing a gate oxide layer, and setting at least one semiconductor device capable of emitting light after applying a bias voltage on the periphery of the semiconductor device to be tested containing a gate oxide layer; optionally, the at least One semiconductor device is a MOS transistor or a PN junction.

This embodiment does not limit the number of MOS transistors or PN junctions provided, but since three points that are not on the same straight line can locate a plane, the more preferred technical solution of this embodiment is to use a semiconductor with a gate oxide layer Three or more MOS transistors or PN junctions are arranged around the device, and three MOS transistors or PN junctions are most preferably arranged. When there is a failure point on the gate oxide layer, by measuring the position of the failure point corresponding to the luminous point generated by the 3 MOS transistors or the PN junction, that is, the position of the luminous point can be accurately located on a plane. The at least 3 MOS transistors Or the PN junction should be in the same plane.

In order not to affect the manufacturing process of the semiconductor device, save cost, and stabilize the process, the 1 semiconductor device described in the example of this embodiment is arranged on the scribe line (Scribe line) on the periphery of the semiconductor device to be tested. When applying a bias voltage to a semiconductor device, it can be connected to an external power supply through the pad (Pad).

Moreover, the at least one semiconductor device does not need to have a point connection relationship with the semiconductor device to be tested, which avoids the influence of external devices on the performance of the semiconductor device to be tested. In this embodiment, there is no limitation on the connection relationship between the at least one semiconductor device and whether it is connected or not.

Step S200, applying a bias voltage to the at least one semiconductor device capable of emitting light after applying the bias voltage, and capturing the luminous point generated by the at least one semiconductor device;

Step S300, applying a bias voltage to the semiconductor device under test containing the gate oxide layer, capturing the luminescent point generated on the failure point of the gate oxide layer;

In this embodiment, step S200 and step S300 are performed at the same time, so that all generated light-emitting points can be imaged at one time, and the relative positions can be calculated without overlaying images.

By adjusting the magnitude of the bias voltage, the intensity of the light emission generated by at least one semiconductor device can be adjusted. Usually, the intensity of the light emission generated by the at least one semiconductor device is based on the light generated by the failure point of the same gate oxide layer. The intensity of the emission is adjusted. When the intensity of the light emission generated by at least one semiconductor device is the same as the intensity of the light emission generated by the failure point of the gate oxide layer, the position of the failure point on the gate oxide layer can be better located. The intensity described in this example is the same, and the intensity is not required to be strictly the same, just the same order of magnitude. This is because if the intensity difference is too large, the luminous point that is too weak will cover the failure point, and the luminous point that is too strong will be covered by the failure point. .

In this embodiment, the actual position of the at least one semiconductor device is known, and the position of the luminous point generated after the bias voltage is applied is determined by a photodetector, and the photodetector captures the at least one The position of the luminescent point generated by the semiconductor device and displayed on the imaging system.

The luminous point generated on the failure point of the gate oxide layer of the semiconductor device to be tested is also detected by a photodetector. After capturing the position where the luminous point is generated, the luminous point and its position can be displayed on the imaging system , the photodetector is, for example, a charge-coupled device (CCD) or MCT (HgCdTe) detector,

Finally, perform step S400, calculate the relative position of the luminous point generated on the failure point of the gate oxide layer and the luminous point generated by at least one semiconductor device; and step S500, according to the actual physical position of at least one semiconductor device and the calculated The actual physical position of the failure point of the gate oxide layer is determined by the relative position of the luminous point generated on the failure point of the gate oxide layer and the luminescence point generated by at least one semiconductor device.

Since the present invention uses one-time imaging, the relative position between the luminous points is guaranteed to be accurate, and the physical position of the failure point can be accurately positioned using the relative position, which avoids the generation of the failure position of the gate oxide layer that must be captured by the detector in the existing process The process step of overlaying the luminescent point of the luminous point with the image of the semiconductor device observed by the optical microscope (Optical Microscopy), so as to avoid the deviation during the overlay process and achieve the purpose of accurately locating the failure position of the gate oxide layer.

Although the present invention only discloses the failure analysis structure and failure analysis method of the gate oxide layer, in fact, the idea and technology of the present invention are applicable to the analysis of defects that can produce light emission in the manufacturing process of semiconductor devices.

Although the present invention is disclosed as above with preferred embodiments, it is not used to limit the claims. Any person skilled in the art can make possible changes and modifications without departing from the spirit and scope of the present invention. Therefore, the present invention The scope of protection should be based on the scope defined by the claims of the present invention.

Claims (7)

1. test structure that is used for gate oxide layer failure analysis, it is characterized in that, comprise the semiconductor device to be measured that contains gate oxide, and be positioned at described semiconductor device to be measured periphery after applying bias voltage, can produce photoemissive at least 1 semiconductor device, when testing, simultaneously described semiconductor device to be measured and described at least 1 semiconductor device are applied bias voltage, the failpoint on the described semiconductor device to be measured produces the light emission when being coupled with bias voltage.

2. test structure as claimed in claim 1 is characterized in that: described at least 1 semiconductor device is a MOS transistor.

3. test structure as claimed in claim 1 is characterized in that: described at least 1 semiconductor device is a PN junction.

4. test structure as claimed in claim 1 is characterized in that: described at least 1 semiconductor device is 3.

5. test structure as claimed in claim 1 is characterized in that: described at least 1 semiconductor device is positioned at same plane.

6. test structure as claimed in claim 1 is characterized in that: described at least 1 semiconductor device is arranged on the Cutting Road of described semiconductor device periphery.

7. gate oxide layer failure analysis method comprises:

Be arranged in the semiconductor device to be measured periphery of containing gate oxide and can produce photoemissive at least 1 semiconductor device after applying bias voltage;

Described at least 1 semiconductor device is applied bias voltage, catch the luminous point of its generation, simultaneously the semiconductor device to be measured that contains gate oxide is applied bias voltage, catch the luminous point that produces on the failpoint of gate oxide;

The relative position of the luminous point of the luminous point that produces on the failpoint of calculating gate oxide and at least 1 semiconductor device generation;

The actual physical location of the failpoint of the relative position location gate oxide of the luminous point that produces on the failpoint according to the actual physical location of described at least 1 semiconductor device and the gate oxide that calculates and the luminous point of at least 1 semiconductor device generation.

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