CN101807535B - Gate oxide layer failure analysis method and used test structure - Google Patents
Gate oxide layer failure analysis method and used test structure Download PDFInfo
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- CN101807535B CN101807535B CN2009100461454A CN200910046145A CN101807535B CN 101807535 B CN101807535 B CN 101807535B CN 2009100461454 A CN2009100461454 A CN 2009100461454A CN 200910046145 A CN200910046145 A CN 200910046145A CN 101807535 B CN101807535 B CN 101807535B
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Abstract
The invention relates to a test structure for gate oxide layer failure analysis and a gate oxide layer failure analysis method; the test structure comprises a semi-conductor device to be tested which contains the gate oxide layer, and at least 1 semi-conductor device which is arranged on the periphery of the semi-conductor device to be tested and can produce light emission after bias voltage is applied, thereby preventing overlay error produced in a failure positioning process in the prior art, and achieving the purpose of accurately positioning the failure position of the gate oxide layer.
Description
Technical field
The present invention relates to the manufacturing field of semiconductor device, relate in particular to the test structure and the gate oxide layer failure analysis method that are used for gate oxide layer failure analysis.
Background technology
Along with the size of integrated circuit is more and more littler, it is more and more important that the quality of the gate oxide of semiconductor device and reliability become.But, because how reducing of dimensions of semiconductor devices is located the tiny flaw that exists on the gate oxide and is understood more and more difficult that its failure mechanism becomes.
At present, the integrated circuit field of making is mainly adopted illuminating microscope (Photo EmissionMicroscopy PEM) is located the failpoint of semiconductor device.Gate oxide to semiconductor device applies bias voltage, and when having failpoint on the semiconductor device, failpoint can produce a large amount of light emissions, and illuminating microscope can detect these light emissions, forms the image of luminous point.There is the point of electric leakage etc. in described failpoint such as the defect point that exists on the gate oxide.
As shown in Figure 1, be the existing structural representation that contains the semiconductor device of gate oxide, wherein, 1 is the active area of device, and 2 is the area of grid of device, is generally polysilicon, and 1 and 2 zones that overlap are the gate oxide region.Usually, method with failpoint on the gate oxide of PEM location comprises: at first, ineffective part is biased voltage, and catch the luminous point that produces on the failpoint of gate oxide of semiconductor device by photo-detector (Detector), and with the position display of described luminous point on image system, described photo-detector for example is charge-coupled device (CCD) or MCT (HgCdTe) detector; Secondly, the image of photo-detector luminous point position that captures and the semiconductor device that observes by light microscope (Optical Microscopy) is made folded figure (overlay), can determine the position of failpoint on the semiconductor device.
Because need be twice imaging (picture of luminous point, with physical image) figure be folded figure and handle that (purpose of folded figure is the picture with luminous point, correspond to the physical location of actual failpoint), the accuracy of folded figure is limited by the accuracy of scale (Calibration) of the image-forming block of twice imaging itself, therefore, after doing folded figure processing, the position of failpoint is different with the position of considered repealed point on the gate oxide that obtains, there is several microns error, cause to obtain failpoint accurately, also just can't accurately analyze the basic reason that produces failpoint.As shown in Figure 2, produce the structural representation of deviation when being in the actual process on the gate oxide of location invalid position, 3 positions for the luminous point that failpoint produced of the gate oxide of the semiconductor device that captures by photo-detector (Detector), 4 is the position of folding the failpoint of the gate oxide that obtains after figure handles, as can be seen from the figure, there is bigger error.Along with size of semiconductor device is more and more littler, need accurately to locate the position of failpoint on the gate oxide, this error can not satisfy the needs of reliability of technology design and yield.
Summary of the invention
Technical problem to be solved by this invention provides a kind of test structure that is used for gate oxide layer failure analysis, with the failpoint on the gate oxide of accurate in locating semiconductor device.
For addressing the above problem, the invention provides a kind of test structure that is used for gate oxide layer failure analysis, comprise the semiconductor device to be measured that contains gate oxide, and be positioned at described semiconductor device to be measured periphery after applying bias voltage, can produce photoemissive at least 1 semiconductor device.
Optionally, described at least 1 semiconductor device is MOS transistor or PN junction.Optionally, described at least 1 semiconductor device is 3.Optionally, described at least 1 semiconductor device is positioned at same plane.Optionally, described at least 1 semiconductor device is arranged on the Cutting Road of described semiconductor device periphery.
The present invention also provides a kind of gate oxide layer failure analysis method, comprising: be arranged in the semiconductor device to be measured periphery of containing gate oxide and can produce photoemissive at least 1 semiconductor device after applying bias voltage;
Described at least 1 semiconductor device is applied bias voltage, catch the luminous point of its generation;
The semiconductor device to be measured that contains gate oxide is applied bias voltage, catch the luminous point that produces on the failpoint of gate oxide;
The relative position of the luminous point of the luminous point that produces on the failpoint of calculating gate oxide and at least 1 semiconductor device generation;
The actual physical location of the failpoint of the relative position location gate oxide of the luminous point that produces on the failpoint according to the actual physical location of described at least 1 semiconductor device and the gate oxide that calculates and the luminous point of at least 1 semiconductor device generation.
Optionally, described at least 1 semiconductor device is MOS transistor or PN junction.Optionally, described at least 1 semiconductor device is arranged on the Cutting Road of described semiconductor device periphery.
Compared with prior art, the present invention has following advantage:
Adopt test structure and the gate oxide layer failure analysis method that is used for gate oxide layer failure analysis of the present invention, utilization can produce photoemissive at least one semiconductor device and the semiconductor device to be measured that contains gate oxide after applying bias voltage, use Polaroid, guarantee that the relative position between the luminous point is accurate, the physical location of failpoint can use relative position accurately to locate, avoided the luminous point that the invalid position of the gate oxide that existing technology must capture detector produces and the image of the semiconductor device that observes by light microscope (Optical Microscopy) to make to fold the processing step of figure, thereby avoid the deviation that in folded figure process, produces, reach the purpose of the invalid position of accurate location gate oxide.
Description of drawings
Fig. 1 contains the structural representation of the semiconductor device of gate oxide for prior art;
Fig. 2 is the structural representation that produces deviation in the prior art actual process on the gate oxide of location during invalid position;
Fig. 3 is used for the structural representation of the test structure of gate oxide layer failure analysis for the embodiment of the invention;
The test structure that is used for gate oxide layer failure analysis that Fig. 4 provides for the application embodiment of the invention is located the result schematic diagram of invalid position on the gate oxide.
Embodiment
Defective at the prior art of discussing in the background technology, the invention provides a kind of test structure that is used for gate oxide layer failure analysis, when carrying out failure analysis by described test structure, can avoid adopting folded figure technology, thereby avoid the deviation that in folded figure process, produces, accurately locate the invalid position of gate oxide.
Below in conjunction with embodiment the test structure that is used for gate oxide layer failure analysis provided by the invention is elaborated.
Present embodiment provides a kind of test structure that is used for gate oxide layer failure analysis, with reference to the accompanying drawings shown in 3, comprise the semiconductor device to be measured that contains gate oxide, 21 is the active area of semiconductor device to be measured among the figure, 22 is the area of grid of semiconductor device to be measured, be generally polysilicon, 21 and 22 zones that overlap are the gate oxide region., and be positioned at described semiconductor device to be measured periphery after applying bias voltage, can produce photoemissive at least 1 semiconductor device 23.Optionally, described at least 1 semiconductor device is MOS transistor or PN junction.Optionally, described at least 1 semiconductor device is more than 3 or 3.What described light emission produced is the light wave of wave-length coverage at 700～1600nm, such as near the infrared light the 1100nm.
In the test structure that present embodiment provided, when described at least one semiconductor device is coupled with bias voltage, can produce the light emission, can catch the photoemissive position that described at least one semiconductor device produces by photo-detector, simultaneously, its actual physical location is known, defect point on the semiconductor device to be measured is when being coupled with bias voltage, also can produce the light emission, therefore, the relative position of the luminous point that the luminous point that produces on the failpoint according to the gate oxide of the actual physical location of at least 1 semiconductor device and the semiconductor device to be measured that calculates and at least 1 semiconductor device produce can be located the actual physical location of the failpoint of gate oxide.
In the present embodiment, described bias voltage is preferably and is added in described at least 1 semiconductor device simultaneously and comprises on the semiconductor device to be measured of gate oxide, makes all luminous points of producing Polaroid, can not need folded figure to calculate relative position.
Optionally, the photoemissive intensity that the photoemissive intensity that described at least 1 semiconductor device produces can also produce according to the failpoint with gate oxide is mediated, when the photoemissive intensity that produces when at least 1 semiconductor device is identical with the photoemissive intensity of the failpoint generation of gate oxide, can better locate the position of failpoint on the gate oxide.The described intensity of present embodiment is identical, and the desired strength strictness is not identical, and the same order of magnitude gets final product, and this is that too Ruo luminous point can be covered failpoint because if intensity differs too big, and too strong luminous point can be covered by failpoint.
Present embodiment does not limit the quantity of set MOS transistor, but, because 3 points on same straight line can not located a plane, therefore, the technical scheme that present embodiment is more preferably most preferably is provided with 3 MOS transistor or PN junction for MOS transistor or the PN junction more than 3 or 3 is set around the semiconductor device that contains gate oxide.When having failpoint on the gate oxide, by measuring the position of the luminous point that corresponding 3 MOS transistor of failpoint or PN junction produce, described at least 3 MOS transistor in position or the PN junction that promptly can in one plane accurately locate luminous point should be positioned at same plane.
In order not influence the manufacture craft of semiconductor device, save cost, process for stabilizing, originally execute on the Cutting Road (Scribe line) that described 1 semiconductor device of example is set at described semiconductor device periphery, when described 1 semiconductor device is applied bias voltage, can be connected to external power supply by liner (Pad).
And described at least 1 semiconductor device does not need to produce the some annexation with described semiconductor device, has avoided adding the influence of device to the semiconductor device self performance.Present embodiment is to the annexation between described at least 1 semiconductor device, and whether connects also and do not limit.
By the described test structure of present embodiment, can be quick, the invalid position of accurate in locating gate oxide, thereby can judge fast and produce the gate oxide failure reasons in the semiconductor device fabrication process, and make improvements, thereby the reliability of raising device improves the product yield.
With reference to figure 4, for using the result schematic diagram of invalid position on the test structure location gate oxide that is used for gate oxide layer failure analysis that the embodiment of the invention provides, 24 positions for the luminous point that failpoint produced of the gate oxide of the semiconductor device to be measured that captures by photo-detector (Detector), 25 for adopting the described test structure of present embodiment to carry out the position of the failpoint of failure analysis acquisition, as can be seen from the figure, the accuracy of the failpoint position of acquisition improves greatly.
Present embodiment also provides a kind of gate oxide layer failure analysis method, comprising:
Step S100 provides the semiconductor device to be measured that contains gate oxide, is arranged in the semiconductor device to be measured periphery of containing gate oxide and can produces photoemissive at least 1 semiconductor device after applying bias voltage; Optionally, described at least 1 semiconductor device is MOS transistor or PN junction.
Present embodiment does not limit the set MOS transistor or the quantity of PN junction, but, because 3 points on same straight line can not located a plane, therefore, the technical scheme that present embodiment is more preferably most preferably is provided with 3 MOS transistor or PN junction for MOS transistor or the PN junction more than 3 or 3 is set around the semiconductor device that contains gate oxide.When having failpoint on the gate oxide, by measuring the position of the luminous point that corresponding 3 MOS transistor of failpoint or PN junction produce, described at least 3 MOS transistor in position or the PN junction that promptly can in one plane accurately locate luminous point should be positioned at same plane.
In order not influence the manufacture craft of semiconductor device, save cost, process for stabilizing, originally execute on the Cutting Road (Scribe line) that described 1 semiconductor device of example is set at described semiconductor device to be measured periphery, when described 1 semiconductor device is applied bias voltage, can be connected to external power supply by liner (Pad).
And described at least 1 semiconductor device does not need to produce the some annexation with described semiconductor device to be measured, has avoided adding the influence of device to semiconductor device self performance to be measured.Present embodiment is to the annexation between described at least 1 semiconductor device, and whether connects also and do not limit.
Step S200 can produce photoemissive at least 1 semiconductor device and applies bias voltage described after applying bias voltage, catch the luminous point that described at least 1 semiconductor device produces;
Step S300 applies bias voltage to the semiconductor device to be measured that contains gate oxide, catches the luminous point that produces on the failpoint of gate oxide;
In the present embodiment, step S200 and step S300 carry out simultaneously, make all luminous points of generation Polaroid, can not need folded figure to calculate relative position.
By regulating the size of bias voltage, can regulate the photoemissive intensity that at least 1 semiconductor device produces, usually, the photoemissive intensity that described at least 1 semiconductor device produces is to mediate according to the photoemissive intensity that the failpoint with gate oxide produces, when the photoemissive intensity that produces when at least 1 semiconductor device is identical with the photoemissive intensity of the failpoint generation of gate oxide, can better locate the position of failpoint on the gate oxide.The described intensity of this example is identical, and the desired strength strictness is not identical, and the same order of magnitude gets final product, and this is that too Ruo luminous point can be covered failpoint because if intensity differs too big, and too strong luminous point can be covered by failpoint.
In the present embodiment, the physical location of described at least one semiconductor device is known, the position of the luminous point that it produces after applying bias voltage is determined by photo-detector, photo-detector is caught the position of the luminous point of described at least one semiconductor device generation, and it is presented on the image system.
The luminous point that produces on the failpoint of the gate oxide of semiconductor device to be measured is also undertaken by photo-detector (Detector), after capturing the position that produces described luminous point, can be on image system with luminous point and position display thereof, described photo-detector for example is charge-coupled device (CCD) or MCT (HgCdTe) detector
At last, carry out step S400, the relative position of the luminous point of the luminous point that produces on the failpoint of calculating gate oxide and at least 1 semiconductor device generation; And step S500, the actual physical location of the failpoint of the relative position location gate oxide of the luminous point that produces on the failpoint according to the actual physical location of at least 1 semiconductor device and the gate oxide that calculates and the luminous point of at least 1 semiconductor device generation.
Because the present invention uses Polaroid, guarantee that the relative position between the luminous point is accurate, the physical location of failpoint can use relative position accurately to locate, avoided the luminous point that the invalid position of the gate oxide that existing technology must capture detector produces and the image of the semiconductor device that observes by light microscope (OpticalMicroscopy) to make to fold the processing step of figure, thereby avoid the deviation that in folded figure process, produces, reach the purpose of the invalid position of accurate location gate oxide.
Though the present invention only discloses failure analysis structure and failure analysis method to gate oxide, in fact, thinking of the present invention and technology thereof are applicable in the semiconductor device fabrication process can produce photoemissive defect analysis.
Though the present invention with preferred embodiment openly as above; but it is not to be used for limiting claim; any those skilled in the art without departing from the spirit and scope of the present invention; can make possible change and modification, so protection scope of the present invention should be as the criterion with the scope that claim of the present invention was defined.
Claims (7)
1. test structure that is used for gate oxide layer failure analysis, it is characterized in that, comprise the semiconductor device to be measured that contains gate oxide, and be positioned at described semiconductor device to be measured periphery after applying bias voltage, can produce photoemissive at least 1 semiconductor device, when testing, simultaneously described semiconductor device to be measured and described at least 1 semiconductor device are applied bias voltage, the failpoint on the described semiconductor device to be measured produces the light emission when being coupled with bias voltage.
2. test structure as claimed in claim 1 is characterized in that: described at least 1 semiconductor device is a MOS transistor.
3. test structure as claimed in claim 1 is characterized in that: described at least 1 semiconductor device is a PN junction.
4. test structure as claimed in claim 1 is characterized in that: described at least 1 semiconductor device is 3.
5. test structure as claimed in claim 1 is characterized in that: described at least 1 semiconductor device is positioned at same plane.
6. test structure as claimed in claim 1 is characterized in that: described at least 1 semiconductor device is arranged on the Cutting Road of described semiconductor device periphery.
7. gate oxide layer failure analysis method comprises:
Be arranged in the semiconductor device to be measured periphery of containing gate oxide and can produce photoemissive at least 1 semiconductor device after applying bias voltage;
Described at least 1 semiconductor device is applied bias voltage, catch the luminous point of its generation, simultaneously the semiconductor device to be measured that contains gate oxide is applied bias voltage, catch the luminous point that produces on the failpoint of gate oxide;
The relative position of the luminous point of the luminous point that produces on the failpoint of calculating gate oxide and at least 1 semiconductor device generation;
The actual physical location of the failpoint of the relative position location gate oxide of the luminous point that produces on the failpoint according to the actual physical location of described at least 1 semiconductor device and the gate oxide that calculates and the luminous point of at least 1 semiconductor device generation.
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| CN2009100461454A CN101807535B (en) | 2009-02-12 | 2009-02-12 | Gate oxide layer failure analysis method and used test structure |
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Families Citing this family (8)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN102456666B (en) * | 2010-10-19 | 2013-12-18 | 上海华虹Nec电子有限公司 | Digital coordinate axis and reliability test method of gate oxide film |
| CN103926264B (en) * | 2014-03-04 | 2016-03-02 | 武汉新芯集成电路制造有限公司 | The localization method of gate oxide failpoint |
| CN104078343B (en) * | 2014-07-02 | 2017-02-01 | 武汉新芯集成电路制造有限公司 | Failure analysis method for gate oxide defect original appearance |
| CN105336730B (en) * | 2014-08-01 | 2018-11-02 | 中芯国际集成电路制造(上海)有限公司 | The inter-level dielectric test structure of abnormality detection for first floor metal to grid |
| CN104733343B (en) * | 2015-03-30 | 2018-10-16 | 上海华力微电子有限公司 | Grid oxide layer defect inspection method and element leakage detection method |
| CN106098583B (en) * | 2016-08-19 | 2018-09-18 | 上海华力微电子有限公司 | For the electron beam scanning detection method of polysilicon oxide grid missing |
| CN112305407B (en) * | 2020-10-21 | 2024-06-11 | 上海华力集成电路制造有限公司 | Method for locating failure position and reason of test structure |
| CN112420542B (en) * | 2020-11-26 | 2022-09-20 | 华虹半导体(无锡)有限公司 | Method for positioning failure point in semiconductor device |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1495873A (en) * | 1998-07-01 | 2004-05-12 | ̫����ʽ���� | Optical signal detecting method |
| US20070059850A1 (en) * | 2005-09-14 | 2007-03-15 | Semiconductor Manufacturing International (Shanghai) Corporation | Method and system for derivation of breakdown voltage for MOS integrated circuit devices |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1495873A (en) * | 1998-07-01 | 2004-05-12 | ̫����ʽ���� | Optical signal detecting method |
| US20070059850A1 (en) * | 2005-09-14 | 2007-03-15 | Semiconductor Manufacturing International (Shanghai) Corporation | Method and system for derivation of breakdown voltage for MOS integrated circuit devices |
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