CN101807215B - Method for designing chip for real-time decomposition of mixed pixel of hyper-spectral image - Google Patents

Abstract

The invention belongs to the field of the image processing and provides a chip adopting a field programmable gate array (FPGA) to realize real-time decomposition of a mixed pixel of a hyper-spectral image. The chip adopts a superspeed integrated circuit hardware description language (VHDL) to be completed and consists of a data read-in module (1), a matrix autocorrelation computation module (2), a matrix singular value decomposition module (3), a matrix pseudoinverse computation module (4) and a pixel projection decomposition end-member module (5). The invention adopts the design idea of SYSTEM ON CHIP. Various control signals are generated inside the FPGA to make the whole chip have rapid response. The chip can complete real-time processing of the hyper-spectral image data, can be used for semiconductor processing, and has short development period, low design cost and development risk.

Description

A kind ofly design the method that mixed pixel of hyper-spectral image decomposes chip in real time

Technical field

The present invention relates to a kind of mixed pixel of hyper-spectral image and decompose chip and implementation method in real time.

Technical background

Ground return that remote sensor obtained or emission spectrum signal are unit record with the pixel.It is the comprehensive of the pairing terrestrial materials spectral signal of pixel.The pairing face of land of each pixel often comprises different cover types in the image, and they have different spectral response characteristics.Each pixel is then only used these " heterogeneous " compositions of a signal record.If this pixel only comprises one type, then become pure pixel (pure pixel), the spectral response characteristics or the spectral signal of the type just that it writes down; If this pixel comprises more than a kind of soil cover type, then form mixed pixel (mixed pixel).What mixed pixel write down is the comprehensive of corresponding different soils cover type spectral response characteristic.

Be subjected to complicated multifarious influence of the restricted and nature atural object of the spatial resolution of remote sensor, mixed pixel is prevalent in the remote sensing images, the plant spectrum that records as the field mostly is the mixed spectra (comprising shade toward contact) of plant and underlying surface soil thereof, even the exposed face of land (no vegetation or few vegetation covering) also is the mixed spectra of dissimilar soil, mineral etc.

The requirement that the existence of mixed pixel makes traditional pixel level remote sensing classification and area measurement precision be difficult to reach use.In order to improve the precision of remote sensing application, the resolution problem that solves mixed pixel becomes very necessary.

The application software that existing technology decomposition mixed pixel of hyper-spectral image generally is based on various operating system designs is finished, and its mainly is fit to handle afterwards, can not finish real-time decomposition mixed pixel of hyper-spectral image.

Summary of the invention

In order to address the above problem, the purpose of this invention is to provide a kind of high spectrum image process chip based on FPGA, computer technology, digital image processing techniques are combined with modern FPGA technology, can realize the high speed of high spectrum image data, processing in real time.And can according to different needs formulate different IP kernel hardware be easy to the upgrading, to satisfy the needs of following multiple function, to realize better more function, the raising cost performance reduces cost.

The present invention solves the technical scheme that its technical matters takes:

A kind ofly design the method that mixed pixel of hyper-spectral image decomposes chip in real time, it is characterized in that finishing the design that mixed pixel of hyper-spectral image decomposes chip in real time based on SoC, the concrete steps of this design are as follows:

(I) high spectrum mixed pixel decomposition method is determined;

(II) it is definite that mixed pixel of hyper-spectral image decomposes the chip design parameter in real time;

(III) mixed pixel of hyper-spectral image decomposes the chip system design in real time;

(IV) mixed pixel of hyper-spectral image decomposes the chip design software programming in real time;

(V) mixed pixel of hyper-spectral image decomposes chip design emulation in real time;

(VI) mixed pixel of hyper-spectral image decomposes the FPGA realization of chip in real time.

Its feature is that also above-mentioned (I) determined to finish the best approach that mixed pixel decomposes based on SOC (system on a chip) (SoC), (II) provided the various parameters that mixed pixel of hyper-spectral image decomposes chip design in real time, (III), (IV), (V) adopts Very High Speed Integrated Circuit (VHSIC) hardware description language to finish the design of chip, (VI) finished the realization that mixed pixel of hyper-spectral image decomposes chip in real time based on programmable gate array, chip design software is made up of five kinds of modules, they are that (1) data are read in module, (2) matrix auto-correlation computing module, (3) Singular Value Decomposition Using module, (4) matrix pseudoinverse computing module, (5) the end member module is decomposed in the pixel projection, and chip adopts the hierarchical structure method for designing of top-down (Top-Down).

Described a kind of method that mixed pixel of hyper-spectral image decomposes chip in real time that designs is characterized in that having provided mixed pixel of hyper-spectral image and decomposes the chip design parameters optimization in real time.

Described a kind of method that mixed pixel of hyper-spectral image decomposes chip in real time that designs is characterized in that adopting programmable gate array to finish mixed pixel of hyper-spectral image and decomposes chip design in real time.

Described a kind of method that mixed pixel of hyper-spectral image decomposes chip in real time that designs, the control that its feature is read in data realizes by following steps:

1) earlier to data reception block transfer commencing signal;

2) data are gone into module and are taked two RAM to coordinate to receive data, and the data of a RAM are given next module, and another RAM receives data;

3) intact pixel data of every biography, the duty transposing of two RAM, and produce an enabling signal to next module;

4) passed when all data, sent termination signal to chip.

Described a kind of method that mixed pixel of hyper-spectral image decomposes chip in real time that designs is characterized in that the calculating of matrix auto-correlation realizes by following steps:

1) receives and to start after data are read in the signal of module;

2) data are converted to single-precision floating point type data by fixed point;

3) 32 parallel multiplication concurrent workings of calling module, the result deposits in the register;

4) after the calculating of matrix auto-correlation is finished, send enabling signal and transmit data to the Singular Value Decomposition Using module.

Described a kind of method that mixed pixel of hyper-spectral image decomposes chip in real time that designs is characterized in that the precision of system adopts the floating type data type.

Described a kind of method that mixed pixel of hyper-spectral image decomposes chip in real time that designs, the design software that it is characterized in that the impact signal process chip adopts modular design, comprises that specifically (1) data read in module, (2) matrix auto-correlation computing module, (3) Singular Value Decomposition Using module, (4) matrix pseudoinverse computing module, (5) pixel projection and decompose the end member module.It is characterized in that:, finish the real-time decomposition of mixed pixel of hyper-spectral image by module combinations.

A kind of mixed pixel of hyper-spectral image decomposes chip in real time, it is characterized in that using arbitrary method acquisition among the claim 1-7, comprising: the module combinations of top-down hierarchical structure.

Owing to adopted above technical scheme, the beneficial effect that the present invention had is:

1. finish the high spectrum image data in real time based on SOC (system on a chip) (SOC) and handle, for the real-time resolving device of mixed pixel of hyper-spectral image that designs low-power consumption, miniaturization provides condition;

2. the employing on-site programmable gate array FPGA is finished mixed pixel of hyper-spectral image and is decomposed chip design in real time, and the construction cycle is short, design cost is low, and the research and development risk is little;

3. adopt single-precision floating point type data computation, the computational accuracy height, error calculated is little;

4. adopt Jacobi reach a standard method computation of characteristic values and proper vector, fast convergence rate is convenient to the parallelization design;

5. adopt line production, parallel processing, can be to high latitude, high data volume high spectrum image is handled in real time, finishes mixed pixel of hyper-spectral image and decomposes in real time.

Description of drawings

Below in conjunction with accompanying drawing and subordinate list the specific embodiment of the present invention is described in further detail.

Fig. 1 VCA algorithm flow chart;

Fig. 2 (a) adopts double precision datum type policy result for system;

Fig. 2 (b) adopts single precision data type policy result for system;

Fig. 3 reads in the modular design frame diagram for data;

Fig. 4 is for calculating auto-correlation module frame figure;

Fig. 5 is for calculating SVD operator frame diagram;

Fig. 6 is for calculating SVD operator frame diagram;

Fig. 7 asks end member module frame figure for calculating projection;

Embodiment

Fig. 1 has provided vertex component analysis algorithm (VCA) and has finished the key step that mixed pixel of hyper-spectral image decomposes:

1) the known observation spectrum matrix R=[r that forms by single pixel vector ₁, r ₂..., r _N], N is a pixel number in the image, at first uses svd (SVD) to observation spectrum matrix dimensionality reduction, transforms to the q n-dimensional subspace n, as follows formula

$X=U_q^{T}R---\left(1\right)$

Wherein, U _qPreceding q the matrix that vector is formed by the left transformation matrix of SVD.

2) X is projected to obtain monomer S on the lineoid _q:

${\left[Y\right]}_{:,j}={\left[X\right]}_{:,j}/\left({\left[X\right]}_{:,j}^{T}u\right)---\left(2\right)$

Wherein, u=mean (X), u are the vectors of 1 * d.

3) an initial given direction f:

f＝((I-AA ^#)w)/(‖(I-AA ^#)w‖) (3)

Wherein, A=[e _u| 0| ... | 0], A is p * p matrix, is used for storing the projection of estimating the end member signal, e _u=[0 ..., 0,1] ^TBe vector of unit length; W=randn (0, I _p), w is a zero-mean random Gaussian vector, covariance is I _pF is orthogonal to by [A] _{:, 1:i}The vector of the subspace of opening.

4) data projection on the lineoid that (2) formula is obtained arrives on the given direction of (3) formula, obtains following formula:

v＝f ^TY (4)

5) the pixel position of the extreme value correspondence of this projection can be tried to achieve by following formula:

k＝argmax _{j＝1，…，N}‖[v] _:，j‖ (5)

6) result of (5) formula is stored promptly store pixel index [indice] _i=k.

7) result with (5) formula asks for next projecting direction.

[A] _:，i＝[Y] _:，k (6)

8) bring (6) formula into (3) formula, repeat (4) and (5) formula computing, whenever repeat once, produce the space that row that a vector f is orthogonal to standby matrix A are opened at random, and y is projected on the f, just can obtain pixel position corresponding to extreme value.At last, try to achieve the curve of spectrum of end member with following formula:

$\hat{M}=U_d{\left[X\right]}_{:,\mathrm{indice}}---\left(7\right)$

Be the image size with m * n in the table 1, l is the wave band number, and p is the background spectrum characteristic number of choosing, and d is Jacobi's number of revolutions, and k is the number of comparisons when asking eigenwert.The required calculation times of auto-correlation module in the algorithm is maximum as can be seen from Table 1, is the key component in the total system, need be designed to a module separately; Contrary two the required operation times of part of Singular Value Decomposition Using and compute matrix can be designed to the submodule executed in parallel respectively at the same order of magnitude; The required operation times of other parts is less, can be integrated into projection and ask the end member sequence of modules to carry out, to save resource and to increase work efficiency.

System's operational precision.The curve of spectrum that Fig. 2 has provided with known three materials is an experiment condition according to the synthetic emulated data of linear mixed model, set the result that different accuracy extracts mixed pixel, the black line is represented the curve of spectrum of known three kinds of materials, and red line is represented the curve of spectrum of three kinds of materials decomposing out by algorithm.As can be seen from the figure, single-precision number certificate and double precision datum are to extracting the end member data well, so select to help the precision of the floating type data of hard-wired single precision as system here.

Fig. 3 has provided the frame diagram of data read module, considers that the high-spectral data amount is big, the characteristics of data dispatch complexity, here data read separately as a module, realize first RAM read data when state machine is 1, second RAM write data by two RAM collaborative works of state machine control; When state machine is 0, first RAM write data, second RAM read data.

It is maximum to calculate the needed calculation times of auto-correlation module, is the key link that influences system real time.Here need to introduce parallel processing mechanism, call the computing simultaneously of a plurality of parallel multiplications.

Hyperspectral imager produces 12 fixed-point datas, and transmission speed is 400Mbps, and the data of then transmitting m * n * l need the time $T_{}$ ${}_1=m\&times;n\&times;l\&times;\frac{12}{400\&times;{10}^6}s;$ Suppose to have c multiplier, operate under the clock of 200M, calculating auto-correlation needs the time $T_{}$ ${}_2=m\&times;n\&times;{\mathrm{<figure-callout\; id="2"\; label="l"\; filenames="HA20182653200810187804101E00011.png,HA20182653200810187804101E00012.png"\; state="\{\{state\}\}">l</figure-callout>}}^2\&times;\frac{1}{200\&times;{10}^6}\&times;\frac{1}{c}s.$ Work as T ₂≤ T ₁, module can requirement of real time, and abbreviation can get $c\&GreaterEqual;\frac{1}{6},$ Wherein, l=128 is the wave band number.Consider the complexity and the portability of program design, choose c=32, promptly call 32 multiplier concurrent workings.Fig. 4 has provided the frame diagram that calculates the auto-correlation module, and this module has the special address generator of data read module to come being transported in 32 multipliers of control data.

Fig. 5 has provided Singular Value Decomposition Using module frame figure, and controller module is responsible for detecting enabling signal, management data storer, is received from the correlation matrix data, the controlling sub execution sequence; Three function sub-modules are realized function separately, the mode that the inner main employing of submodule is carried out in proper order; Owing to also be that order is carried out between three submodules,, saved the SRAM resource of FPGA inside so only need a data storer to deposit results of intermediate calculations.

The pseudo-algorithm for inversion of matrix is as follows:

If matrix $A\&Element;C_r^{m\&times;n},B_i\&Element;C^{n\&times;n},{\mathrm{\&delta;}}_i\&Element;C(i=0,\&CenterDot;\&CenterDot;\&CenterDot;,r),$ Public B ₀=O δ ₀=1

B _k+1＝δ _kI-A ^TAB _k，k＝0，…，r-1 (8)

δ _k+1＝tr(A ^TAB _k+1)/(k+1)，k＝0，…，r-1 (9)

$A^{+}=\frac{B_r{A}^T}{{\mathrm{\&delta;}}_r}---\left(10\right)$

A in the formula (10) ⁺It is the pseudoinverse of matrix A

Compute matrix pseudoinverse module adopts parallel computation, and by the conveying of controller control data, compute matrix multiplication and order are parallel carries out, and Fig. 6 has provided the design framework figure of compute matrix pseudoinverse.

The projection algorithm that calculates pixel is fairly simple, and calculated amount is little, adopts the serial row calculation mode can requirement of real time, and the order execution pattern as shown in Figure 7.

Mixed pixel of hyper-spectral image decomposes chip in real time and selects for use the FPGA master slice of the production of Xilinx company, Vertix5 to finish.Mixed pixel of hyper-spectral image decomposes the behavioral scaling emulation of chip in real time and adopts the Active-VHDL software of U.S. Active company exploitation to finish, comprehensive, mapping, the layout of impact signal process chip, connect up and have the post-simulation (Post Simulation) of time delay, adopt the Xilinx Fundation of company FPGA (Field Programmable Gate Array) design software to finish.

The required calculation times of each major part of table 1 algorithm

The algorithm major part	Multiplication	Add (subtracting) method	Relatively	Other	Amount to
						Auto-correlation	m×n×l 2	(m×n-1)×l 2	0	0	2m×n×l 2≈8.5×10 9
Svd	12×l×d	6×l×d	k	20×d	18×l×d+k≈9.2×10 7
						Pseudo inverse matrix	m×d×l 2	(m×d-1)×l 2	0	0	2m×d×l 2≈3.1×10 9
Calculate projection	m×n×l	0	m×n×l	0	2m×n×l≈3.4×10 5

Claims (1)

1. the method for designing of a high-spectrum image dimensionality reduction chip is finished the design of high-spectrum image dimensionality reduction chip based on SoC, and the concrete steps of high-spectrum image dimensionality reduction chip design are as follows:

(I) the high-spectrum image dimensionality reduction algorithm is determined;

(II) the high-spectrum image dimensionality reduction chip design parameter is determined;

(III) high-spectrum image dimensionality reduction chip system design;

(IV) the high-spectrum image dimensionality reduction chip design software is write;

(V) high-spectrum image dimensionality reduction chip design and simulation;

(VI) FPGA of high-spectrum image dimensionality reduction chip realizes;

It is characterized in that: above-mentioned (I) adopts singular value decomposition algorithm, and choose Jacobi's method of reaching a standard and ask proper value of matrix and proper vector, (II) provides the various parameters of high-spectrum image dimensionality reduction chip design, wherein choose single-precision floating point type data and carry out data processing, single-precision floating point type data are made up of 8 exponential parts and 24 fraction parts, be accurate to the 6-7 position effective digital, (III), (IV), (V) adopts VHDL language to finish the design of chip, (VI) finishes the realization of high-spectrum image dimensionality reduction chip based on field programmable gate array, chip design software is made up of five modules, they are system control module (1), auto-correlation module (2), eigenwert is found the solution module (3), eigenwert extraction module (4), dimensionality reduction is realized module (5), wherein system control module is controlled the entire chip system, signal contact in the coordination chip between other each intermodular data transmission and each module makes them can both accurately carry out the work of module separately; The auto-correlation module receives the high spectrum image data and its data matrix is carried out auto-correlation computation, and the auto-correlation computation result data type conversion that obtains is found the solution module by eigenwert is required type; Eigenwert is found the solution eigenwert and the proper vector that module is found the solution the autocorrelation matrix matrix of consequence that the auto-correlation module obtains; The eigenwert extraction module is found the solution the eigenwert that module obtains to eigenwert and is sorted, and extracts to comprise the top n eigenwert characteristic of correspondence vector that contains much information, and forms and comprises the big N of an amount of image information eigenvectors matrix; Dimensionality reduction realizes that module multiplies each other the eigenvectors matrix that original high spectrum image matrix and eigenwert extraction matrix obtain, and obtains the image array behind the dimensionality reduction; Chip adopts top-down hierarchical structure method for designing, and this hierarchical structure comprises top-level module and bottom module.

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