CN101800221B - Semiconductor device - Google Patents
Semiconductor device Download PDFInfo
- Publication number
- CN101800221B CN101800221B CN201010119101.2A CN201010119101A CN101800221B CN 101800221 B CN101800221 B CN 101800221B CN 201010119101 A CN201010119101 A CN 201010119101A CN 101800221 B CN101800221 B CN 101800221B
- Authority
- CN
- China
- Prior art keywords
- metal part
- dielectric film
- metal
- resistor
- multiple resistors
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 42
- 229910052751 metal Inorganic materials 0.000 claims abstract description 101
- 239000002184 metal Substances 0.000 claims abstract description 101
- 239000012535 impurity Substances 0.000 claims abstract description 40
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 34
- 229920005591 polysilicon Polymers 0.000 claims description 32
- 239000000758 substrate Substances 0.000 claims description 13
- 230000008878 coupling Effects 0.000 claims description 4
- 238000010168 coupling process Methods 0.000 claims description 4
- 238000005859 coupling reaction Methods 0.000 claims description 4
- 238000009966 trimming Methods 0.000 claims description 4
- 230000005611 electricity Effects 0.000 claims 3
- 238000003698 laser cutting Methods 0.000 claims 1
- 238000000034 method Methods 0.000 abstract description 13
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 8
- 229910052739 hydrogen Inorganic materials 0.000 description 8
- 239000001257 hydrogen Substances 0.000 description 8
- 238000004519 manufacturing process Methods 0.000 description 8
- 239000013078 crystal Substances 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- 239000010410 layer Substances 0.000 description 3
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 238000002347 injection Methods 0.000 description 2
- 239000007924 injection Substances 0.000 description 2
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 229910000838 Al alloy Inorganic materials 0.000 description 1
- GDFCWFBWQUEQIJ-UHFFFAOYSA-N [B].[P] Chemical compound [B].[P] GDFCWFBWQUEQIJ-UHFFFAOYSA-N 0.000 description 1
- 229910021529 ammonia Inorganic materials 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 239000002800 charge carrier Substances 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000000280 densification Methods 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 239000012299 nitrogen atmosphere Substances 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 239000005368 silicate glass Substances 0.000 description 1
- 238000005245 sintering Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/0802—Resistors only
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/20—Resistors
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Semiconductor Integrated Circuits (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
Abstract
Provided is a method which is capable of producing polycrystalline silicon resistors with a high ratio accuracy so that a precision resistor circuit may be designed. A semiconductor device has a structure in which an occupation area of a metal portion covering a low concentration impurity region constituting each of the polycrystalline silicon resistors is adjusted so that ratio accuracy may be further corrected after a resistance is corrected.
Description
Technical field
The present invention relates to the to have bleeder resistor semiconductor device of (bleeder resistor), the resistor that this bleeder resistor is formed by polysilicon forms.
Background technology
In semiconductor integrated circuit, use diffused resistor or polyresistor.Diffused resistor is made up of monocrystalline silicon Semiconductor substrate (being injected into wherein with the impurity of the conduction type of the conductivity type opposite of this Semiconductor substrate).Polyresistor is by Impurity injection polysilicon is wherein formed.Polyresistor there is especially little leakage current due to the dielectric film around resistor and the high resistance that caused by the defect existing at crystal boundary aspect advantage, cause being widely used in semiconductor integrated circuit.
Fig. 3 A and 3B are respectively schematic plan view and the signal cross-sectional view of conventional polyresistor circuit.Polyresistor is by deposition (similar by low-pressure chemical vapor deposition (LPCVD) or its), the polysilicon membrane on dielectric film injects p-type or N-shaped impurity, and then processing gains by photoetching technique is that resistor shape produces.Carry out Impurity injection for determining the resistance of polyresistor.Depend on the resistance of expectation, the concentration of the p-type that inject or N-shaped impurity is 1 × 10
17/ cm
3to 1 × 10
20/ cm
3in scope, change.In addition, the each end formation contact hole on resistor both sides and metal line are to obtain its electromotive force.Between the metal wiring layer of end and polysilicon, satisfied ohmic contact requires that Selective implantation is equal to or greater than 1 × 10 by using patterning photoresistance
20/ cm
3the impurity of high concentration enter in the polysilicon segment corresponding to resistor end.
To using the resistor structure of polysilicon, as illustrated in the schematic plan view of Fig. 3 A and the schematic section of Fig. 3 B, in order to comprise the polysilicon 103 made from low concentration impurity district 104 and high concentration impurities district 105, on its dielectric film 102 in Semiconductor substrate 101, form.Electromotive force obtains from metal line 107 by the contact hole 106 forming above high concentration impurities district 105.
In addition, as illustrated in Fig. 3 B, metal is placed on the polysilicon 103 made from low concentration impurity district 104 and high concentration impurities district 105 mentioned above to prevent that hydrogen (it affects the resistance of polysilicon) from diffusing into polysilicon in semiconductor technology.Polysilicon forms by having the crystal grain of relative high-crystallinity and the crystal boundary of intergranule (having low-crystallinity, i.e. high level density).The electronics that the resistance of polyresistor is mainly caught by a large amount of energy levels that existed by crystal boundary or hole (it serves as charge carrier) determine.But in the time having the hydrogen of high diffusion coefficient and produce, hydrogen easily arrives polysilicon and can be caught by energy level, thereby change resistance in semiconductor fabrication process.Sintering step after hydrogen produces the example of technique and is included in metal electrode and forms in nitrogen atmosphere and use the plasma nitride film of ammonia to form step.The resistance that can suppress polysilicon with metal wiring layer covering polyresistor is because hydrogen spreads the variation causing.
The method that is used for the resistance of stablizing polysilicon is open at for example JP2002-076281A.
But, there is following point for the method for the resistance of stablizing polysilicon., in semiconductor fabrication process, exist the metal on polysilicon to be subject to the problem that other factor except hydrogen (it affects polysilicon) (charged (charging), the heat, the stress etc. that for example cause due to plasma) affects.These factors affect polysilicon by the metal on it, cause the variation of resistance.
In addition, resistance can change due to the difference between the electromotive force of the metal providing above and the electromotive force of the resistor providing below.Can imagine, because by using the resistor being formed by the polysilicon that wherein injects a large amount of impurity, in electromotive force official post polyresistor mentioned above, impurity concentration changes.Therefore the method that the metal part, providing from above obtains electromotive force also affects the variation of resistance.
Such as, in the circuit (circuit of voltage detector or voltage adjuster etc.) of use bleeder resistor, output current/magnitude of voltage is determined by the ratio of bleeder resistor.But even in the time that resistance changes slightly, the resistance ratio accuracy of resistor group reduces, and therefore may not obtain the desired value of output current/magnitude of voltage.This causes the productive rate reducing, and is so especially in the case of the product of claimed accuracy.
Summary of the invention
Make the present invention to solve problem mentioned above, and therefore the object of this invention is to provide the method having than the polyresistor of the accuracy more at high proportion that can be realized by conventional method for realizing.
In order to solve problem mentioned above, the present invention adopts following means.
First, provide the semiconductor device that comprises resistor, it comprises: Semiconductor substrate; The first dielectric film forming in Semiconductor substrate; Have multiple resistors of same shape, they form and are formed by the polysilicon that comprises low concentration impurity district and high concentration impurities district on the first dielectric film; The second dielectric film forming on multiple resistors; Through the film formed contact hole of the second insulation of top, high concentration impurities district; Be connected to contact hole and connect the first metal line of multiple resistors of being formed by polysilicon; Be arranged on the second dielectric film to cover the second metal part in the low concentration impurity district in resistor group one of (comprise in single resistor and interconnected at least two resistors).
In addition, some fuses that form between resistor groups and resistor that semiconductor device has in resistor are wherein tailored into the structure that obtains desired value.
In addition, semiconductor device has the structure that wherein the second metal part can change by fine setting (trimming) on area.
According to the present invention, by revising the resistance ratio in semiconductor device, it is possible that manufacture has the more polyresistor of steady resistance ratio.By adopting resistor circuit of the present invention, providing, to have the bleeder resistor of accuracy be at high proportion possible, because depend on the structure of resistor circuit, the value based on being obtained by the first fine setting is further carried out fine setting.
Brief description of the drawings
In the accompanying drawings:
Figure 1A is that diagram is according to the schematic plan view of the semiconductor device of first embodiment of the invention;
Figure 1B is that diagram is according to the schematic section of the semiconductor device of first embodiment of the invention;
Fig. 2 is according to the schematic plan view of the semiconductor device of second embodiment of the invention;
Fig. 3 A is the schematic plan view of conventional polyresistor circuit;
Fig. 3 B is the schematic section of conventional polyresistor circuit; And
Fig. 4 is the chart of the relation between the surface area of the second metal part of diagram resistance ratio and resistor.
Embodiment
Now, embodiment of the invention will be described with reference to drawings.
Figure 1A and 1B are respectively according to the schematic plan view of the semiconductor device of the first embodiment of the present invention and schematic section.Under in regular situation, resistor group is formed by polysilicon 103, on first dielectric film 102 of polysilicon 103 in Semiconductor substrate 101, form and comprise low concentration impurity district 104 and the high concentration impurities district 105 at the two ends in this low concentration impurity district 104, and electromotive force obtains from the metal line 107 that comprises the first metal part 108 by contact hole 106, contact hole 106 forms through the second dielectric film 120 of 105 tops, high concentration impurities district.In addition, polysilicon 103 is covered by the second metal part 109.The 3rd metal part 110 is arranged to connect adjacent to the second metal part and by the fuse for finely tuning.The second metal part-structure is to be connected to the fuse (it is formed by polysilicon) for finely tuning, polyresistor and the first metal part are connected to this fuse, and the area of the metal part with same potential can be changed with the part or the 3rd the whole of metal part that separate the 3rd metal part by cutting off fuse.This is connected in Figure 1A and illustrates.In this case, the second metal part 109 that only covers a cell resistance device is not connected to other parts or substrate.The resistance proportional jitter that the invention is intended to revise by the area in increase as described below or minimizing low concentration impurity district resistor, this resistance proportional jitter is by causing with routine techniques layout semiconductor device.
As what mention in the explanation of routine techniques, the example that affects the factor of metal during semiconductor fabrication process comprises following factors.
,, in semiconductor fabrication process, the metal on polysilicon is subject to other factor except hydrogen (it affects polysilicon) (charged, hot, the stress for example causing due to plasma etc.) impact.Therefore, these factors affect polysilicon by the metal on it, cause the variation of resistance.Above-described factor is with the area change of top (i.e. the second metal part).Thereby, find that resistance is because the area of the second metal part changes.
Fig. 4 is that the resistance of diagram hypothesis polyresistor is set to 1, ratio (resistance ratio) fixed chart with the area of the second metal part.There is proportional relation from obvious visible second area of metal part of Fig. 4 and the resistance of polyresistor.Therefore, the increase of the second metal part area can increase resistance.
The present invention utilizes relation mentioned above, and has the feature of the area correction resistance by changing the second metal part.This carries out after resistance correction mentioned above.This is can not provide the resistance of expectation and value departs from the means to save the situation of expecting resistance in correction mentioned above.Therefore, thus the value based on obtaining by the first fine setting further finely tune to provide and there is the bleeder resistor of accuracy at high proportion.
Can understand the area change 50 μ m when the second metal part from Fig. 4
2time, resistance ratio increases by 1%.Based on this fact, the increase of area is considered to enter and generate layout.
For example, as illustrated in Figure 1A, the second metal part is placed on polyresistor (each low concentration impurity district and high concentration impurities district of comprising) top to cover resistor group completely.This layout has and during heating treatment prevents that hydrogen from diffusing into the effect of polyresistor, and heat treatment is for example to manufacture densification steps in the interlayer film being formed by boron phosphorus silicate glass (BPSG) or its analog or in the metal annealing (it is to carry out after the step of manufacture polyresistor) of manufacturing in metal wiring layer.The second metal part 109 is connected to the 3rd metal part 110 for adjusting area.This connection is by the fuse 111 for finely tuning being formed by polysilicon.Note when the 3rd metal part 110 formed by the material identical with the second metal part 109 and preferably when for example aluminium alloy forms step simpler.
As illustrated in Figure 1A, provide multiple the 3rd metal parts 110, and these the 3rd metal parts 110 are by being connected to each other for the fuse of finely tuning.Be connected to if desired the fuse 111 for finely tuning of these the 3rd metal parts 110 by cut-out, thereby these metal parts are separated and are changed area to obtain the resistance ratio of expecting.In Figure 1A, two the 3rd metal parts 110 are set.But, when the area occupied of single the 3rd metal part 110 reduces and when the quantity of the 3rd metal part 110 increases, can carry out meticulousr adjustment.
Fig. 2 illustrates the schematic plan view of semiconductor device according to a second embodiment of the present invention.Fig. 2 is different from Figure 1A aspect these the 3rd metal parts of connection.Particularly, as contrary in the fuse using in the first embodiment, these the 3rd metal parts 110 are connected to the second metal part 109 and are connected to each other by metal portion coupling part 112, and metal portion coupling part 112 is formed by the material identical with the 3rd metal part in a second embodiment.Pass through if desired to cut off metal portion coupling part 112 with laser or its analog, thereby metal part can change the resistance ratio of expecting to obtain on area.
Described above, resistance ratio can be by being connected to the 3rd metal part by the second metal part so that variable area is adjusted.
Claims (9)
1. a semiconductor device, comprising:
Semiconductor substrate;
The first dielectric film forming in Semiconductor substrate;
Have multiple resistors of same shape, it is arranged on described the first dielectric film and is formed by polysilicon, and each in wherein said multiple resistors has low concentration impurity district and the high concentration impurities district at two ends, described low concentration impurity district;
The second dielectric film forming on described multiple resistors;
The contact hole forming through the second dielectric film in described high concentration impurities district;
That formed by metal wiring layer and connect the first metal part of described multiple resistors by described contact hole;
Be arranged on described the second dielectric film to cover the second metal part in the described low concentration impurity district of resistor group, described resistor group comprise more than two interconnected resistor of selecting from described multiple resistors and single resistor one of them; And
The 3rd metal part of the area for increasing described the second metal part providing adjacent to described the second metal part, described the 3rd metal part can separate with described the second metal part electricity,
Wherein said the second metal part is connected by fuse with described the 3rd metal part.
2. semiconductor device as claimed in claim 1, the area of wherein said the second metal part can reduce by laser trimming.
3. semiconductor device as claimed in claim 1, wherein said the second metal part and described the 3rd metal part are formed by metal wiring layer.
4. a semiconductor device, comprising:
Semiconductor substrate;
The first dielectric film forming in Semiconductor substrate;
Have multiple resistors of same shape, it is arranged on described the first dielectric film and is formed by polysilicon, and each in wherein said multiple resistors has low concentration impurity district and the high concentration impurities district at two ends, described low concentration impurity district;
The second dielectric film forming on described multiple resistors;
The contact hole forming through the second dielectric film in described high concentration impurities district;
That formed by metal wiring layer and connect the first metal part of described multiple resistors by described contact hole;
Be arranged on described the second dielectric film to cover the second metal part in the described low concentration impurity district of resistor group, described resistor group comprise more than two interconnected resistor of selecting from described multiple resistors and single resistor one of them; And
The 3rd metal part of the area for increasing described the second metal part providing adjacent to described the second metal part, described the 3rd metal part can separate with described the second metal part electricity,
Wherein said the second metal part with described the 3rd metal part by being connected by the metal coupling part of laser cutting.
5. semiconductor device as claimed in claim 4, the area of wherein said the second metal part can reduce by laser trimming.
6. semiconductor device as claimed in claim 4, wherein said the second metal part and described the 3rd metal part are formed by metal wiring layer.
7. a semiconductor device, comprising:
Semiconductor substrate;
The first dielectric film forming in Semiconductor substrate;
Have multiple resistors of same shape, it is arranged on described the first dielectric film and is formed by polysilicon, and each in wherein said multiple resistors has low concentration impurity district and the high concentration impurities district at two ends, described low concentration impurity district;
The second dielectric film forming on described multiple resistors;
The contact hole forming through the second dielectric film in described high concentration impurities district;
That formed by metal wiring layer and connect the first metal part of described multiple resistors by described contact hole;
Be arranged on described the second dielectric film to cover the second metal part in the whole described low concentration impurity district of resistor group, described resistor group comprise more than two interconnected resistor of selecting from described multiple resistors and single resistor one of them; And
The 3rd metal part of the area for increasing described the second metal part providing adjacent to described the second metal part, described the 3rd metal part can separate with described the second metal part electricity.
8. semiconductor device as claimed in claim 7, the area of wherein said the second metal part can reduce by laser trimming.
9. semiconductor device as claimed in claim 7, wherein said the second metal part and described the 3rd metal part are formed by metal wiring layer.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2009-026503 | 2009-02-06 | ||
| JP2009026503A JP2010182954A (en) | 2009-02-06 | 2009-02-06 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN101800221A CN101800221A (en) | 2010-08-11 |
| CN101800221B true CN101800221B (en) | 2014-11-26 |
Family
ID=42539729
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201010119101.2A Expired - Fee Related CN101800221B (en) | 2009-02-06 | 2010-02-03 | Semiconductor device |
Country Status (3)
| Country | Link |
|---|---|
| US (1) | US8242580B2 (en) |
| JP (1) | JP2010182954A (en) |
| CN (1) | CN101800221B (en) |
Families Citing this family (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2010035608A1 (en) * | 2008-09-25 | 2010-04-01 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and manufacturing method thereof |
| JP5568334B2 (en) * | 2010-02-24 | 2014-08-06 | ラピスセミコンダクタ株式会社 | Semiconductor device and manufacturing method thereof |
| US9478359B2 (en) * | 2013-12-10 | 2016-10-25 | Analog Devices Global | Phase corrector for laser trimming, an integrated circuit including such a phase corrector, and a method of providing phase correction in an integrated circuit |
| JP6267987B2 (en) * | 2014-02-13 | 2018-01-24 | エスアイアイ・セミコンダクタ株式会社 | Semiconductor device |
| JP6222002B2 (en) * | 2014-08-22 | 2017-11-01 | トヨタ自動車株式会社 | Current interrupt device |
| JP6586152B2 (en) * | 2017-12-22 | 2019-10-02 | エイブリック株式会社 | Semiconductor device |
| JP7045271B2 (en) * | 2018-06-28 | 2022-03-31 | エイブリック株式会社 | Semiconductor devices and semiconductor chips |
| US11545480B2 (en) * | 2018-06-29 | 2023-01-03 | Texas Instruments Incorporated | Integrated circuit with single level routing |
Family Cites Families (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2002076281A (en) | 2000-08-30 | 2002-03-15 | Seiko Instruments Inc | Semiconductor device and method of manufacturing the same |
| JP2003282716A (en) * | 2002-03-25 | 2003-10-03 | Nec Microsystems Ltd | Semiconductor device |
| JP4723827B2 (en) * | 2004-08-04 | 2011-07-13 | セイコーインスツル株式会社 | Resistance circuit |
| JP4811988B2 (en) * | 2005-03-23 | 2011-11-09 | セイコーインスツル株式会社 | Semiconductor device |
| US7403094B2 (en) * | 2005-04-11 | 2008-07-22 | Texas Instruments Incorporated | Thin film resistor and dummy fill structure and method to improve stability and reduce self-heating |
| JP4880939B2 (en) * | 2005-07-29 | 2012-02-22 | セイコーインスツル株式会社 | Semiconductor device |
-
2009
- 2009-02-06 JP JP2009026503A patent/JP2010182954A/en not_active Withdrawn
-
2010
- 2010-02-03 CN CN201010119101.2A patent/CN101800221B/en not_active Expired - Fee Related
- 2010-02-04 US US12/700,124 patent/US8242580B2/en active Active
Also Published As
| Publication number | Publication date |
|---|---|
| US20100200952A1 (en) | 2010-08-12 |
| US8242580B2 (en) | 2012-08-14 |
| CN101800221A (en) | 2010-08-11 |
| JP2010182954A (en) | 2010-08-19 |
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Effective date of registration: 20160323 Address after: Chiba County, Japan Patentee after: SEIKO INSTR INC Address before: Chiba, Chiba, Japan Patentee before: Seiko Instruments Inc. |
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Granted publication date: 20141126 Termination date: 20210203 |