CN101800184A - Packaging base plate with cave structure and manufacture method thereof - Google Patents
Packaging base plate with cave structure and manufacture method thereof Download PDFInfo
- Publication number
- CN101800184A CN101800184A CN200910007058A CN200910007058A CN101800184A CN 101800184 A CN101800184 A CN 101800184A CN 200910007058 A CN200910007058 A CN 200910007058A CN 200910007058 A CN200910007058 A CN 200910007058A CN 101800184 A CN101800184 A CN 101800184A
- Authority
- CN
- China
- Prior art keywords
- patterned circuit
- metal
- layer
- insulating barrier
- base plate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1515—Shape
- H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
- H01L2924/1533—Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate
- H01L2924/15331—Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate being a ball array, e.g. BGA
Landscapes
- Production Of Multi-Layered Print Wiring Board (AREA)
Abstract
The invention discloses a packaging base plate with a cave structure and a manufacture method thereof. The manufacture method of the packaging base plate comprises a coating plate, wherein the coating plate comprises a first metal layer, a second metal layer and a middle layer, and the middle layer is arranged between the first metal layer and the second metal layer; part of the first metal layer is etched to expose part of the middle layer and is provided with a metal block; the coating plate and a first copper foil base plate are pressed, and the first copper foil base plate comprises a first insulating layer and a first copper foil layer; the first copper foil layer is subjected to line patterning to form a first patterned line; the second metal layer is subjected to line patterning to form a second patterned line; the metal block is removed to form the cave structure; and the middle layer positioned in the cave structure is removed.
Description
Technical field
The present invention relates to a kind of base plate for packaging and preparation method thereof, particularly relate to base plate for packaging of a kind of tool cave structure and preparation method thereof.
Background technology
In recent years, the fast development of 3 D stereo (3D) structure dress, remove and significantly to dwindle memory shared area on circuit board, promote simultaneously outside the service efficiency after electronic product dwindles, more the chip of difference in functionality can be incorporated into same structure dress module, reach system in package (System in Package, high benefit SiP).Wherein, stacked encapsulating structure (PoP) promptly belongs to a type of 3 D stereo structure dress, and for instance, stacked encapsulating structure can see through the memory of high power capacity and complicated processor are combined, and reduces the circuit board space of high-order mobile phone significantly.
What Fig. 1 illustrated is the cross-sectional view of traditional stacked encapsulating structure.As shown in Figure 1, traditional stacked encapsulating structure 1 includes first packaging body 2 and is layered in second packaging body 3 on first packaging body 2.First packaging body 2 comprises that first chip, 20, the first chips of being located on first substrate 22 20 by wire bonds (bond wire) 26, as gold thread, constitute electric connection with first substrate 22, and first chip 20 is enveloped by moulding material 24 with wire bonds 26.Second packaging body 3 comprises that second chip, 30, the second chips of being located on second substrate 32 30 constitute electric connection by the wire bonds 36 and second substrate 32, and first chip 30 is enveloped by moulding material 34 equally with wire bonds 36.Second substrate 32 of second packaging body 3 constitutes electric connection by first substrate 22 of the tin ball 40 and first packaging body 2, usually, can insert primer 42 between first substrate 22 and second substrate 32, in order to avoid tin ball 40 is subjected to outside destroy.
The stacked encapsulating structure of above-mentioned tradition comprises following shortcoming at least: the distance of the limited size of (1) tin ball 40 between first substrate 22 and second substrate 32.The height of tin ball 40 must surpass the height of moulding material 24, to guarantee the electric connection between first substrate 22 and second substrate 32, thereby can't further dwindle the tin ball-joint apart from (pitch), cause the number of tin ball 40 and output input pin (I/O) number to be difficult to promote; (2) first substrates 22 are different with the thermal coefficient of expansion (CTE) of second substrate 32 to cause tin ball 40 may be subjected in various degree stress, has influence on the reliability of packaging body; (3) control of the coplanarity of tin ball 40 is difficult for, and makes that the Yu Yudu (process window) of packaging technology is less; (4) need additionally carry out encapsulating step between first substrate 22 and second substrate 32; (5) it is bigger to pile up volume.
Summary of the invention
Main purpose of the present invention is providing a kind of base plate for packaging of improvement, stacked packaging body and preparation method thereof, to solve and to overcome disadvantages of background technology and shortcoming.
According to a preferred embodiment of the invention, the invention provides a kind of manufacture method of base plate for packaging, include: cladding sheet is provided, comprises the first metal layer, second metal level and intermediate layer, the intermediate layer is between the first metal layer and second metal level; The first metal layer of etching part exposes the intermediate layer of part and forms metal blocks; With the cladding sheet and the first copper clad laminate pressing, first copper clad laminate comprises first insulating barrier and first copper foil layer; Line patternization first copper foil layer forms first patterned circuit; Line patternization second metal level forms second patterned circuit; Remove metal blocks, form cave structure; And removal is positioned at the intermediate layer of cave structure.
According to another preferred embodiment of the invention, the invention provides a kind of manufacture method of semiconductor package body, include: cladding sheet is provided, comprises the first metal layer, second metal level and intermediate layer, the intermediate layer is between the first metal layer and second metal level; The first metal layer of etching part exposes the intermediate layer of part and forms metal blocks; With the cladding sheet and the first copper clad laminate pressing, first copper clad laminate comprises first insulating barrier and first copper foil layer; Line patternization first copper foil layer forms first patterned circuit; Line patternization second metal level forms second patterned circuit, and wherein second patterned circuit comprises a plurality of upside-down mounting connection pads that connect metal blocks; Remove metal blocks, form cave structure; Removal is positioned at the intermediate layer of cave structure; Insert flip-chip in cave structure, its active face is electrically connected with corresponding upside-down mounting connection pad by the tin ball down; And packing material inserted in the cave structure, seal up flip-chip.
According to another preferred embodiment again of the present invention, the invention provides a kind of base plate for packaging of tool cave structure, include: first insulating barrier; Cave structure is arranged in first insulating barrier; First patterned circuit is positioned on the one side of first insulating barrier; Second patterned circuit is positioned on the another side of first insulating barrier with respect to first patterned circuit, and wherein second patterned circuit includes a plurality of upside-down mounting connection pads, is positioned at the bottom of cave structure; And a plurality of first conductive through holes, be arranged in first insulating barrier, be used for being electrically connected first patterned circuit and second patterned circuit.Wherein second patterned circuit is the double-level-metal structure.
In order further to understand feature of the present invention and technology contents, see also following about detailed description of the present invention and accompanying drawing.Yet accompanying drawing is only for reference and aid illustration usefulness, is not to be used for the present invention is limited.
Description of drawings
What Fig. 1 illustrated is the cross-sectional view of traditional stacked encapsulating structure.
Fig. 2 to Figure 13 is the manufacture method according to the stacked encapsulating structure that the preferred embodiment of the present invention illustrated.
Description of reference numerals
1: 2: the first packaging bodies of stacked encapsulating structure
20: the first chips of 3: the second packaging bodies
Substrate 24,34 in 22: the first: moulding material
26,36: 30: the second chips of wire bonds
Substrate 40,402,602 in 32: the second: the tin ball
42: primer 100: cladding sheet
102: intermediate layer 104: the first metal layer
104a: 106: the second metal levels of metal blocks
106a: the second patterned circuit 106b: upside-down mounting connection pad
112: the first insulating barriers of 110: the first copper clad laminates
114: the first copper foil layer 114a: first patterned circuit
130: the second copper clad laminates of 120: the first conductive through holes
134: the second copper foil layers of 132: the second insulating barriers
134a: the 3rd patterned circuit 135,150a, 160a: perforate
14: the three copper clad laminates of 138: the second conductive through holes
144: the three copper foil layers of 142: the three insulating barriers
144a: 148: the three conductive through holes of the 4th patterned circuit
150,160: welding resisting layer 170: nickel-gold layer
180: cave structure 200,610: substrate
200a, 300a: first 200b, 300b: second
Laminar substrate 400 in 300: four: flip-chip
400a: active face 410: packing material
500: packaging body 600:IC packaging body
700: chip 710: the mould closure material
Embodiment
See also Fig. 2 to Figure 13, it is the manufacture method according to the stacked encapsulating structure that the preferred embodiment of the present invention illustrated.At first, as shown in Figure 2, provide cladding sheet 100, for example, copper-nickel-copper (Cu-Ni-Cu) composite metal base material, copper-Solder for Al-Cu Joint Welding (Cu-Al-Cu) composite metal base material or copper clad laminate (copper cladlaminate, CCL).Cladding sheet 100 comprises intermediate layer 102, the first metal layer 104 and second metal level 106.The first metal layer 104 is located on first of intermediate layer 102, second metal level 106 be located at intermediate layer 102 on first second.The first metal layer 104 is preferably the copper metal, and its thickness for example is about between 30 microns to 150 microns, and greater than the thickness of second metal level 106, second metal level 106 is preferably the copper metal, and its thickness is about between 1 micron to 50 microns.If cladding sheet 100 is a copper clad laminate, then its intermediate layer 102 can be glass cloth, epoxy resin or thermosetting resin etc.
As shown in Figure 3, carry out photoetching process and etch process, etch away the first metal layer 104 of part, to form metal blocks 104a.Aforesaid photoetching process and etch process are included in the first metal layer 104 and form photoresist pattern (figure does not show), define the scope and the shape of desire formation metal blocks, and then etch away the first metal layer 104 of not lived by the photoresist pattern covers with wet etch method or dry ecthing method, up to exposing intermediate layer 102.According to a preferred embodiment of the invention, the length of metal blocks 104a * wide size is approximately between 0.5mm * 0.5mm to 10mm * 10mm.In addition, according to another preferred embodiment of the invention, also intermediate layer 102 can be etched away, only stay the part intermediate layer 102 that is positioned under the metal blocks 104a.
As shown in Figure 4, after forming metal blocks 104a, first copper clad laminate 110 of cladding sheet 100 and single face copper is pressed into substrate 200, wherein, first copper clad laminate 110 comprises first insulating barrier 112, for example, and prepreg, and first copper foil layer 114.At this moment, first of substrate 200 200a has 114, the second 200b of first copper foil layer that second metal level 106 is arranged.
As shown in Figure 5, then carry out conductive through hole technology, form a plurality of first conductive through holes 120 in substrate 200, it is electrically connected first copper foil layer 114 on 200 first 200a of substrate and second metal level 106 on second 200b.Aforesaid conductive through hole technology is known technology, and it comprises steps such as boring, chemical copper plating and electro-coppering haply.
As shown in Figure 6, then carry out photoetching process and etch process, on first 200a of substrate 200, etch away first copper foil layer 114 of part and on second 200b, etch away second metal level 106 and the intermediate layer 102 of part, on first 200a of substrate 200 and second 200b, form the first patterned circuit 114a and the second patterned circuit 106a so respectively.It should be noted that this moment, the second patterned circuit 106a included second metal level 106 of part and the intermediate layer 102 of part.And the second patterned circuit 106a also includes a plurality of upside-down mounting connection pads that are connected with metal blocks 104a (flip-chip bond pad) 106b.
As shown in Figure 7, then increase lamination interflow journey, second copper clad laminate 130 of pressing single face copper and the 3rd copper clad laminate 140 of single face copper respectively on first 200a of substrate 200 and second 200b, form four laminar substrates 300, wherein, second copper clad laminate 130 comprises the perforate 135 of reservation, be positioned at metal blocks 104a directly over, to expose metal blocks 104a.Second copper clad laminate 130 comprises second insulating barrier 132, for example dielectric layer and second copper foil layer 134, and the 3rd copper clad laminate 140 comprises the 3rd insulating barrier 142 and the 3rd copper foil layer 144.
As shown in Figure 8, then carry out laser punching technology in regular turn, conductive through hole technology and outside line Patternized technique, on first 300a of four laminar substrates 300, form the 3rd patterned circuit 134a, on second 300b of four laminar substrates 300, form the 4th patterned circuit 144a, wherein, the 3rd patterned circuit 134a electrically connects via second conductive through hole 138 and the first patterned circuit 114a that are formed in second insulating barrier 132, and the 4th patterned circuit 144a electrically connects via the 3rd conductive through hole 148 and the second patterned circuit 106a that are formed in the 3rd insulating barrier 142.
As shown in Figure 9, carry out the welding resisting layer step subsequently, on first 300a of four laminar substrates 300 and second 300b, form welding resisting layer 150 and welding resisting layer 160 respectively.Welding resisting layer 150 and welding resisting layer 160 can be made of photosensitive material.Then, utilize photoetching process, in welding resisting layer 150 and welding resisting layer 160, form perforate 150a and 160a, expose the 3rd patterned circuit 134a and the 4th patterned circuit 144a of part respectively.
As shown in figure 10, then on the copper surface of coming out, form nickel-gold layer 170 or other anti-oxidation metal surface treatment.Be noted that, on the surface of metal blocks 104a, do not form nickel-gold layer this moment.For example, can be when forming nickel-gold layer 170 or other anti-oxidation metal surface treatment, the surface of metal blocks 104a is covered earlier with photoresist, behind the intact nickel-gold layer to be plated then, again photoresist is divested.
As shown in figure 11, then carry out the alkali etching step, after not covering the metal blocks 104a of nickel-gold layer and being positioned at intermediate layer 102 complete ablations under the metal blocks 104a, again with acid solution microetch depression, expose upside-down mounting connection pad 106b, so promptly form four laminar substrates 300 of tool cave structure 180.Be noted that the making flow process among Fig. 2 to Figure 11 is designed at four-sheet structure, the present invention can also be applied in other different package substrate constructions such as doubling plate, three ply board, six laminates or eight laminates.
As shown in figure 12, after finishing four laminar substrates 300 of tool cave structure 180, then insert flip-chip 400 in cave structure 180, its active face 400a electrically connects with corresponding upside-down mounting connection pad 106b by tin ball 402 down.Subsequently, with packing material 410, for example, the epoxy resin-base material is inserted in the cave structure 180, seals up flip-chip 400, so promptly forms the packaging body 500 that flip-chip 400 is embedded in four laminar substrates 300.According to a preferred embodiment of the invention, this moment packing material 410 the surperficial copline of surperficial rough and welding resisting layer 150.
As shown in figure 13, after finishing packaging body 500, follow stacked IC packaging body 600 on packaging body 500.IC packaging body 600 comprises: chip 700, be located on first of substrate 610; Mould closure material 710 envelopes chip 700; A plurality of tin balls 602 are located on second of substrate 610, are electrically connected to the 3rd patterned circuit 134a by nickel/gold layer 170 correspondence.
The above only is the preferred embodiments of the present invention, and all equivalent variations and modifications of doing according to claim of the present invention all should belong to covering scope of the present invention.
Claims (13)
1. the manufacture method of a base plate for packaging includes:
Cladding sheet is provided, comprises the first metal layer, second metal level and intermediate layer, this intermediate layer is between this first metal layer and this second metal level;
This first metal layer of etching part exposes this intermediate layer of part and forms metal blocks;
With this cladding sheet and the first copper clad laminate pressing, this first copper clad laminate comprises first insulating barrier and first copper foil layer;
This first copper foil layer of line patternization forms first patterned circuit;
This second metal level of line patternization forms second patterned circuit;
Remove this metal blocks, form cave structure; And
Removal is positioned at this intermediate layer of this cave structure.
2. the manufacture method of base plate for packaging as claimed in claim 1, wherein the thickness of this first metal layer is greater than this second metal layer thickness.
3. the manufacture method of base plate for packaging as claimed in claim 1, wherein this second patterned circuit comprises a plurality of upside-down mounting connection pads that are positioned at this cave structure bottom.
4. the manufacture method of base plate for packaging as claimed in claim 1 wherein includes following steps in addition:
In this first insulating barrier, form a plurality of first conductive through holes.
5. the manufacture method of base plate for packaging as claimed in claim 1 wherein includes following steps in addition:
Pressing second copper clad laminate on this first patterned circuit, wherein this second copper clad laminate comprises second insulating barrier and second copper foil layer, and this second copper clad laminate has the perforate that corresponds to this metal blocks;
In this second insulating barrier, form a plurality of second conductive through holes; And
This second copper foil layer of line patternization forms the 3rd patterned circuit.
6. the manufacture method of a semiconductor package body includes:
Cladding sheet is provided, comprises the first metal layer, second metal level and intermediate layer, this intermediate layer is between this first metal layer and this second metal level;
This first metal layer of etching part exposes this intermediate layer of part and forms metal blocks;
With this cladding sheet and the first copper clad laminate pressing, this first copper clad laminate comprises first insulating barrier and first copper foil layer;
This first copper foil layer of line patternization forms first patterned circuit;
This second metal level of line patternization forms second patterned circuit, and wherein this second patterned circuit comprises a plurality of upside-down mounting connection pads that connect this metal blocks;
Remove this metal blocks, form cave structure;
Removal is positioned at this intermediate layer of this cave structure;
Insert flip-chip in this cave structure, its active face is electrically connected with corresponding this upside-down mounting connection pad by the tin ball down; And
Packing material is inserted in this cave structure, sealed up this flip-chip.
7. the manufacture method of semiconductor package body as claimed in claim 6, wherein the thickness of this first metal layer is greater than this second metal layer thickness.
8. the manufacture method of semiconductor package body as claimed in claim 6 wherein includes following steps in addition:
In this first insulating barrier, form a plurality of first conductive through holes.
9. the manufacture method of semiconductor package body as claimed in claim 6 wherein includes following steps in addition:
Pressing second copper clad laminate on this first patterned circuit, wherein this second copper clad laminate comprises second insulating barrier and second copper foil layer, and this second copper clad laminate has the perforate that corresponds to this metal blocks;
In this second insulating barrier, form a plurality of second conductive through holes; And
This second copper foil layer of line patternization forms the 3rd patterned circuit.
10. the base plate for packaging of a tool cave structure includes:
First insulating barrier;
Cave structure is arranged in this first insulating barrier;
First patterned circuit is positioned on the one side of this first insulating barrier;
Second patterned circuit, be positioned on the another side of this first insulating barrier with respect to this first patterned circuit, wherein this second patterned circuit includes a plurality of upside-down mounting connection pads, be positioned at the bottom of this cave structure, and this second patterned circuit of part is the double-level-metal structure, this double-level-metal structure bag copper containing layer and intermediate metal layer; And
A plurality of first conductive through holes are arranged in this first insulating barrier, are used for electrically connecting this first patterned circuit and this second patterned circuit.
11. the base plate for packaging of tool cave structure as claimed in claim 10, wherein this intermediate metal layer comprises nickel or aluminium.
12. the base plate for packaging of tool cave structure as claimed in claim 10 wherein includes second insulating barrier in addition, covers this first patterned circuit, and the 3rd patterned circuit, is positioned on this second insulating barrier.
13. the base plate for packaging of tool cave structure as claimed in claim 12 wherein includes a plurality of second conductive through holes in addition, is arranged in this second insulating barrier, is used for electrically connecting this first patterned circuit and the 3rd patterned circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2009100070588A CN101800184B (en) | 2009-02-09 | 2009-02-09 | Packaging base plate with cave structure and manufacture method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2009100070588A CN101800184B (en) | 2009-02-09 | 2009-02-09 | Packaging base plate with cave structure and manufacture method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN101800184A true CN101800184A (en) | 2010-08-11 |
| CN101800184B CN101800184B (en) | 2012-01-25 |
Family
ID=42595796
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2009100070588A Expired - Fee Related CN101800184B (en) | 2009-02-09 | 2009-02-09 | Packaging base plate with cave structure and manufacture method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN101800184B (en) |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102931165A (en) * | 2012-11-15 | 2013-02-13 | 日月光半导体（上海）股份有限公司 | Package substrate and manufacturing method thereof |
| CN103187386A (en) * | 2011-12-30 | 2013-07-03 | 矽品精密工业股份有限公司 | Substrate structure, packaging structure and manufacturing method thereof |
| CN104882416A (en) * | 2013-11-13 | 2015-09-02 | 钰桥半导体股份有限公司 | Semiconductor Package With Package-on-package Stacking Capability And Method Of Manufacturing The Same |
| CN106206508A (en) * | 2014-09-17 | 2016-12-07 | 三星电机株式会社 | Package board, manufacture the method for package board and there is the stacked package part of package board |
| CN106298759A (en) * | 2016-09-09 | 2017-01-04 | 宜确半导体（苏州）有限公司 | A kind of radio-frequency power amplifier module and RF front-end module |
| TWI569392B (en) * | 2014-10-20 | 2017-02-01 | 欣興電子股份有限公司 | Method for manufacturing a carrier having a cavity |
| CN109841531A (en) * | 2019-01-30 | 2019-06-04 | 深圳市志金电子有限公司 | Package substrate manufacturing process, package substrate and wafer packaging structure |
-
2009
- 2009-02-09 CN CN2009100070588A patent/CN101800184B/en not_active Expired - Fee Related
Cited By (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103187386A (en) * | 2011-12-30 | 2013-07-03 | 矽品精密工业股份有限公司 | Substrate structure, packaging structure and manufacturing method thereof |
| CN103187386B (en) * | 2011-12-30 | 2016-02-03 | 矽品精密工业股份有限公司 | Board structure, encapsulating structure and method for making thereof |
| CN102931165A (en) * | 2012-11-15 | 2013-02-13 | 日月光半导体（上海）股份有限公司 | Package substrate and manufacturing method thereof |
| CN102931165B (en) * | 2012-11-15 | 2015-08-19 | 日月光半导体(上海)有限公司 | The manufacture method of base plate for packaging |
| CN104882416A (en) * | 2013-11-13 | 2015-09-02 | 钰桥半导体股份有限公司 | Semiconductor Package With Package-on-package Stacking Capability And Method Of Manufacturing The Same |
| CN104882416B (en) * | 2013-11-13 | 2017-10-20 | 钰桥半导体股份有限公司 | Semiconductor package part with stacked package ability and preparation method thereof |
| CN106206508A (en) * | 2014-09-17 | 2016-12-07 | 三星电机株式会社 | Package board, manufacture the method for package board and there is the stacked package part of package board |
| CN106206508B (en) * | 2014-09-17 | 2019-06-28 | 三星电机株式会社 | Package board, the method for manufacturing package board and the stacked package part with package board |
| TWI569392B (en) * | 2014-10-20 | 2017-02-01 | 欣興電子股份有限公司 | Method for manufacturing a carrier having a cavity |
| CN106298759A (en) * | 2016-09-09 | 2017-01-04 | 宜确半导体（苏州）有限公司 | A kind of radio-frequency power amplifier module and RF front-end module |
| CN109841531A (en) * | 2019-01-30 | 2019-06-04 | 深圳市志金电子有限公司 | Package substrate manufacturing process, package substrate and wafer packaging structure |
Also Published As
| Publication number | Publication date |
|---|---|
| CN101800184B (en) | 2012-01-25 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN100562991C (en) | Semiconductor package and forming method thereof | |
| CN101789383B (en) | Method for making packaging substrate with recess structure | |
| CN101800184B (en) | Packaging base plate with cave structure and manufacture method thereof | |
| KR100553281B1 (en) | Semiconductor device and board for mounting semiconductor element, and method for manufacturing the same | |
| US7902652B2 (en) | Semiconductor package and semiconductor system in package using the same | |
| US7829987B2 (en) | Carrier structure embedded with semiconductor chips and method for manufacturing the same | |
| US8304917B2 (en) | Multi-chip stacked package and its mother chip to save interposer | |
| US7768119B2 (en) | Carrier structure embedded with semiconductor chip | |
| KR100723493B1 (en) | Substrate for smart card modules applicable to both wire bonding and flip chip, and the smart card modules including them | |
| CN101288351A (en) | Printed wiring board and method for manufacturing printed wiring board | |
| CN101887874A (en) | Substrate having single patterned metal layer, and package applied with the substrate , and methods of manufacturing of the substrate and package | |
| JP2005317861A (en) | Semiconductor device and method of manufacturing the same | |
| CN103681559A (en) | Chip packaging basal plate and preparation method thereof | |
| CN101252092A (en) | Multi-chip packaging structure and making method thereof | |
| US7927919B1 (en) | Semiconductor packaging method to save interposer | |
| TWI417993B (en) | Package substrate with a cavity, semiconductor package and fabrication method thereof | |
| CN101877334A (en) | Semiconductor device with heat radiation and gain | |
| JP4379693B2 (en) | Semiconductor device and manufacturing method thereof | |
| JP2001274324A (en) | Semiconductor mounting substrate for multilayer semiconductor device, and semiconductor device and multilayer semiconductor device | |
| EP2068361A1 (en) | Packaging substrate having chip embedded therein and manufacturing method thereof | |
| CN102664170A (en) | Semiconductor package structure and manufacturing method thereof | |
| CN101236942B (en) | IC base plate and its making method | |
| KR20150043135A (en) | printed circuit board which includes metal layer and semiconductor package including the same | |
| CN102751203A (en) | Semiconductor encapsulation structure and manufacture method of semiconductor encapsulation structure | |
| CN113299564A (en) | Packaging structure of board-level fan-out flexible packaging substrate and preparation method thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20120125 Termination date: 20210209 |