CN101794048A - Display panel and maintenance method thereof - Google Patents
Display panel and maintenance method thereof Download PDFInfo
- Publication number
- CN101794048A CN101794048A CN200910007018A CN200910007018A CN101794048A CN 101794048 A CN101794048 A CN 101794048A CN 200910007018 A CN200910007018 A CN 200910007018A CN 200910007018 A CN200910007018 A CN 200910007018A CN 101794048 A CN101794048 A CN 101794048A
- Authority
- CN
- China
- Prior art keywords
- electrode
- source electrode
- drain electrode
- metal wire
- pixel
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Images
Landscapes
- Liquid Crystal (AREA)
- Devices For Indicating Variable Information By Combining Individual Elements (AREA)
Abstract
The invention discloses a display panel and a maintenance method thereof. The display panel comprises at least one pixel group, wherein the pixel group comprises a first scan line, a second scan line, a third scan line, a first data wire, a second data wire, a first pixel structure and a second pixel structure; every pixel structure comprises two thin film transistors and pixel electrodes corresponding to TFT; and every thin film transistor comprises sources, grids and drains, wherein a first thin film transistor has defects. The maintenance method of the display panel comprises: cutting off the electrical connection of a third drain and a fourth source; cutting off the electrical connection of a fourth thin film transistor and a fourth pixel electrode; electrically connecting the fourth source with a first drain; and electrically connecting the fourth pixel electrode with the third scan line.
Description
Technical field
The present invention relates in particular to a kind of display panel and method for maintaining thereof that keeps in repair dot structure relevant for a kind of display panel and method for maintaining thereof.
Background technology
Generally speaking, display panel (for example display panels) is made of two plate bases up and down and the liquid crystal layer that is folded between the two substrates, can dispose pel array on one of them substrate, the zone at this pel array place promptly is the viewing area of watching display frame for the user.The pel array of display panels normally substrate is provided with many interlaced sweep traces and data line, these sweep traces are to be arranged at abreast on the substrate, these data lines are that vertical interlaced is in these sweep traces, to form the viewing area, the viewing area can be provided with a plurality of pixel cells, i.e. pel array.Each pixel cell is provided with pixel electrode and driving component (for example membrane transistor pipe TFT) and shared electrode wire, in order to show image, wherein can form a storage capacitors Cst between shared electrode wire and the pixel electrode.Can form outer peripheral areas around the viewing area, in order to for example pad (Bonding Pad), driving circuit assembly (for example drive IC, FPC) to be set, the space that perhaps provides circuit to lay.
The type of drive of conventional liquid crystal is respectively to have a sweep trace (grid signal line) and a data line (or source electrode signal line) transmission to drive the membrane transistor pipe that signal is given sub-pixel at each single sub-pixel, need integrated circuit (IC) chip (source IC) to authorize signal and drive source electrode, but when monitor resolution improves, then need more drive IC.Yet, provide the expense of the gate drive apparatus of sweep signal and data-signal and source electrode driving device higher respectively, especially source electrode driving device is expensive especially.In order to save cost, the method of many minimizing data lines promptly is suggested, for example use a data line to transmit signal to 2 a sub-picture element, but need to increase the sweep trace to 2 times of former quantity, this measure not only increases the use amount and the cost of gate drive apparatus, also reduce each aperture ratio of pixels (Aperture Ratio, AR).
For improving this phenomenon, develop the driving signal that another pel array and arrange in pairs or groups specific, to reach identical pixel electrode charging effect.As shown in Figure 6, Fig. 6 is the equivalent circuit diagram of the pel array of display panel of the prior art.The pel array of display panel comprises many group pixels, and each pixel groups comprises the first sweep trace 212a, the second sweep trace 212b, data line 214, first active member (for example being membrane transistor) 216a, the second active member 216b, the first pixel electrode 218a, the second pixel electrode 218b, the first shared electrode wire 220a and the second shared electrode wire 220b.The first sweep trace 212a and the second sweep trace 212b be arranged in parallel, and the data line 214 vertical first sweep trace 212a and the second sweep trace 212b.Wherein, the first active member 216a and the first sweep trace 212a and data line 214 electrically connects, and the second active member 216b electrically connects with second sweep trace 212b electric connection and with the first active member 216a.In the present embodiment, the drain D 1 of the first active member 216a and the source S of the second active member 216b 2 electrically connect, so that the second active member 216b and the first active member 216a electrically connect.Have a connecting line CL between the first pixel electrode 218a and the second pixel electrode 218b, it is in order to the drain D 1 that electrically connects the first active member 216a and the source S 2 of the second active member 216b.Thus, the second active member 216b just can electrically connect with data line 214 by the first active member 216a.In addition, the first pixel electrode 218a and the first active member 216a electrically connect, and the second pixel electrode 218b and the second active member 216b electrically connect.In other words, the first pixel electrode 218a can receive data-signal on the data line 214 by the first active member 216a, and the second pixel electrode 218b then can receive data-signal on the data line 214 by the second active member 216b.
But because the employed source signal of the second membrane transistor 216b is provided by the first film electric crystal 216a, if the first film electric crystal 216a can't normal running because of the processing procedure defective, to also make the second membrane transistor 216b can't normal running, this will once cause two abnormal show picture elements.Thereby need seek a kind of method and solve this problem.
Summary of the invention
The object of the present invention is to provide a kind of display panel and method for maintaining thereof, can solve the problem that a membrane transistor defective causes two pixels to lose efficacy, improve the product yield, reduce cost.
The invention provides a kind of display panel method for maintaining, this display panel comprises at least one pixel groups, and this pixel groups comprises: first sweep trace, second sweep trace and three scan line, and it is arranged in parallel; First data line and second data line, vertical this first sweep trace, this second sweep trace and this three scan line setting, wherein this first sweep trace, this first data line, this second sweep trace and this second data line define first pixel region, and this second sweep trace, this first data line, this three scan line and this second data line define second pixel region; First dot structure is arranged at this first pixel region, and this first dot structure comprises first pixel electrode and second pixel electrode; The first film electric crystal, electrically connect with this first pixel electrode, this the first film electric crystal has first grid, first source electrode and first drain electrode, this first grid is to be electrically connected at this second sweep trace, and this first source electrode is to be electrically connected at this first data line, and there is defective in this first film electric crystal; And second membrane transistor, electrically connect with this second pixel electrode, this second membrane transistor has second grid, second source electrode and second drain electrode, this second grid is to be electrically connected at this first sweep trace, and this second source electrode is to be electrically connected at this first drain electrode, and this second drain electrode is to be electrically connected at this second pixel electrode; Second dot structure, be arranged at this second pixel region, this second dot structure comprises the 3rd membrane transistor, electrically connect with the 3rd pixel electrode, the 3rd membrane transistor has the 3rd grid, the 3rd source electrode and the 3rd drain electrode, the 3rd grid is to be electrically connected at this three scan line, and the 3rd source electrode is to be electrically connected at this second data line; The 4th membrane transistor, electrically connect with the 4th pixel electrode, the 4th membrane transistor has the 4th grid, the 4th source electrode and the 4th drain electrode, the 4th grid is to be electrically connected at this second sweep trace, and the 4th drain electrode is to be electrically connected at the 4th pixel electrode, and the 4th source electrode is electrically connected at the 3rd drain electrode; This method for maintaining comprises: cut off the electric connection between the 3rd drain electrode and the 4th source electrode; Cut off the electric connection of the 4th membrane transistor and the 4th pixel electrode; Electrically connect the 4th source electrode and this first drain electrode; Electrically connect the 4th drain electrode and this first source electrode; And electrically connect the 4th pixel electrode and this three scan line.
As optional technical scheme, this display panel also comprises first metal wire and second metal wire, and this first metal wire is positioned at different line layers with this second metal wire with this first film electric crystal and this second membrane transistor.
As optional technical scheme, this first drain electrode is overlapped with this first metal wire, and the 4th source electrode and this first metal wire are overlapped, and this first drain electrode is not overlapping with the 4th source electrode; This first source electrode and this second metal wire are overlapped, and the 4th drain electrode is overlapped with this second metal wire, and this first source electrode and the 4th drains not overlapping.
As optional technical scheme, this electrically connects the 4th source electrode and this first drain electrode comprises: electrically connect the 4th source electrode and this first metal wire; And electrically connect this first metal wire and this first drain electrode; This electrically connects the 4th drain electrode and comprises with this first source electrode: electrically connect the 4th drain electrode and this second metal wire; And electrically connect this second metal wire and this first source electrode.
As optional technical scheme, the 4th source electrode and this first metal wire overlapping have first contact hole, and electrically connect by this first contact hole; The 4th drain electrode has second contact hole with this second metal wire overlapping, and electrically connects by this second contact hole.
As optional technical scheme, this electrically connects the 4th source electrode and this first drain electrode comprises: electrically connect this first metal wire and this first drain electrode; This electrically connects the 4th drain electrode and comprises with this first source electrode: electrically connect this second metal wire and this first source electrode.
The present invention also provides a kind of display panel, comprising: substrate; And at least one pixel groups, this pixel groups comprises: first sweep trace, second sweep trace and three scan line are set in parallel on this substrate; First data line and second data line, vertical this first sweep trace, this second sweep trace and this three scan line are arranged on this substrate, wherein this first sweep trace, this first data line, this second sweep trace and this second data line define first pixel region, and this second sweep trace, this first data line, this three scan line and this second data line define second pixel region; First dot structure is arranged at this first pixel region, and this first dot structure comprises first pixel electrode and second pixel electrode; The first film electric crystal, electrically connect with this first pixel electrode, this the first film electric crystal has first grid, first source electrode and first drain electrode, this first grid is to be electrically connected at this second sweep trace, and this first source electrode is to be electrically connected at this first data line, and there is defective in this first film electric crystal; And second membrane transistor, electrically connect with this second pixel electrode, this second membrane transistor has second grid, second source electrode and second drain electrode, this second grid is to be electrically connected at this first sweep trace, and this second source electrode is to be electrically connected at this first drain electrode, and this second drain electrode is to be electrically connected at this second pixel electrode; Second dot structure, be arranged at this second pixel region, this second dot structure comprises the 3rd membrane transistor, electrically connect with the 3rd pixel electrode, the 3rd membrane transistor has the 3rd grid, the 3rd source electrode and the 3rd drain electrode, the 3rd grid is to be electrically connected at this three scan line, and the 3rd source electrode is to be electrically connected at this second data line; The 4th membrane transistor, electrically connect with the 4th pixel electrode, the 4th membrane transistor has the 4th grid, the 4th source electrode and the 4th drain electrode, the 4th grid is to be electrically connected at the 3rd drain electrode, and the 4th drain electrode is to be electrically connected at the 4th pixel electrode, and the 4th source electrode is electrically connected at the 3rd drain electrode; Wherein, has first cut-out point between the 3rd drain electrode and the 4th source electrode; Has second cut-out point between the 4th membrane transistor and the 4th pixel electrode; The 4th source electrode and this first drain electrode electric connection and the 4th drain electrode electrically connect with this first source electrode, thereby make the 4th membrane transistor drive this first pixel electrode and this second pixel electrode; And the 4th pixel electrode and this three scan line electrically connect.
As optional technical scheme, this display panel also comprises first metal wire and second metal wire, and this first metal wire is positioned at different line layers with this second metal wire with this first film electric crystal and this second membrane transistor.
As optional technical scheme, this first drain electrode is overlapped with this first metal wire, and the 4th source electrode and this first metal wire are overlapped, and this first drain electrode is not overlapping with the 4th source electrode; This first source electrode and this second metal wire are overlapped, and the 4th drain electrode is overlapped with this second metal wire, and this first source electrode and the 4th drains not overlapping.
As optional technical scheme, the 4th source electrode and this first metal wire overlapping have first contact hole, and electrically connect by this first contact hole; The 4th drain electrode has second contact hole with this second metal wire overlapping, and electrically connects by this second contact hole.
Can be about the advantages and spirit of the present invention by following detailed Description Of The Invention and appended graphic being further understood.
Description of drawings
Fig. 1 is the equivalent circuit diagram of the pel array of display panel of the present invention.
There is the synoptic diagram of the display panel of defective in Fig. 2 for the first film electric transistor of the present invention.
Fig. 3 is the synoptic diagram of the display panel after the display panel method for maintaining of the first embodiment of the present invention keeps in repair.
Figure 4 shows that the synoptic diagram of the display panel after the display panel method for maintaining maintenance of the second embodiment of the present invention.
Figure 5 shows that the method flow diagram of display panel method for maintaining of the present invention.
Fig. 6 is the equivalent circuit diagram of the pel array of display panel of the prior art.
Embodiment
See also Fig. 1, Fig. 1 is the equivalent circuit diagram of the pel array of display panel of the present invention.Display panel method for maintaining of the present invention is in order to display panel is keeped in repair, display panel after this method for maintaining and adopting said method keep in repair can be applicable in various display or the system, for example: LCD (Liquid Crystal Display, LCD), display of organic electroluminescence, organic light emitting diode display, Plasmia indicating panel, field emission display, CNT display or electric ink (E-ink) display etc.In the present embodiment, display panel 100 is to be that example illustrates with the display panels, and at this moment, display panel can not be provided with respect to backlight module (illustrating), and forms liquid crystal indicator.But be not limited thereto, the present invention also can be applicable to the display panel of other pattern.
As shown in Figure 1, the display panel of present embodiment comprises substrate (not illustrating), substrate can be brittle base (for example glass substrate) or flexible base plate (for example plastic base), and in one embodiment, substrate for example is thin film transistor (TFT) (Thin Film Transistor; TFT) array base palte, at this moment, display panel can for example be a display panels, it can more comprise liquid crystal layer (not illustrating) and colored filter (ColorFilter; CF) substrate (not illustrating).
In the present embodiment, display panels also comprises at least one pixel groups, and this pixel groups comprises first sweep trace 4, second sweep trace 2, three scan line 6, first data line 3, second data line 1, first dot structure and second dot structure.First sweep trace 4, second sweep trace 2 and three scan line 6 are arranged in parallel on substrate.First data line 3 and second data line, 1 vertical first sweep trace 4, second sweep trace 2 and three scan line 6 are arranged on the substrate.Wherein, first sweep trace 4, first data line 3, second sweep trace 2 and second data line 1 define first pixel region; Second sweep trace 2, first data line 3, three scan line 6 and second data line 1 define second pixel region.In addition, display panels also includes the shared electrode wire (not shown), wherein can form storage capacitors Cst between shared electrode wire and the pixel electrode.In the present embodiment, first sweep trace 4, second sweep trace 2 and three scan line 6 are made of the first metal layer, first data line 3 and second data, 1 line are made of second metal level, and first shared electrode wire and second shared electrode wire are made of the transparency conducting layer that is positioned at the first metal layer and second metal level top, and wherein second metal level is between the first metal layer and transparency conducting layer.Yet in other embodiments, first data line 3 and second data line 1 are made of the first metal layer, and first sweep trace 4, second sweep trace 2 and three scan line 6 are made of second metal level.
See also Fig. 1 and Fig. 2, there is the synoptic diagram of the display panel of defective in Fig. 2 for the first film electric transistor of the present invention.First dot structure is arranged at first pixel region, and first dot structure comprises first pixel electrode 74, second pixel electrode 84, the first film electric crystal 7 and second membrane transistor 8.Wherein, the first film electric crystal 7 and first pixel electrode 74 electrically connect, and for example electrically connect by contact hole.The first film electric crystal 7 has first grid 71, first channel layer, first source electrode 72 and first drain electrode 73, first grid 71 is to be electrically connected at or to be integrated in second sweep trace 2, and first source electrode 72 is to be electrically connected at first data line 3, and there is defective in the first film electric crystal 7, and for example short circuit phenomenon can't be worked.Second membrane transistor 8 and second pixel electrode 84 electrically connect, second membrane transistor 8 has second grid 81, second channel layer, second source electrode 82 and second drain electrode 83, second grid 81 is to be electrically connected at or to be integrated in first sweep trace 4, and second source electrode 82 is to be electrically connected at first drain electrode 73, and second drain electrode 83 is to be electrically connected at second pixel electrode 84, for example is electrically connected to second pixel electrode 84 by contact hole (or through hole).Second dot structure is arranged at second pixel region, and second dot structure comprises the 3rd pixel electrode 94, the 4th pixel electrode 14, the 3rd membrane transistor 9 and the 4th membrane transistor 10.The 3rd membrane transistor 9 and the 3rd pixel electrode 94 electrically connect, the 3rd membrane transistor 9 has the 3rd grid 91, triple channel layer, the 3rd source electrode 92 and the 3rd drain electrode 93, the 3rd grid 91 is to be electrically connected at three scan line 6, and the 3rd source electrode 92 is to be electrically connected at second data line 1.The 4th membrane transistor 10 and the 4th pixel electrode 14 electrically connect, the 4th membrane transistor 10 has the 4th grid 11, the 4th channel layer, the 4th source electrode 12 and the 4th drain electrode 13, the 4th grid 11 is to be electrically connected at second sweep trace 2, the 4th source electrode 12 is electrically connected at the 3rd drain electrode 93, and the 4th drain electrode 13 is to be electrically connected at the 4th pixel electrode 14, for example is electrically connected to the 4th pixel electrode 14 by contact hole (or through hole).
For example, under the situation of the first film electric crystal 7 operate as normal, if a view data will be write in first dot structure, present embodiment can provide high voltage to sweep trace 2 with the first grid 71 of opening the first film electric crystal 7 and the second grid 81 of second membrane transistor 8, and then view data (Vdata) is write to first pixel electrode 74 via first source electrode 72 of the first film electric crystal 7, first channel layer, first drain electrode 73, its capacitive coupling electrode and contact hole etc. by first data line 3, so that 74 work of first pixel electrode.Yet, when view data being write first pixel electrode 320, view data (Vdata) can write to second pixel electrode 84 via second source electrode 82, second channel layer, second drain electrode 83, its capacitive coupling electrode and the contact hole etc. of second membrane transistor 8, so that 84 work of second pixel electrode.
In addition, display panels also comprises first metal wire 15 and second metal wire 16, first metal wire 15 is positioned at different line layers with second metal wire 16 with the first film electric crystal and this second membrane transistor, and is not in same line layer with first data line 3 and second data line 1.In the present embodiment, first metal wire 15 and second metal wire 16 for example can be on the same line layer with first sweep trace 4, second sweep trace 2 and three scan line 6.First drain electrode, 73 and first metal wire 15 of display panel is overlapped, and the 4th source electrode 12 and first metal wire 15 are also overlapped, but first drain electrode the 73 and the 4th source electrode 12 is not overlapping; In addition, first source electrode 72 and second metal wire 16 are overlapped, and the 4th drain electrode 13 and second metal wire 16 is also overlapped, and first source electrode 72 is not overlapping with the 4th drain electrode 13.
Wherein, the method for maintaining that occurs after the short circuit of the first film electric crystal of display panels comprises following step.See also Fig. 3 and Fig. 5, Fig. 3 is the synoptic diagram of the display panel after the display panel method for maintaining of the first embodiment of the present invention keeps in repair, and Figure 5 shows that the method flow diagram of display panel method for maintaining of the present invention.At first,, cut off the electric connection of 12 of the 3rd drain electrode the 93 and the 4th source electrodes, for example utilize cut to form first and cut off line 17 as step S100.As step S101, cut off the electric connection of the 4th membrane transistor 10 and the 4th pixel electrode 14, can adopt cut to form second equally and cut off line 18.Step S102 electrically connects the 4th source electrode 12 and first drain electrode 73, and this step for example can utilize laser welding technology to form solder joint A (or tie point) conducting the 4th source electrode 12 and first metal wire 15 at lap 24 places of the 4th source electrode 12 and first metal wire 15; Form welding point B (or tie point) conducting first drain electrode 73 and first metal wire 15 again at lap 25 places of first drain electrode, 73 and first metal wire 15, thereby electrically connect first drain electrode the 73 and the 4th source electrode 12.Step S103 electrically connects the 4th drain electrode 13 and first source electrode 72, and wherein first source electrode 72 is connected to first data line 3, so can also say, electrically connects the 4th drain electrode 13 and first data line 3; In this step, for example can utilize laser welding technology to form solder joint C (or tie point) conducting the 4th drain electrode 13 and second metal wire 16 at lap 27 places of the 4th drain electrode 13 and second metal wire 16; At lap 26 places formation solder joint D (or tie point) conducting first source electrode 72 and second metal wire 16 of first data line 3 (or first source electrode 72), drain 13 again thereby electrically connect first source electrode 72 and the 4th with second metal wire 16.There is defective the first film electric crystal thereby utilize the 4th membrane transistor to repair, solves because the defective of the first film electric crystal causes the problem of two undesired demonstrations of pixel of first dot structure.At last, step S104, electrically connect the 4th pixel electrode 14 and three scan line 6, for example utilize laser welding technology to form solder joint (or tie point) E at the 4th pixel electrode 14 and three scan line 6 overlappings, conducting the 4th pixel electrode 14 and three scan line 6, thereby the 4th darkening pixels that the 4th membrane transistor and the 4th pixel electrode are formed.
See also Fig. 4 and Fig. 5, Figure 4 shows that the synoptic diagram of the display panel after the display panel method for maintaining maintenance of the second embodiment of the present invention.Display panels is except that having the described pel array of the foregoing description, wherein the 4th source electrode 12 of this pixel groups of display panels and first metal wire, 15 overlappings 24 also have first contact hole, 22, the four source electrodes 12 by first contact hole 22 and 15 electric connections of first metal wire; The overlapping 27 of the 4th drain electrode 13 and second metal wire 16 has 21, the four drain electrodes 13 of second contact hole and electrically connects by second contact hole 21 and second metal wire 16.Understandable, first contact hole 22 also can be positioned at first drain electrode, 73 and first metal wire, 15 overlapping conductings, first drain electrode, 73 and first metal wire 15; Second contact hole 21 also can be positioned at the overlapping of first source electrode 72 and second metal wire 16, conducting first source electrode 72 and second metal wire 16.At this moment, the method for maintaining that occurs after the short circuit of the first film electric crystal of display panels comprises following step.At first, step S100 cuts off the electric connection of 12 of the 3rd drain electrode the 93 and the 4th source electrodes, for example utilizes cut to form first and cuts off line 17.Step S101 cuts off the electric connection of the 4th membrane transistor 10 and the 4th pixel electrode 14, can adopt cut to form second equally and cut off line 18.Step S102, electrically connect the 4th source electrode 12 and first drain electrode 73, this step for example can utilize laser welding technology to form welding point B (or tie point) conducting first drain electrode 73 and first metal wire 15 at lap 25 places of first drain electrode, 73 and first metal wire 15, thereby electrically connects first drain electrode the 73 and the 4th source electrode 12.Step S103 electrically connects the 4th drain electrode 13 and first source electrode 72, and wherein first source electrode 72 is connected to first data line 3, so can also say, electrically connects the 4th drain electrode 13 and first data line 3; In this step, for example can utilize laser welding technology at lap 26 places formation solder joint (or tie point) D conducting first source electrode 72 and second metal wire 16 of first data line 3 (or first source electrode 72), thereby electrically connect first source electrode 72 and the 4th drain electrode 13 with second metal wire 16.At last, step S104, electrically connect the 4th pixel electrode 14 and three scan line 6, for example utilize laser welding technology to form solder joint (or tie point) E at the 4th pixel electrode 14 and three scan line 6 overlappings, conducting the 4th pixel electrode 14 and three scan line 6, thereby the 4th darkening pixels that the 4th membrane transistor and the 4th pixel electrode are formed.
As mentioned above, display panel method for maintaining of the present invention uses adjacent normal flawless membrane transistor to replace defective membrane transistor, the pixel that two defectiveness can't normally be shown is repaired into the pixel of a dim spotization, has improved the product yield, and helps reducing cost.
By the detailed description of above embodiment, be to wish to know more to describe feature of the present invention and spirit, and be not to come claim scope of the present invention is limited with above-mentioned disclosed embodiment.On the contrary, its objective is that hope can contain in being arranged in of various changes and the tool equality claim scope of the present invention.Therefore, claim scope of the present invention should be done the broadest explanation according to above-mentioned explanation, contains the arrangement of all possible change and tool equality to cause it.
Claims (10)
1. display panel method for maintaining, this display panel comprises at least one pixel groups, this pixel groups comprises:
First sweep trace, second sweep trace and three scan line, it is arranged in parallel;
First data line and second data line, vertical this first sweep trace, this second sweep trace and this three scan line setting, wherein this first sweep trace, this first data line, this second sweep trace and this second data line define first pixel region, and this second sweep trace, this first data line, this three scan line and this second data line define second pixel region;
First dot structure is arranged at this first pixel region, and this first dot structure comprises:
First pixel electrode and second pixel electrode;
The first film electric crystal, electrically connect with this first pixel electrode, this the first film electric crystal has first grid, first source electrode and first drain electrode, this first grid is to be electrically connected at this second sweep trace, and this first source electrode is to be electrically connected at this first data line, and there is defective in this first film electric crystal; And
Second membrane transistor, electrically connect with this second pixel electrode, this second membrane transistor has second grid, second source electrode and second drain electrode, this second grid is to be electrically connected at this first sweep trace, and this second source electrode is to be electrically connected at this first drain electrode, and this second drain electrode is to be electrically connected at this second pixel electrode;
Second dot structure is arranged at this second pixel region, and this second dot structure comprises:
The 3rd pixel electrode and the 4th pixel electrode;
The 3rd membrane transistor, electrically connect with the 3rd pixel electrode, the 3rd membrane transistor has the 3rd grid, the 3rd source electrode and the 3rd drain electrode, and the 3rd grid is to be electrically connected at this three scan line, and the 3rd source electrode is to be electrically connected at this second data line; And
The 4th membrane transistor, electrically connect with the 4th pixel electrode, the 4th membrane transistor has the 4th grid, the 4th source electrode and the 4th drain electrode, the 4th grid is to be electrically connected at this second sweep trace, and the 4th drain electrode is to be electrically connected at the 4th pixel electrode, and the 4th source electrode is electrically connected at the 3rd drain electrode; It is characterized in that this method for maintaining comprises:
Cut off the electric connection between the 3rd drain electrode and the 4th source electrode;
Cut off the electric connection of the 4th membrane transistor and the 4th pixel electrode;
Electrically connect the 4th source electrode and this first drain electrode;
Electrically connect the 4th drain electrode and this first source electrode; And
Electrically connect the 4th pixel electrode and this three scan line.
2. method for maintaining as claimed in claim 1 is characterized in that this display panel also comprises first metal wire and second metal wire, and this first metal wire is positioned at different line layers with this second metal wire with this first film electric crystal and this second membrane transistor.
3. method for maintaining as claimed in claim 2 is characterized in that this first drain electrode overlaps with this first metal wire, and the 4th source electrode and this first metal wire are overlapped, and this first drain electrode and the 4th source electrode are not overlapping; This first source electrode and this second metal wire are overlapped, and the 4th drain electrode is overlapped with this second metal wire, and this first source electrode and the 4th drains not overlapping.
4. method for maintaining as claimed in claim 3 is characterized in that
This electrically connects the 4th source electrode and this first drain electrode comprises:
Electrically connect the 4th source electrode and this first metal wire; And
Electrically connect this first metal wire and this first drain electrode;
This electrically connects the 4th drain electrode and comprises with this first source electrode:
Electrically connect the 4th drain electrode and this second metal wire; And
Electrically connect this second metal wire and this first source electrode.
5. method for maintaining as claimed in claim 3 is characterized in that the 4th source electrode and this first metal wire overlapping have first contact hole, and electrically connects by this first contact hole; The 4th drain electrode has second contact hole with this second metal wire overlapping, and electrically connects by this second contact hole.
6. method for maintaining as claimed in claim 5 is characterized in that
This electrically connects the 4th source electrode and this first drain electrode comprises:
Electrically connect this first metal wire and this first drain electrode;
This electrically connects the 4th drain electrode and comprises with this first source electrode:
Electrically connect this second metal wire and this first source electrode.
7. a display panel is characterized in that this display panel comprises substrate and at least one pixel groups, and this pixel groups comprises:
First sweep trace, second sweep trace and three scan line are set in parallel on this substrate;
First data line and second data line, vertical this first sweep trace, this second sweep trace and this three scan line are arranged on this substrate, wherein this first sweep trace, this first data line, this second sweep trace and this second data line define first pixel region, and this second sweep trace, this first data line, this three scan line and this second data line define second pixel region;
First dot structure is arranged at this first pixel region, and this first dot structure comprises
First pixel electrode and second pixel electrode;
The first film electric crystal, electrically connect with this first pixel electrode, this the first film electric crystal has first grid, first source electrode and first drain electrode, this first grid is to be electrically connected at this second sweep trace, and this first source electrode is to be electrically connected at this first data line, and there is defective in this first film electric crystal; And
Second membrane transistor, electrically connect with this second pixel electrode, this second membrane transistor has second grid, second source electrode and second drain electrode, this second grid is to be electrically connected at this first sweep trace, and this second source electrode is to be electrically connected at this first drain electrode, and this second drain electrode is to be electrically connected at this second pixel electrode;
Second dot structure is arranged at this second pixel region, and this second dot structure comprises
The 3rd membrane transistor, electrically connect with the 3rd pixel electrode, the 3rd membrane transistor has the 3rd grid, the 3rd source electrode and the 3rd drain electrode, and the 3rd grid is to be electrically connected at this three scan line, and the 3rd source electrode is to be electrically connected at this second data line; And
The 4th membrane transistor, electrically connect with the 4th pixel electrode, the 4th membrane transistor has the 4th grid, the 4th source electrode and the 4th drain electrode, the 4th grid is to be electrically connected at the 3rd drain electrode, and the 4th drain electrode is to be electrically connected at the 4th pixel electrode, and the 4th source electrode is electrically connected at the 3rd drain electrode;
Wherein, have first between the 3rd drain electrode and the 4th source electrode and cut off line;
Have second between the 4th membrane transistor and the 4th pixel electrode and cut off line;
The 4th source electrode and this first drain electrode electric connection and the 4th drain electrode electrically connect with this first source electrode, thereby make the 4th membrane transistor drive this first pixel electrode and this second pixel electrode; And
The 4th pixel electrode and this three scan line electrically connect.
8. display panel as claimed in claim 7 is characterized in that this display panel also comprises first metal wire and second metal wire, and this first metal wire is positioned at different line layers with this second metal wire with this first film electric crystal and this second membrane transistor.
9. display panel as claimed in claim 8 is characterized in that this first drain electrode overlaps with this first metal wire, and the 4th source electrode and this first metal wire are overlapped, and this first drain electrode and the 4th source electrode are not overlapping; This first source electrode and this second metal wire are overlapped, and the 4th drain electrode is overlapped with this second metal wire, and this first source electrode and the 4th drains not overlapping.
10. display panel as claimed in claim 9 is characterized in that the 4th source electrode and this first metal wire overlapping have first contact hole, and electrically connects by this first contact hole; The 4th drain electrode has second contact hole with this second metal wire overlapping, and electrically connects by this second contact hole.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN200910007018A CN101794048A (en) | 2009-02-03 | 2009-02-03 | Display panel and maintenance method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN200910007018A CN101794048A (en) | 2009-02-03 | 2009-02-03 | Display panel and maintenance method thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN101794048A true CN101794048A (en) | 2010-08-04 |
Family
ID=42586822
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN200910007018A Pending CN101794048A (en) | 2009-02-03 | 2009-02-03 | Display panel and maintenance method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN101794048A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI684170B (en) * | 2018-03-15 | 2020-02-01 | 友達光電股份有限公司 | Electronic device |
-
2009
- 2009-02-03 CN CN200910007018A patent/CN101794048A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI684170B (en) * | 2018-03-15 | 2020-02-01 | 友達光電股份有限公司 | Electronic device |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN100576029C (en) | LCD panel and liquid crystal indicator with it | |
| JP5140999B2 (en) | Liquid crystal display | |
| CN101833200B (en) | Horizontal electric field type liquid crystal display device and manufacturing method thereof | |
| EP2797069B1 (en) | Active matrix substrate, display device, method for inspecting the active matrix substrate, and method for inspecting the display device | |
| KR102468366B1 (en) | Organic Light Emitting Diode Display Device | |
| US7701542B2 (en) | Liquid crystal display device with data switching thin film transistor for inspection and inspection method thereof | |
| CN112908227A (en) | Display device and method of manufacturing the same | |
| CN102722058B (en) | Liquid crystal array substrate, manufacturing method and repair method of liquid crystal array substrate | |
| JP2007298791A (en) | Liquid crystal display device and method for repairing its defect | |
| CN102998865A (en) | Array substrate, as well as manufacture method and display device thereof | |
| CN100444006C (en) | Thin film transistor array panel for display | |
| CN101799605B (en) | Pixel array | |
| US9405162B2 (en) | Active matrix display device with auxiliary repair line | |
| US7180564B2 (en) | In-plane-switching liquid crystal display for large pixel type | |
| JP2010145875A (en) | Liquid crystal display device and manufacturing method thereof | |
| US11930672B2 (en) | Display device | |
| CN110379387A (en) | Driving circuit, display module and display equipment | |
| CN218547885U (en) | <xnotran></xnotran> | |
| CN101408683B (en) | Display panel repairing method and display panel repaired by using the same | |
| US10168592B2 (en) | Display panel | |
| CN101794048A (en) | Display panel and maintenance method thereof | |
| CN101788739A (en) | Display panel repair method and display panel | |
| KR101157248B1 (en) | Mass production system checking structure of liquid crystal display device | |
| CN101943835A (en) | Repairing structure and repairing method for liquid-crystal display (LCD) panel | |
| KR101695025B1 (en) | Liquid crystal display and method of repairing the same |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C02 | Deemed withdrawal of patent application after publication (patent law 2001) | ||
| WD01 | Invention patent application deemed withdrawn after publication |
Application publication date: 20100804 |