CN101789791B - Broadband radio intermediate-frequency analogue/digital mixed signal processor - Google Patents
Broadband radio intermediate-frequency analogue/digital mixed signal processor Download PDFInfo
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Abstract
The invention discloses a broadband radio intermediate-frequency analogue/digital mixed signal processor, which comprises a broadband intermediate-frequency analogue front end connected with radio frequency equipment, an analogue/digital mixed signal processor connected with the broadband intermediate-frequency analogue front end, an external connection interface connected with the analogue/digital mixed signal processor and a clock allocation system, wherein the broadband intermediate-frequency analogue front end comprises a transmission channel, a receiving channel and an intermediate-frequency local oscillator; the analogue/digital mixed signal processor comprises an ADC, a DAC and a digital signal processing unit; a signal received by the radio frequency equipment is transmitted to the ADC through the receiving channel for analogue/digital conversion and then is transmitted to the digital signal processing unit for processing; and the signal which is processed by the digital signal processing unit and needs transmitting is subjected to digital/analogue conversion and then is transmitted to the radio frequency signal through the transmission channel for transmission. The broadband radio intermediate-frequency analogue/digital mixed signal processor has the characteristics of small volume, low power consumption, wide application range, reliable working performance and good signal processing effect, and can effectively overcome a plurality of defects and shortcomings existing in the conventional like products in China and other countries.
Description
Technical field
The invention belongs to wireless mobile communications signal processing technology field, especially relate to a kind of broadband radio intermediate-frequency analogue/digital mixed signal processor.
Background technology
Along with the development of information technology, radiotechnics obtains a wide range of applications, and software and radio technique has entered the stage of Digital Signal Processing so that radio signal is processed.From present domestic, overseas market, lack a kind of small-sized, low-power consumption, the universal and radio intermediate frequency analogue/digital mixed signal processing hardware platform that can carry out stackable expansion.Existing external product expensive (for example Britain Sundance) adopts the expensive technical scheme of intermediate frequency Direct Digital mostly; And home products is to be the custom-designed signal handling equipment of a certain application mostly, because of rather than a kind of general hardware platform.
In addition, existing domestic, same kind of products at abroad all provides the overall structure from the base band to the radio frequency, thereby has limited the range of application of product.Nowadays, more applications need a kind of broadband radio intermediate-freuqncy signal processor, so that the processing platform of the common hardware below the intermediate frequency to be provided, on this common hardware processing platform platform, the user can develop, verify the radio digital signal Processing Algorithm of oneself, comprise modulation /demodulation, synchronously, error correction and data subdivision connect, the user also can buy third-party IP core (IP) and come its application of rapid build; Such general hardware platform is required to have abundant outside expansion connecting interface simultaneously, connect with the convenient external signal treatment facilities such as main control system, information source (video, audio frequency, Ethernet etc.) of being connected with computer.
All in all, there is following shortcoming in existing similar products at home and abroad: 1) adopt the technical scheme of direct if digitization (mould that needs are expensive/number conversion chip ADC, high-speed figure Direct-conversion chip DDC and large capacity, high speed field programmable gate array chip FPGA) to cause product cost expensive; In fact, the high speed that high-speed ADC produces, a large amount of digitalized data are difficult to directly process for current in the world existing FPGA, therefore, also need the DDC process chip to come the down-sampling of settling signal to extract to reduce the signal data amount, although such hardware configuration has satisfied the concept requirement of software radio, lack versatility and the reproducibility used; 2) the upper and lower frequency conversion scheme of digital quadrature that proposes of existing like product has, signal too high to the FPGA resource occupation and processes the shortcomings such as limited bandwidth, under this scheme, leave for modulation, demodulation, synchronously, the resource of the more crucial signal processing module such as error correction is very limited, limited the range of application of product; 3) existing product adopts that digitlization down-conversion and band are logical to be owed Sampling techniques front end filter has been proposed requirements at the higher level, also will lose certain signal to noise ratio, needs highly sensitive receiver also inapplicable in using at some; 4) existing product is at equal Shortcomings in aspect such as volume, power consumption, engineering practicabilities.
Summary of the invention
Technical problem to be solved by this invention is for above-mentioned deficiency of the prior art, a kind of broadband radio intermediate-frequency analogue/digital mixed signal processor is provided, its volume is little, low in energy consumption and applied widely, reliable working performance, signal treatment effect are good, can effectively solve the existing cost of existing similar products at home and abroad expensive, lack versatility and the reproducibility used, number of drawbacks and the deficiency such as range of application is narrow, power consumption is high, engineering practicability is poor.
For solving the problems of the technologies described above, the technical solution used in the present invention is: a kind of broadband radio intermediate-frequency analogue/digital mixed signal processor is characterized in that: the analog/digital mixing signal processor that comprises the Wideband Intermediate Frequency AFE (analog front end) of joining with radio-frequency apparatus, joins with the Wideband Intermediate Frequency AFE (analog front end), join with the analog/digital mixing signal processor and the external connection interface section that is used for communicating with the external signal treatment facility and the interconnection system that joins with Wideband Intermediate Frequency AFE (analog front end), analog/digital mixing signal processor and external connection interface section respectively; Described Wideband Intermediate Frequency AFE (analog front end) comprises transmission channel, receive path and the intermediate frequency local oscillator of joining with transmission channel and receive path respectively; Described analog/digital mixing signal processor comprises A/D converter ADC, D/A converter DAC and the digital signal processing unit that joins with A/D converter ADC and D/A converter DAC respectively, and digital signal processing unit and external connection interface section are joined; The signal that described radio-frequency apparatus receives is delivered to digital signal processing unit again and is processed after receive path is delivered to A/D converter ADC and carries out mould/number conversion; The signal that needs after digital signal processing unit is processed to send is delivered to radio-frequency apparatus by transmission channel again and is sent after D/A converter DAC carries out D/A switch.
Described receive path comprises that the intermediate frequency that connects successively receives prime filter, intermediate frequency digital Auto Gain controller, intermediate frequency reception rear class filter, the quadrature demodulator that is applicable to the wide-band scope and base band receiving filter, intermediate frequency receives the prime filter and radio-frequency apparatus joins, base band receiving filter and A/D converter ADC join, and described intermediate frequency digital Auto Gain controller and intermediate frequency receive the rear class filter and join; Described transmission channel comprises the baseband transmission filter that connects successively, the quadrature modulator that can be applicable to the wide-band scope, intermediate frequency emission prime filter, the pre-gain amplifier of intermediate frequency and intermediate frequency transmission final stage filter, baseband transmission filter and D/A converter DAC join, and intermediate frequency transmission final stage filter and radio-frequency apparatus join; Described quadrature demodulator and quadrature modulator all join with intermediate frequency local oscillator.
Described intermediate frequency local oscillator comprises reference frequency source, voltage controlled oscillator, local oscillator output filter, local oscillator output driver and the local oscillator output power splitter that connects successively and the loop filter that joins with voltage controlled oscillator; The two ends of described loop filter join with input and the output of voltage controlled oscillator respectively, and two outputs of described local oscillator output power splitter join with quadrature demodulator and quadrature modulator respectively.
The DSP digital signal processor that described digital signal processing unit comprises FPGA field programmable gate array processing module, join with FPGA field programmable gate array processing module and the configuration circuit of FPGA field programmable gate array processing module, described configuration circuit joins with FPGA field programmable gate array processing module and DSP digital signal processor respectively, and described FPGA field programmable gate array processing module and DSP digital signal processor join with external connection interface section respectively.
Described configuration circuit comprises dynamic-configuration control circuit and the non-volatile Flash storage chip one, non-volatile Flash storage chip two and the non-volatile Flash storage chip three that join with the dynamic-configuration control circuit respectively, and the dynamic-configuration control circuit joins with FPGA field programmable gate array processing module and DSP digital signal processor respectively.
Described external connection interface section comprises Ethernet interface, RS422/485/232 interface and the Transistor-Transistor Logic level transmitting-receiving buffer interface that joins with FPGA field programmable gate array processing module and the multichannel buffer serial line interface that joins with the DSP digital signal processor.
Carry out two-way communication by external memory unit between described FPGA field programmable gate array processing module and DSP digital signal processor, described external memory unit joins with FPGA field programmable gate array processing module and DSP digital signal processor respectively.
The present invention compared with prior art has the following advantages:
1, versatility is good, applied widely: design of the present invention has taken into full account the requirement of radio communication, navigation, radar, radio measurement and control/various application occasions centering frequency word signal processors such as measurement, has a very strong scalability.At first, intermediate frequency range wide (50MHz-500MHz) can adapt to the requirement that large multi radio intermediate-freuqncy signal is processed; Secondly, the present invention can be by network interface, Transistor-Transistor Logic level, the RS422/485 expansion that superposes, when adopting network interface to expand can with the computer server seamless link, finished the tasks such as follow-up signal processing, demonstration, control by computer server; Again, the invention provides the AGC control range of the wide 90dB of reaching, precision reaches 1.5dB, provides to enrich external interface, can adapt to more applied environment.
2, system hardware structure modularization, Structured Design, Design of Hardware Architecture is simple, is easy to systemic-function adjustment and maintenance: the present invention is designed with dynamic configuration circuit CONF, is used for realizing the dynamic-configuration to FPGA.CONF adopts three configuring chip project organizations, can dynamically switch three kinds of FPGA hardware configuration engineerings, really realizes the dynamic-configuration ability of software radio.
3, owing to adopt the simulation quadrature frequency conversion, signal is directly moved Base-Band Processing, so just can thoroughly solve the shortcoming that aforesaid present product exists, need not be with the logical sampling of owing thereby reach, take a large amount of FPGA resources without the upper and lower frequency conversion of digital quadrature, needn't adopt high-speed figure Direct-conversion chip DDC and large capacity, high speed field programmable gate array chip FPGA, thereby also reach the properties of product of small-sized, low-power consumption, universal, stackable expansion.
4, reasonable in design, complete function, the Wideband Intermediate Frequency AFE (analog front end) is finished the functions such as the amplification, filtering, gain control, Up/Down Conversion of analog intermediate frequency signal, wherein transmission channel is finished intermediate frequency filtering and signal gain is amplified in advance, for the modulation scheme of using non-permanent envelope, in order to make radio-frequency (RF) power amplification performance maximal efficiency, intermediate-freuqncy signal must satisfy certain level requirement, so the signal of intermediate frequency transmission channel gains in advance to amplify and just is very important; To finish the control of intermediate frequency filtering and automatic gain for receive path, the modern broadband wireless communication system often requires large dynamic range, intermediate frequency automatic gain of the present invention adopts two-stage cascade, and the gain control range of 90dB can be provided, and control precision is less than 1.5dB.Signal after above-mentioned Wideband Intermediate Frequency AFE (analog front end) conditioning is connected to D/A converter (DAC) and A/D converter (ADC) after quadrature modulator and quadrature demodulator and low-pass analog filter, finish the conversion of analog to digital signal, digital signal processing algorithm is adopted in the processing of baseband signal, is finished by FPGA and DSP integration and cooperation.Wherein, FPGA field programmable gate array processing module can finish digital low-pass filtering, carrier synchronization, signal frame synchronously, sample value (employings) is synchronous and the function such as symbol synchronization, the DSP digital signal processor can finish information data framing, tear the functions such as frame processing, FEC encoding and decoding open.Adopt such processing structure can reduce performance requirement to the DSP digital signal processor, save cost, improve the data throughout of system.In addition, what the present invention adopted is the opening system structure, and the actual development person can be adjusted neatly according to the requirement of institute's applied environment.To sum up, the present invention can connect intermediate frequency simulation (50 Europe) signal from 50MHz to 500MH, and provide quadrature I the base band signal process bandwidth of Q two-way 60MHz, provide simultaneously the abundant external expansion interface such as Ethernet interface, RS422/485/232 interface.
In sum, volume of the present invention is little, low in energy consumption and applied widely, reliable working performance, the signal treatment effect is good, it is expensive effectively to solve the existing cost of existing similar products at home and abroad, lack versatility and the reproducibility used, range of application is narrow, front end filter is required high, volume is large, power consumption is high, number of drawbacks and the deficiencies such as engineering practicability is poor, it provides a kind of small-sized, low-power consumption and general radio intermediate frequency analogue/digital mixed signal processing hardware platform, direct 50 Europe interfaces and Digital Signal Processing parts and external connection interface section parts from the paramount intermediate frequency of Low Medium Frequency (50MHz) (500MHz) are provided, can be widely used in radio communication, navigation, radar digital signal processing, radio measurement and control is measured, the fields such as radio spectrum analysis monitoring.
Below by drawings and Examples, technical scheme of the present invention is described in further detail.
Description of drawings
Fig. 1 is circuit block diagram of the present invention.
Fig. 2 is circuit theory and the external wiring diagram of Wideband Intermediate Frequency AFE (analog front end) of the present invention.
Fig. 3 is circuit theory and the external wiring diagram of analog/digital mixing signal processor of the present invention and external connection interface section.
Fig. 4 is circuit theory and the external wiring diagram of FPGA field programmable gate array processing module configuration circuit of the present invention.
Description of reference numerals:
1-Wideband Intermediate Frequency AFE (analog front end); 1-1 one receive path; 1-11 one intermediate frequency receives the prime filter
The ripple device;
1-12-intermediate frequency numeral automatic torque-increasing 1-13-intermediate frequency receives rear class 1-14-quadrature demodulator;
The benefit controller; Filter;
1-15-base band receiving filter; The 1-2-intermediate frequency local oscillator; The 1-21-reference frequency source;
The 1-22-voltage controlled oscillator; The 1-23-loop filter; 1-24-local oscillator output filter;
1-25-local oscillator output driver; 1-26-local oscillator output work is divided the 1-3-transmission channel;
Device;
1-31-baseband transmission filter; The 1-32-quadrature modulator; The filter of 1-33-intermediate frequency emission prime
The ripple device;
The 1-34-intermediate frequency gains in advance and amplifies 1-35-intermediate frequency transmission final stage 2-analog/digital mixing signal
Device; Filter; Processor;
2-1-A/D converter ADC; 2-2-D/A converter 2-3-Digital Signal Processing is single
DAC; Unit;
The single 2-33-DSP digital signal of 2-31-FPGA field-programmable 2-32-exterior storage place
The gate array processing module; Unit; The reason device;
The 2-34-dynamic-configuration is controlled electric 2-35-configuration circuit; The non-volatile Flash of 2-36-deposits
The road; Storage chip one;
The non-volatile Flash 3-of the non-volatile Flash storage 2-38-of 2-37-external connection interface section;
Chip two; Storage chip three;
The 3-1-Ethernet interface; 3-2-RS422/485/232 3-3-TTL level transmitting-receiving buffering
Interface; Interface;
3-4-multichannel buffer serial interface 4-interconnection system; The 5-radio-frequency apparatus.
Mouthful;
Embodiment
As shown in Figure 1, the present invention includes the Wideband Intermediate Frequency AFE (analog front end) 1 of joining with radio-frequency apparatus 5, the analog/digital mixing signal processor 2 that joins with Wideband Intermediate Frequency AFE (analog front end) 1, join with analog/digital mixing signal processor 2 and the external connection interface section 3 that is used for communicating with the external signal treatment facility and the interconnection system 4 that joins with Wideband Intermediate Frequency AFE (analog front end) 1, analog/digital mixing signal processor 2 and external connection interface section 3 respectively.
In conjunction with Fig. 2, described Wideband Intermediate Frequency AFE (analog front end) 1 comprises transmission channel 1-3, receive path 1-1 and the intermediate frequency local oscillator 1-2 that joins with transmission channel 1-3 and receive path 1-1 respectively.The single 2-3 of Digital Signal Processing that described analog/digital mixing signal processor 2 comprises A/D converter ADC2-1, D/A converter DAC2-2 and joins with A/D converter ADC2-1 and D/A converter DAC2-2 respectively, digital signal processing unit 2-3 and external connection interface section 3 are joined.The signal that described radio-frequency apparatus 5 receives is delivered to the single 2-3 of Digital Signal Processing again and is processed after receive path 1-1 is delivered to A/D converter ADC2-1 and carries out mould/number conversion.The signal that needs to send after the single 2-3 of described Digital Signal Processing processes is delivered to radio-frequency apparatus 5 by transmission channel 1-3 again and is sent after D/A converter DAC2-2 carries out D/A switch.Described A/D converter ADC2-1, D/A converter DAC2-2 and digital signal processing unit 2-3 all join with interconnection system 4.
In the present embodiment, described receive path 1-1 comprises that the intermediate frequency that connects successively receives prime filter 1-11, intermediate frequency digital Auto Gain controller 1-12, intermediate frequency receives rear class filter 1-13, the quadrature demodulator 1-14 that is applicable to the wide-band scope and base band receiving filter 1-15, intermediate frequency receives prime filter 1-11 and radio-frequency apparatus 5 joins, base band receiving filter 1-15 and A/D converter ADC2-1 join, and described intermediate frequency digital Auto Gain controller 1-12 and intermediate frequency receive rear class filter 1-13 and join.Described transmission channel 1-3 comprises baseband transmission filter 1-31, the quadrature modulator 1-32 that can be applicable to the wide-band scope, intermediate frequency emission prime filter 1-33, the pre-gain amplifier 1-34 of intermediate frequency and the intermediate frequency transmission final stage filter 1-35 that connects successively, baseband transmission filter 1-31 and D/A converter DAC2-2 join, and intermediate frequency transmission final stage filter 1-35 and radio-frequency apparatus 5 join.Described quadrature demodulator 1-14 and quadrature modulator 1-32 all join with intermediate frequency local oscillator 1-2.
Described intermediate frequency local oscillator 1-2 comprises reference frequency source 1-21, voltage controlled oscillator 1-22, local oscillator output filter 1-24, local oscillator output driver 1-25 and the local oscillator output power splitter 1-26 that connects successively and the loop filter 1-23 that joins with voltage controlled oscillator 1-22.The two ends of described loop filter 1-23 join with input and the output of voltage controlled oscillator 1-22 respectively, and two outputs of described local oscillator output power splitter 1-26 join with quadrature demodulator 1-14 and quadrature modulator 1-32 respectively.
As shown in Figure 3, the DSP digital signal processor 2-33 that described digital signal processing unit 2-3 comprises FPGA field programmable gate array processing module 2-31, join with FPGA field programmable gate array processing module 2-31 and the configuration circuit 2-35 of FPGA field programmable gate array processing module 2-31, described configuration circuit 2-35 joins with FPGA field programmable gate array processing module 2-31 and DSP digital signal processor 2-33 respectively, and described FPGA field programmable gate array processing module 2-31 and DSP digital signal processor 2-33 join with external connection interface section 3 respectively.
In conjunction with Fig. 4, described configuration circuit 2-35 comprises dynamic-configuration control circuit 2-34 and non-volatile Flash storage chip one 2-36, non-volatile Flash storage chip two 2-37 and non-volatile Flash storage chip three 2-38 that join with dynamic-configuration control circuit 2-34 respectively, and dynamic-configuration control circuit 2-34 joins with FPGA field programmable gate array processing module 2-31 and DSP digital signal processor 2-33 respectively.Carry out two-way communication by external memory unit 2-32 between described FPGA field programmable gate array processing module 2-31 and DSP digital signal processor 2-33, described external memory unit 2-32 joins with FPGA field programmable gate array processing module 2-31 and DSP digital signal processor 2-33 respectively.
Described external connection interface section 3 comprises the Ethernet interface 3-1, the RS422/485/232 interface 3-2 that join with FPGA field programmable gate array processing module 2-31 and Transistor-Transistor Logic level transmitting-receiving buffer interface 3-3 and the multichannel buffer serial line interface 3-4 that joins with DSP digital signal processor 2-33.
The course of work of the present invention is: after described radio-frequency apparatus 5 receives analog intermediate frequency signal, first analog intermediate frequency signal is sent to receive path 1-1, and after above-mentioned analog intermediate frequency signal enters receive path 1-1, receive prime filter 1-11 through intermediate frequency first and select useful signal, again the selected useful signal that goes out is sent into the intermediate frequency digital Auto Gain controller 1-12 control adjustment of gaining, described intermediate frequency digital Auto Gain controller 1-12 can provide the gain control range of 90dB, and its control precision is less than 1.5dB, thereby it can play that to adjust late-class circuit be the effect that intermediate frequency receives rear class filter 1-13 input signal dynamic range, so that whole system also can work under high dynamic range; Subsequently, after the high-frequency signal that process intermediate frequency digital Auto Gain controller 1-12 carries out obtaining after the automatic gain control further receives rear class filter 1-13 by intermediate frequency, the intermediate frequency local oscillator signal that produces with local oscillator output power splitter 1-26 in quadrature demodulator 1-14 carries out mixing and carries out intermediate-freuqncy signal after the down-conversion quadrature demodulation of baseband signal, corresponding formation I, Q two-way digital orthogonal baseband signal, and with the I that obtains, Q two-way digital orthogonal baseband signal is delivered to base band receiving filter 1-15 and is carried out filtering processing (the high frequency images component that produces after the filtering quadrature demodulation) and corresponding generation demodulated base band signal; Afterwards, after by A/D converter ADC2-1 the demodulated base band signal that produces being converted to digital signal again, sending into again digital signal processing unit 2-3 and carry out analyzing and processing (comprising demodulation, despreading, fft analysis etc.) and obtain the code stream such as the information source such as video, audio frequency; The information source code stream that will obtain after will processing by external connection interface section 3 is at last delivered to the external signal treatment facility and is carried out further subsequent treatment and application.During actual the use, digital control approach is adopted in control to described intermediate frequency digital Auto Gain controller 1-12, specifically adopt FPGA field programmable gate array processing module 2-31 to control, FPGA field programmable gate array processing module 2-31 adopts such as parameters such as square law detection, pseudo code correlation peak values the intermediate frequency digital Auto Gain controller 1-12 of outside numerical control is carried out the level adjustment, and the adjustment of level can not make moderate progress to the signal to noise ratio of receiver in theory.
The advantage that adopts quadrature demodulator 1-14 to carry out quadrature demodulation is: can not only reduce rear class A/D converter ADC2-1 to the requirement of sampling clock frequency, can effectively reduce the instructions for use of base band receiving filter 1-15 simultaneously.Concrete reason is as follows: when adopting quadrature demodulator 1-14 to carry out quadrature demodulation, the IQ two-way baseband signal that quadrature frequency conversion produces is actually the Hilbert transform process of an analog signal, and real signal is transformed to its analytical form.And the analytical form of real signal has been expressed the full detail of signal, therefore can realize the Whole frequency band analysis under the A/D converter ADC2-1 sample frequency, rather than half half frequency range analysis of the sample frequency of anti-Qwest principle, simultaneously, the high frequency images component of quadrature demodulation after can the establishment demodulation, thus requirement to baseband filter reduced.
On the contrary, at first be converted to base-band analog signal by D/A converter DAC2-2 through the digital baseband signal that produces after the digital signal processing unit 2-3 analyzing and processing, and in this D/A switch process, can produce the high frequency images component of base band, in order to suppress the high frequency images component, the base-band analog signal that produces through D/A converter DAC2-2 conversion will pass through baseband transmission filter 1-31 filtering high frequency images component, and then sends into quadrature modulator 1-32 and carry out baseband signal to the up-conversion quadrature modulation conversion of intermediate-freuqncy signal; According to the present invention, adopt the quadrature modulation mode equally also establishment the image component after the modulation, having reduced centering takes place frequently and penetrates the requirement of prime filter 1-33 and intermediate frequency transmission final stage filter 1-35, in a lot of application scenarios, the level of its inner intermediate-freuqncy signal of 5 pairs of inputs of the radio-frequency apparatus that is connected with the present invention has requirement, in order to improve the scope of application of the present invention, also increased the pre-gain amplifier 1-34 of intermediate frequency of one-level adjustable gain, carry out adjustable gain control by the pre-gain amplifier 1-34 of intermediate frequency, can guarantee with radio frequency part to be that the power amplifier of radio-frequency apparatus 5 is operated in an optimum linear working point, fully improve the efficient of radio-frequency (RF) power amplification, this is for non-constant enveloped modulation, as: the OFDM modulation system is highly beneficial.Simultaneously, be the pre-gain amplifier 1-34 of intermediate frequency owing to adopt the numerical control adjustable gain, can avoid the loaded down with trivial details work of the analog circuit gain module debugging that must carry out in the traditional design.In addition, because radio signal adopts framing to send mostly, has different frame project organizations, some situation requires some signal in the frame is carried out power control, pilot power control such as frame, adopting the numerical control gain module is the neatly power of the interior unlike signal component of control frame of the pre-gain amplifier 1-34 of intermediate frequency, thereby the service efficiency of energy Effective Raise signal.
Among the described intermediate frequency local oscillator 1-2, voltage controlled oscillator 1-22 inside is integrated with phase discriminator, vibration output frequency behind the voltage controlled oscillator VCO frequency division among the described phase discriminator output voltage controlled oscillator 1-22 and the phase difference of reference frequency source 1-21 also produce phase discriminating pulse, produce the control voltage of control voltage controlled oscillator VCO after the phase discriminating pulse that produces is level and smooth through the low pass of loop filter 1-23, the frequency of oscillation of this control voltage control voltage controlled oscillator VCO in certain wave band, and so that the output frequency of voltage controlled oscillator VCO is the multiple of certain numerical value of reference frequency source 1-21, this numerical value can be little several times, also can be integral multiple.The frequency of oscillation source of voltage controlled oscillator VCO output is sent into local oscillator output driver 1-25 through local oscillator output filter 1-24 behind the local oscillator band pass filter filtering out of band components, local oscillator output driver 1-25 guarantees the sine wave sources of a 0-5dBm level of its output, outputs to respectively more afterwards quadrature demodulator 1-14 and the quadrature modulator 1-32 of receive path 1-1 and transmission channel 1-3 through local oscillator output power splitter 1-26.
Among the described digital signal processing unit 2-3, the physics that FPGA field programmable gate array processing module 2-31 finishes all signals is connected with logic, FPGA field programmable gate array processing module 2-31 passes through SDRAM simultaneously, the volatile memory device such as SRAM (being external memory unit 2-32) are crosslinked with DSP digital signal processor 2-33, wherein said external memory unit 2-32 is as outside extended menory equipment, share the data address space by FPGA field programmable gate array processing module 2-31 and DSP digital signal processor 2-33, realize both exchanges data.
In the actual use procedure, by the MII Interface realization exchanges data of standard, controlled by the agreement of FPGA field programmable gate array processing module 2-31 and DSP digital signal processor 2-33 co-treatment media Access Layer MAC between Ethernet interface 3-1 and the FPGA field programmable gate array processing module 2-31.The communication protocol of described RS422/485/232 interface 3-2 is realized by FPGA field programmable gate array processing module 2-31, can realize asynchronous and transmission link synchronous serial data.The configuration circuit 2-35 of described FPGA field programmable gate array processing module 2-31 is used for realizing FPGA field programmable gate array processing module 2-31 is carried out dynamic-configuration.
Among the described configuration circuit 2-35, non-volatile Flash storage chip one 2-36, non-volatile Flash storage chip two 2-37 and non-volatile Flash storage chip three 2-38 are three non-volatile Flash storage chips, store respectively three kinds of different allocation project files, by dynamic-configuration control circuit 2-34 above-mentioned three non-volatile Flash storage chips are carried out reading to finish the Dynamic Configuration Process to FPGA field programmable gate array processing module 2-31 during actual the use.Simultaneously, dynamic-configuration control circuit 2-34 and FPGA field programmable gate array processing module 2-31 dispensing unit join, in order to produce control sequential and the configuration status order index signal of FPGA field programmable gate array processing module 2-31 configuration.Described dynamic-configuration control circuit 2-34 also joins with DSP digital signal processor 2-33, is used for receiving the dynamic-configuration instruction that outer DSP digital signal processor 2-33 assigns.In the course of work, DSP digital signal processor 2-33 can dynamically switch by dynamic-configuration control circuit 2-34 the allocation project of FPGA field programmable gate array processing module 2-31 according to the current system state, really realizes the dynamic-configuration ability of software radio.
The above; it only is preferred embodiment of the present invention; be not that the present invention is imposed any restrictions, every any simple modification, change and equivalent structure of above embodiment being done according to the technology of the present invention essence changes, and all still belongs in the protection range of technical solution of the present invention.
Claims (6)
1. a broadband radio intermediate-frequency analogue/digital mixed signal processor is characterized in that: comprise the Wideband Intermediate Frequency AFE (analog front end) (1) of joining with radio-frequency apparatus (5), the analog/digital mixing signal processor (2) that joins with Wideband Intermediate Frequency AFE (analog front end) (1), the external connection interface section (3) of joining with analog/digital mixing signal processor (2) and being used for communicating with the external signal treatment facility and respectively with Wideband Intermediate Frequency AFE (analog front end) (1), the interconnection system (4) that analog/digital mixing signal processor (2) and external connection interface section (3) are joined; Described Wideband Intermediate Frequency AFE (analog front end) (1) comprises transmission channel (1-3), receive path (1-1) and the intermediate frequency local oscillator (1-2) of joining with transmission channel (1-3) and receive path (1-1) respectively; Described analog/digital mixing signal processor (2) comprises A/D converter ADC (2-1), D/A converter DAC (2-2) and the digital signal processing unit (2-3) that joins with A/D converter ADC (2-1) and D/A converter DAC (2-2) respectively, and digital signal processing unit (2-3) joins with external connection interface section (3); The signal that described radio-frequency apparatus (5) receives is delivered to digital signal processing unit (2-3) again and is processed after receive path (1-1) is delivered to A/D converter ADC (2-1) and carries out mould/number conversion; The signal that needs after digital signal processing unit (2-3) is processed to send is delivered to radio-frequency apparatus (5) by transmission channel (1-3) again and is sent after D/A converter DAC (2-2) carries out D/A switch; Described receive path (1-1) comprises that the intermediate frequency that connects successively receives prime filter (1-11), intermediate frequency digital Auto Gain controller (1-12), intermediate frequency receives rear class filter (1-13), be applicable to quadrature demodulator (1-14) and the base band receiving filter (1-15) of wide-band scope, intermediate frequency receives prime filter (1-11) and joins with radio-frequency apparatus (5), base band receiving filter (1-15) joins with A/D converter ADC (2-1), and described intermediate frequency digital Auto Gain controller (1-12) receives rear class filter (1-13) with intermediate frequency and joins; Described transmission channel (1-3) comprises the baseband transmission filter (1-31) that connects successively, the quadrature modulator (1-32) that can be applicable to the wide-band scope, intermediate frequency emission prime filter (1-33), the pre-gain amplifier of intermediate frequency (1-34) and intermediate frequency transmission final stage filter (1-35), baseband transmission filter (1-31) joins with D/A converter DAC (2-2), and intermediate frequency transmission final stage filter (1-35) joins with radio-frequency apparatus (5); Described quadrature demodulator (1-14) and quadrature modulator (1-32) all join with intermediate frequency local oscillator (1-2).
2. according to broadband radio intermediate-frequency analogue/digital mixed signal processor claimed in claim 1, it is characterized in that: described intermediate frequency local oscillator (1-2) comprises reference frequency source (1-21), voltage controlled oscillator (1-22), local oscillator output filter (1-24), local oscillator output driver (1-25) and the local oscillator output power splitter (1-26) that connects successively and the loop filter (1-23) that joins with voltage controlled oscillator (1-22); The two ends of described loop filter (1-23) join with input and the output of voltage controlled oscillator (1-22) respectively, and two outputs of described local oscillator output power splitter (1-26) join with quadrature demodulator (1-14) and quadrature modulator (1-32) respectively.
3. according to claim 1 or 2 described broadband radio intermediate-frequency analogue/digital mixed signal processors, it is characterized in that: described digital signal processing unit (2-3) comprises FPGA field programmable gate array processing module (2-31), the DSP digital signal processor (2-33) that joins with FPGA field programmable gate array processing module (2-31) and the configuration circuit (2-35) of FPGA field programmable gate array processing module (2-31), described configuration circuit (2-35) joins with FPGA field programmable gate array processing module (2-31) and DSP digital signal processor (2-33) respectively, and described FPGA field programmable gate array processing module (2-31) and DSP digital signal processor (2-33) join with external connection interface section (3) respectively.
4. according to broadband radio intermediate-frequency analogue/digital mixed signal processor claimed in claim 3, it is characterized in that: described configuration circuit (2-35) comprises dynamic-configuration control circuit (2-34) and the non-volatile Flash storage chip one (2-36) that joins with dynamic-configuration control circuit (2-34) respectively, non-volatile Flash storage chip two (2-37) and non-volatile Flash storage chip three (2-38), dynamic-configuration control circuit (2-34) join with FPGA field programmable gate array processing module (2-31) and DSP digital signal processor (2-33) respectively.
5. according to broadband radio intermediate-frequency analogue/digital mixed signal processor claimed in claim 3, it is characterized in that: described external connection interface section (3) comprises Ethernet interface (3-1), RS422/485/232 interface (3-2) and the Transistor-Transistor Logic level transmitting-receiving buffer interface (3-3) that joins with FPGA field programmable gate array processing module (2-31) and the multichannel buffer serial line interface (3-4) that joins with DSP digital signal processor (2-33).
6. according to broadband radio intermediate-frequency analogue/digital mixed signal processor claimed in claim 3, it is characterized in that: carry out two-way communication by external memory unit (2-32) between described FPGA field programmable gate array processing module (2-31) and DSP digital signal processor (2-33), described external memory unit (2-32) joins with FPGA field programmable gate array processing module (2-31) and DSP digital signal processor (2-33) respectively.
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| DE102010046187B4 (en) * | 2010-09-23 | 2012-08-30 | Atmel Automotive Gmbh | Circuit for analog-to-digital conversion |
| CN102412841A (en) * | 2011-12-16 | 2012-04-11 | 中船重工（武汉）凌久电子有限责任公司 | High-precision band-limited signal digital-to-analog converter and using method thereof |
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