CN101789449A - Semiconductor assembly structure and manufacturing method thereof - Google Patents
Semiconductor assembly structure and manufacturing method thereof Download PDFInfo
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- CN101789449A CN101789449A CN201010003239A CN201010003239A CN101789449A CN 101789449 A CN101789449 A CN 101789449A CN 201010003239 A CN201010003239 A CN 201010003239A CN 201010003239 A CN201010003239 A CN 201010003239A CN 101789449 A CN101789449 A CN 101789449A
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Abstract
The invention provides a semiconductor assembly structure and a manufacturing method thereof. The structure comprises a substrate, an oxide semiconductor transistor and a protection layer containing free hydrogen; wherein a grid electrode is positioned on the substrate, a grid dielectric layer covers the grid electrode, a source electrode is positioned on the grid dielectric layer, and a drain electrode is positioned on the grid dielectric layer and provided with a channel spacing relative to the source electrode; the oxide semiconductor layer is positioned on the grid dielectric layer, the source electrode and the drain electrode and between the source electrode and the drain electrode and electrically connected with the source electrode and the drain electrode; the protection layer covers an oxide semiconductor layer, the source electrode and the drain electrode; wherein the protection layer is provided with a groove, and the groove encloses the oxide semiconductor layer.
Description
[technical field]
The invention relates to a kind of oxide semi conductor transistor and manufacture method thereof, and particularly relevant for a kind of thin-film transistor array and manufacture method thereof of display floater.
[background technology]
For adopting for example indium gallium zinc oxide (InGaZnO of oxide semiconductor, IGZO) (for example as the semiconductor assembly structure of channel layer material, thin-film transistor), channel layer is subjected to the influence of assembly surrounding atmosphere (for example SiH4 gas that uses in the processing procedure of silicon oxide layer or silicon-nitride layer) easily, causes component characteristic to change.For example; indium gallium zinc oxide layer is if contact with the rete that contains free hydrogen (for example gate dielectric and protective layer); assembly is behind long-time high annealing (anneal); the hydrogen that contains in the rete of free hydrogen can diffuse in the indium gallium zinc oxide layer; make the characteristic of indium gallium zinc oxide layer to become and relatively be partial to conduction state; that is the oxygen in the indium gallium zinc oxide layer can become oxygen by free hydrogen reduction and lack (oxygen vacancies) and make conductivity improve, and then makes critical voltage (threshold voltage) the deflection negative pressure of thin-film transistor.
[summary of the invention]
Purpose of the present invention is providing a kind of semiconductor assembly structure exactly, has preferable component characteristic.
A further object of the present invention provides a kind of manufacture method of semiconductor assembly structure, to improve the component characteristic of semiconductor assembly structure.
A kind of semiconductor assembly structure that one embodiment of the invention proposes, second dielectric layer that comprises substrate, gate electrode, contains first dielectric layer, source electrode, drain electrode, the oxide semiconductor layer of free hydrogen and contain free hydrogen.Gate electrode is positioned in the substrate, the first dielectric layer cover gate electrode, source electrode is positioned on first dielectric layer, drain electrode is positioned on first dielectric layer and with respect to source electrode and has a channel distance, oxide semiconductor layer is positioned at first dielectric layer, on source electrode and the drain electrode and comprise between source electrode and drain electrode, oxide semiconductor layer can further electrically connect source electrode and drain electrode, the second dielectric layer capping oxide semiconductor layer, source electrode and drain electrode, second dielectric layer has groove, and this groove is around oxide semiconductor layer.
In one embodiment of this invention, above-mentioned oxide semiconductor layer comprises indium gallium zinc oxide (IGZO).
In one embodiment of this invention, the first above-mentioned dielectric layer comprises second groove, connects first groove, and exposes the part of grid pole electrode of bottom.
In one embodiment of this invention, above-mentioned semiconductor assembly structure more comprises the 3rd dielectric layer, is positioned on second dielectric layer and inserts first groove and second groove.
In one embodiment of this invention, the 3rd above-mentioned dielectric layer comprises polyimide (polyimide).
In one embodiment of this invention, above-mentioned semiconductor assembly structure more comprises patterned transparent conductive layer, is positioned on second dielectric layer and inserts first groove and second groove.
In one embodiment of this invention, the material of above-mentioned patterned transparent conductive layer comprises indium tin oxide (ITO).
In one embodiment of this invention, above-mentioned patterned transparent conductive layer is passed first groove and is electrically contacted gate electrode with second groove.
In one embodiment of this invention, the first above-mentioned groove comprises the disjunct each other first sub-opening and the second sub-opening, and the first sub-opening and the second sub-opening are arranged at the relative both sides of oxide semiconductor layer respectively.
In one embodiment of this invention, the free hydrogen content of the second above-mentioned dielectric layer is higher than the free hydrogen content of first dielectric layer.
A kind of semiconductor assembly structure that yet another embodiment of the invention proposes comprises substrate and is formed at suprabasil transistor; This transistor comprises gate electrode, source electrode, drain electrode, oxide semiconductor layer, gate dielectric and the protective layer that contains free hydrogen.Gate electrode is positioned in the substrate; source electrode and drain electrode all are positioned in the substrate and have a channel separation between the two; oxide semiconductor layer comprises between source electrode and drain electrode and electrically connects source electrode and drain electrode respectively; gate dielectric is arranged between gate electrode and oxide semiconductor layer, source electrode and the drain electrode, and protective layer is positioned on gate electrode, gate dielectric, source electrode, drain electrode and the oxide semiconductor layer.Wherein, gate dielectric and protective layer one at least have groove, this groove be positioned at oxide semiconductor layer the periphery and around oxide semiconductor layer.
Further embodiment of this invention proposes a kind of manufacture method of semiconductor assembly structure, comprises step: form gate electrode in substrate; Formation contains first dielectric layer of free hydrogen with the cover gate electrode; Form source electrode and drain electrode on first dielectric layer, have a channel separation between source electrode and the drain electrode; Form oxide semiconductor layer on first dielectric layer, source electrode, the drain electrode and comprise between source electrode and drain electrode; Formation contains second dielectric layer of free hydrogen on first dielectric layer, oxide semiconductor layer, source electrode and drain electrode; And etching second dielectric layer is to form groove at least, and this groove is around oxide semiconductor layer.
In one embodiment of this invention, the step of above-mentioned second dielectric layer of etching at least comprises: utilize gate electrode as etch stop layer, second dielectric layer and first dielectric layer are worn in etching in regular turn.
In one embodiment of this invention, the manufacture method of above-mentioned semiconductor assembly structure more comprises step: form the 3rd dielectric layer on second dielectric layer, and insert in the groove.
In one embodiment of this invention, the manufacture method of above-mentioned semiconductor assembly structure more comprises step: form transparency conducting layer on second dielectric layer, and insert in the groove.In addition, transparency conducting layer can pass groove and gate electrode electrically contact mutually.
The embodiment of the invention is by to being less than groove diffuses to oxide semiconductor layer with the cut-out free hydrogen path being set in the second dielectric layer/protective layer that contains free hydrogen; oxide semiconductor layer can not reduced by free hydrogen or reduced by slight free hydrogen; thereby the material property of oxide semiconductor layer can be kept in the manufacture process of semiconductor assembly structure, thereby the semiconductor assembly structure that the embodiment of the invention proposes can have preferable device performance.
For above and other objects of the present invention, feature and advantage can be become apparent, preferred embodiment cited below particularly, and cooperate appended graphicly, be described in detail below.
[description of drawings]
Fig. 1 illustrates the partial schematic diagram for a kind of semiconductor assembly structure that is relevant to the embodiment of the invention.
Fig. 2 illustrates and is the cutaway view along II-II ' line among Fig. 1.
Fig. 3 illustrates the cutaway view for a kind of semiconductor assembly structure that is relevant to yet another embodiment of the invention.
Fig. 4 illustrates the cutaway view for a kind of semiconductor assembly structure that is relevant to further embodiment of this invention.
Fig. 5 A to Fig. 5 E illustrates the manufacturing process for the manufacture method of a kind of semiconductor assembly structure that is relevant to embodiment of the invention proposition.
Fig. 6 shows the voltage of the semiconductor assembly structure that is relevant to the embodiment of the invention and comparative example and the graph of a relation of electric current.
[primary clustering symbol description]
10,20: curve
30: semiconductor assembly structure
32: substrate
36: transistor
361,363: groove
361a, 361b: sub-opening
364: gate dielectric
366: oxide semiconductor layer
368: protective layer
369A: dielectric layer
369B: patterned transparent conductive layer
D: drain electrode
G: gate electrode
L: channel separation
S: source electrode
[embodiment]
Hereinafter according to semiconductor assembly structure of the present invention and manufacture method thereof, cooperate appended graphic elaborating especially exemplified by embodiment, but the embodiment that is provided not is the scope that contains in order to restriction the present invention, and that the method flow step is described is non-in order to limit the order of its execution, any execution flow process that reconfigures by method step, the method with impartial effect that produces is all the scope that the present invention is contained.Wherein graphic only for the purpose of description, do not map according to life size.
See also Fig. 1 and Fig. 2, Fig. 1 shows the partial schematic diagram of a kind of semiconductor assembly structure that is relevant to the embodiment of the invention, and Fig. 2 illustrates and is the cutaway view along II-II ' line among Fig. 1.Wherein, be the clear relative position that demonstrates each assembly, the oxide semiconductor layer of Fig. 1 366 illustrates with perspective fashion, and so in fact oxide semiconductor layer 366 need not be limited as transparent material.
As shown in Figure 1, semiconductor assembly structure 30 comprises substrate 32 and is formed at transistor 36 in the substrate 32, and in present embodiment, transistor 36 has groove 361 and 363.Please in the lump with reference to figure 1 and Fig. 2, transistor 36 comprises gate electrode G, gate dielectric 364, source electrode S, drain electrode D, oxide semiconductor layer 366 and protective layer 368.Wherein, gate dielectric 364 can comprise for example combination of Si oxide, silicon nitride or previous materials of dielectric material with protective layer 368; and former thereby may contain free hydrogen because of processing procedure, especially the free hydrogen content in the protective layer 368 generally can be higher than the free hydrogen content in the gate dielectric 364.
Hold above-mentionedly, gate electrode G is positioned in the substrate 32, gate dielectric 364 cover gate electrode G, and source electrode S is positioned on the gate dielectric 364, and drain electrode D is positioned on the gate dielectric 364 and with respect to source electrode S and has channel separation L.Groove 363 is arranged in gate dielectric 364 and comprises disjunct each other two sub-openings (figure does not indicate), and this two sub-opening is divided into the relative both sides of oxide semiconductor layer 366; Moreover groove 363 exposes the part of grid pole electrode G of bottom; In addition, groove 363 be positioned at oxide semiconductor layer 366 the periphery and around oxide semiconductor layer 366.
In other embodiment; because the free hydrogen content in the gate dielectric 364 is relatively low; component characteristic influence to semiconductor assembly structure 30 is less relatively; therefore to the less demanding application of the component characteristic of semiconductor assembly structure 30; or under the extremely low situation of the free hydrogen content in the gate dielectric 364, can only in protective layer 368, form groove 361 and in gate dielectric 364, do not form groove 363.
In other embodiment, as shown in Figure 3, the semiconductor assembly structure 30 that present embodiment proposes can more comprise dielectric layer 369A, is positioned on the protective layer 368 and inserts groove 361 and 363; At this, dielectric layer 369A is as the packing material of groove 361 and 363, and it selects the material polyimide (polyimide) for example that does not contain free hydrogen for use.In the present embodiment, when semiconductor assembly structure 30 is applied to Thin Film Transistor-LCD (TFT-LCD), the formation of the convenient follow-up pixel electrode of the formation of dielectric layer 369A.
In other embodiment; as shown in Figure 4; the semiconductor assembly structure 30 that the embodiment of the invention proposes also can more comprise patterned transparent conductive layer 369B; be positioned on the protective layer 368 and insert groove 361 and 363, the material of patterned transparent conductive layer 369B can be selected indium tin oxide or other similar material for use.At this moment, patterned transparent conductive layer 369B passes that groove 361 and 363 electrically contacts with gate electrode G and as the top grid electrode of transistor 36, and gate electrode G is then as the bottom grid electrode of transistor 36; In other words, Ci Shi transistor 36 is a kind of double gate transistor.In other embodiment, patterned transparent conductive layer 369B of the present invention also can only insert in groove 361 and 363, and need not be covered in source electrode S and drain electrode D top, that is only in groove 361 and 363, insert patterned transparent conductive layer 369B and do not form double-grid structure.
Specifically describe the manufacture method of a kind of semiconductor assembly structure be relevant to the embodiment of the invention below in conjunction with Fig. 5 A to Fig. 5 E, Fig. 5 A to Fig. 5 E shows the manufacturing process of the semiconductor assembly structure that the embodiment of the invention proposes.
Shown in Fig. 5 A, prior to forming gate electrode G in the substrate 32.Gate electrode G can have any high conductive material, for example is metal level, and substrate 32 can have any high light transmissive material, for example is glass substrate or acryl substrate.
Shown in Fig. 5 B, go up in gate electrode G thereafter and form gate dielectric 364, gate dielectric 364 cover gate electrode G, and its material can be the combination of Si oxide, silicon nitride, silicon-oxygen nitride or previous materials; Owing to the processing procedure reason, for example in processing procedure, adopt SiH4 gas as the silicon source, can contain free hydrogen usually in the gate dielectric 364.
Shown in Fig. 5 C, then on gate dielectric 364, be formed with source electrode S and drain electrode D, have channel separation L between source electrode S and the drain electrode D.
Shown in Fig. 5 D, on gate dielectric 364, source electrode S and drain electrode D, be formed with oxide semiconductor layer 366, and oxide semiconductor layer 366 is also between source electrode S and drain electrode D.In addition, oxide semiconductor layer 366 and source electrode S and drain electrode D electrically connect and between source electrode S and drain electrode D formation length be the channel layer of L.At this, the material of oxide semiconductor layer 366 can be selected the combination of indium gallium zinc oxide, other oxygen metal compound semiconductor materials or previous materials for use.
Shown in Fig. 5 E, on gate dielectric 364, oxide semiconductor layer 366, source electrode S and drain electrode D, be formed with protective layer 368.The material of protective layer 368 can be selected the combination of Si oxide, silicon nitride, silicon-oxygen nitride or previous materials for use; Owing to the processing procedure reason, for example in processing procedure, adopt SiH4 gas as the silicon source, can contain free hydrogen usually in the protective layer 368, and the content of free hydrogen is usually above the free hydrogen content of gate dielectric 364.
Afterwards, be etch stop layer with gate electrode G, etch protection layer 368 and gate dielectric 364 in regular turn are to form groove 361 and form groove 363 in gate dielectric 364 in protective layer 368; Groove 361 links to each other with groove 363 and around oxide semiconductor layer 366, thereby makes semiconductor assembly structure 30 as shown in Figure 2.Need to prove that at this manufacture method of the semiconductor assembly structure that the embodiment of the invention proposes is etch protection layer 368 and form groove 361 only also.
In other embodiment, the manufacture method of the semiconductor assembly structure that the embodiment of the invention proposes also can form another dielectric layer on protective layer 368, and inserts in groove 361 and/or the groove 363, thereby can make structure as shown in Figure 3.
In other embodiment; the manufacture method of the semiconductor assembly structure that the embodiment of the invention proposes also can on protective layer 368, form transparency conducting layer and insert groove 361 and/or groove 363 in, after transparency conducting layer is carried out patterning, can get structure as shown in Figure 4.
See also Fig. 6, Fig. 6 shows the voltage (V) of the semiconductor assembly structure that is relevant to the embodiment of the invention and comparative example and the graph of a relation of electric current (I).Wherein, the difference of the semiconductor assembly structure of the embodiment of the invention and the semiconductor assembly structure of comparative example is; have groove 361,363 in the gate dielectric 364 of the embodiment of the invention and the protective layer 368, do not have groove in the gate dielectric of comparative example and the protective layer around oxide semiconductor layer around oxide semiconductor layer.The voltage of the semiconductor assembly structure of the embodiment of the invention and the relation curve of electric current are curve 10, and the relation curve of the voltage of the semiconductor assembly structure of comparative example and electric current is a curve 20.
As shown in Figure 6, the semiconductor assembly structure of comparative example has bigger leakage current (I
Off), and critical voltage (V
Th) the deflection negative value, and critical voltage is not obvious, so assembly is electrically more undesirable.That compares is following, and the critical voltage of semiconductor assembly structure of the present invention levels off to 0V, and have the preferable subcritical amplitude of oscillation (sub threshold swing, S.S.).This is because the embodiment of the invention can be provided with groove in the protective layer that contains free hydrogen; so oxide semiconductor layer does not subject to the free hydrogen reduction; therefore can maintain approaching semi-conductive state, therefore semiconductor assembly structure of the present invention has preferable semiconductor subassembly characteristic.
In sum; semiconductor assembly structure that the embodiment of the invention proposes and manufacture method thereof are by to being less than in the protective layer that contains free hydrogen groove being set; diffuse to the path of oxide semiconductor layer with the cut-out free hydrogen; oxide semiconductor layer can not reduced by free hydrogen or reduced by slight free hydrogen; thereby the material property of oxide semiconductor layer can be kept in the manufacture process of semiconductor assembly structure, thereby the component characteristic of the semiconductor assembly structure that the embodiment of the invention proposes can be improved.
In addition, anyly have the knack of this skill person and also can do suitably change semiconductor assembly structure and manufacture method thereof that the above embodiment of the present invention proposes, for example suitably change the position of oxide semiconductor layer, oxide semiconductor layer is arranged at source electrode electrically connects or the like mutually with the bottom of drain electrode and with source electrode and drain electrode.
Though the present invention discloses as above with preferred embodiment; right its is not in order to limit the present invention; anyly have the knack of this skill person; without departing from the spirit and scope of the present invention; when can doing a little change and retouching, so protection scope of the present invention is as the criterion when looking accompanying the claim person of defining.
Claims (20)
1. semiconductor assembly structure comprises:
One substrate;
One gate electrode is positioned in this substrate;
One contains first dielectric layer of free hydrogen, covers this gate electrode;
The one source pole electrode is positioned on this first dielectric layer;
One drain electrode is positioned on this first dielectric layer, has a channel separation with respect to this source electrode;
The monoxide semiconductor layer is positioned on this first dielectric layer, this source electrode and this drain electrode, and between this source electrode and this drain electrode, this oxide semiconductor layer electrically connects this source electrode and this drain electrode; And
One contains second dielectric layer of free hydrogen, covers this oxide semiconductor layer, this source electrode and this drain electrode, and wherein this second dielectric layer has one first groove, and this first groove is around this oxide semiconductor layer.
2. semiconductor assembly structure according to claim 1 is characterized in that, this oxide semiconductor layer comprises indium gallium zinc oxide.
3. semiconductor assembly structure according to claim 1 is characterized in that, this first dielectric layer comprises one second groove, connects this first groove, and exposes this gate electrode of part of bottom.
4. semiconductor assembly structure according to claim 3 is characterized in that, more comprises one the 3rd dielectric layer, is positioned on this second dielectric layer and inserts this first groove and this second groove.
5. semiconductor assembly structure according to claim 4 is characterized in that the 3rd dielectric layer comprises polyimide.
6. semiconductor assembly structure according to claim 3 is characterized in that, more comprises a patterned transparent conductive layer, is positioned on this second dielectric layer and inserts this first groove and this second groove.
7. semiconductor assembly structure according to claim 6 is characterized in that the material of this patterned transparent conductive layer comprises indium tin oxide.
8. semiconductor assembly structure according to claim 6 is characterized in that, this patterned transparent conductive layer is passed this first groove and electrically contacted this gate electrode with second groove.
9. semiconductor assembly structure according to claim 1, it is characterized in that, this first groove comprises the disjunct each other first sub-opening and the second sub-opening, and this first sub-opening and the second sub-opening are arranged at the relative both sides of this oxide semiconductor layer respectively.
10. semiconductor assembly structure according to claim 1 is characterized in that, the free hydrogen content of this second dielectric layer is greater than the free hydrogen content of this first dielectric layer.
11. a semiconductor assembly structure comprises:
One substrate;
One transistor is positioned in this substrate, and this transistor comprises:
One gate electrode is positioned in this substrate;
An one source pole electrode and a drain electrode are positioned in this substrate, have a channel separation between this source electrode and this drain electrode;
The monoxide semiconductor layer between this source electrode and this drain electrode, and electrically connects this source electrode and this drain electrode respectively; And
One gate dielectric is arranged between this gate electrode and this oxide semiconductor layer, this source electrode and this drain electrode; And
One contains the protective layer of free hydrogen, is positioned on this gate electrode, this gate dielectric, this source electrode, this drain electrode and this oxide semiconductor layer;
Wherein, this gate dielectric and this protective layer one at least have a groove, be positioned at this oxide semiconductor layer the periphery and around this oxide semiconductor layer.
12. semiconductor assembly structure according to claim 11 is characterized in that, this oxide semiconductor layer comprises indium gallium zinc oxide.
13. semiconductor assembly structure according to claim 11 is characterized in that, more comprises polyimide or indium tin oxide, is arranged in this groove.
14. semiconductor assembly structure according to claim 11 is characterized in that, this groove comprises disjunct each other first opening and second opening, and this first opening and second opening are arranged at the relative both sides of this oxide semiconductor layer respectively.
15. semiconductor assembly structure according to claim 11 is characterized in that, this groove runs through this gate dielectric and this protective layer.
16. the manufacture method of a semiconductor assembly structure comprises:
Form a gate electrode in a substrate;
Form one and contain first dielectric layer of free hydrogen to cover this gate electrode;
Form an one source pole electrode and a drain electrode on this first dielectric layer, have a channel separation between this source electrode and this drain electrode;
Form the monoxide semiconductor layer on this first dielectric layer, this source electrode and this drain electrode, and between this source electrode and this drain electrode;
Form one second dielectric layer on this first dielectric layer, this oxide semiconductor layer, this source electrode and this drain electrode; And
At least this second dielectric layer of etching to be forming a groove, and this groove is around this oxide semiconductor layer.
17. the manufacture method of semiconductor assembly structure according to claim 16 is characterized in that, the step of this second dielectric layer of etching comprises at least: utilize this gate electrode as etch stop layer, this second dielectric layer and this first dielectric layer are worn in etching in regular turn.
18. the manufacture method of semiconductor assembly structure according to claim 16 is characterized in that, more comprises step:
Form one the 3rd dielectric layer on this second dielectric layer, and insert in this groove.
19. the manufacture method of semiconductor assembly structure according to claim 16 is characterized in that, more comprises step:
Form a transparency conducting layer on this second dielectric layer, and insert in this groove.
20. the manufacture method of semiconductor assembly structure according to claim 19 is characterized in that, this transparency conducting layer passes this groove and electrically contacts this gate electrode.
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| CN109003991A (en) * | 2018-08-01 | 2018-12-14 | 京东方科技集团股份有限公司 | Array substrate and preparation method thereof and display panel |
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| CN109003991A (en) * | 2018-08-01 | 2018-12-14 | 京东方科技集团股份有限公司 | Array substrate and preparation method thereof and display panel |
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