CN101789034B - Method and apparatus for constructing a canonical representation - Google Patents
Method and apparatus for constructing a canonical representation Download PDFInfo
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- CN101789034B CN101789034B CN200910208097.4A CN200910208097A CN101789034B CN 101789034 B CN101789034 B CN 101789034B CN 200910208097 A CN200910208097 A CN 200910208097A CN 101789034 B CN101789034 B CN 101789034B
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/32—Circuit design at the digital level
- G06F30/33—Design verification, e.g. functional simulation or model checking
- G06F30/3323—Design verification, e.g. functional simulation or model checking using formal methods, e.g. equivalence checking or property checking
Abstract
The invention discloses a method and apparatus for constructing a canonical representation. Some embodiments provide systems and techniques to facilitate construction of a canonical representation (CR) which represents a logical combination of a set of logical functions. During operation, the system can receive a CR size limit. Next, the system can construct a set of CRs based on the set of logical functions, wherein each CR in the set of CRs represents a logical function in the set of logical functions. The system can then combine a subset of the set of CRs to obtain a combined CR. Next, the system can identify a problematic CR which when combined with the combined CR causes the CR-size limit to be exceeded. The system can then report the problematic CR and/or a logical function associated with the problematic CR to a user, thereby helping the user to identify an error in the set of logical functions.
Description
Technical field
Present disclosure mainly relates to electric design automation.Specifically, present disclosure relates to the method and apparatus of the canonical representation for constructing such as binary decision diagram.
Background technology
The development of design and verification tool has made developing rapidly of computing equipment become possibility.In fact, such instrument is not had may will to design and verify ubiquitous complicated integrated circuit in computing equipment of today hardly.
Constrained random simulation method as a kind of alternative of emulation based on orientation test more and more at large for the functional verification to somewhat complex design.In constrained random simulation method, generate random vector with some operation constraint of satisfied design.Usually these constraints are appointed as the part of test board program.Test board automation tools (TBA) uses test board program to generate RANDOM SOLUTION for stochastic variable set, thus meets the constrain set to stochastic variable set.Then these RANDOM SOLUTION can be used for as design (DUV) to be verified generates effective random stimulus.Use emulation tool to emulate this stimulation, and in test board program, usually check that simulation result is with function for monitoring coverage, provide the degree of confidence about verification quality and integrality to measure thus.
Constraint solver is commonly used to generate the random vector meeting constrain set.The basic function of constraint solver is used for solving following constraint satisfaction problemx: given variables collection and constrain set, for variables collection finds the value set meeting constrain set.For asking better software maintenance and quality, these solutions that constraint solver generates need to reproduce and to determine.In addition, because user requires the good coverage for random simulation usually, so constrained solution also needs to be uniformly distributed.
Regrettably, constraint satisfaction problemx is NP-complete (NP is complete) problem.On the other hand, the logical simulation convergent-divergent linearly along with the scale of design usually.As a result, formation speed is stimulated usually to lag behind the speed using stimulation in simulations far away.Therefore, the performance improving constraint solver is wished, because this can significantly improve the overall performance of constrained random stimulation tool.
Summary of the invention
Some embodiments of the present invention are provided for the system and the technology that contribute to the canonical representation (CR) constructing the logical function can expressed as the combination of logical function set.
During operation, system can receive the restriction of CR scale.Then, system can be gathered by logic-based collection of functions incompatible structure CR, the logical function in each CR presentation logic function set wherein in CR set.When structure CR set, if systems axiol-ogy is to CR more than the restriction of CR scale, then CR and/or the logical function associated with CR can be reported to user by system.
Once successfully build at least some CR, then system can attempt combining CR.In certain embodiments, system can combine CR by iterative manner.Specifically, system heuristically can sort to obtain CR function sequence (this sequence is fundamentally being different from variables reordering) to CR, and combines CR iteratively according to the sequence of CR function.When combination CR, system can be determined: when inoperation CR scale limits, some CR can not combine.Specifically, system can successful combination CR subset to obtain middle CR.But no matter when system attempts combination any residue CR and middle CR, and system can be determined to violate the restriction of CR scale.In response to determining that some CR can not combine when inoperation CR scale limits, CR can be reported to user by system.User can use this information to identify about intrafascicular mistake fast.
In certain embodiments, once system determines that some CR can not combine when inoperation CR scale limits, system automatically can increase the restriction of CR scale and attempt limiting the CR scale of CR and increase combining.
Accompanying drawing explanation
Fig. 1 illustrates each stage according to an embodiment of the invention in the designing and making of integrated circuit.
Fig. 2 A illustrates and retrains according to an embodiment of the invention.
Fig. 2 B illustrates BDD according to an embodiment of the invention.
Fig. 3 illustrates according to an embodiment of the invention can how according to constraint set incompatible structure BDD.
Fig. 4 presents the process flow diagram to the process illustrated according to an embodiment of the invention for constructing BDD.
Fig. 5 presents the process flow diagram to the process illustrated according to an embodiment of the invention for constructing CR.
Fig. 6 presents the process flow diagram to the process illustrated according to an embodiment of the invention for constructing CR.
Fig. 7 illustrates computer system according to an embodiment of the invention.
Fig. 8 illustrates an apparatus in accordance with one embodiment of the invention.
Embodiment
Present following description to enable those skilled in the art realize and to utilize the present invention, and provide this description under the background of application-specific and requirement thereof.Those skilled in the art will the easily clear various amendments to disclosed embodiment, and the General Principle limited here goes for other embodiments and application and do not depart from Spirit Essence of the present invention and scope.Therefore, the invention is not restricted to illustrated embodiment but will be endowed with the widest scope consistent with principle disclosed herein and feature.
integrated circuit (IC) design cycle
Fig. 1 illustrates each stage according to an embodiment of the invention in the designing and making of integrated circuit.
Product conception (step 100) that this process can realize from the integrated circuit using EDA process (step 110) to design.After flow integrated circuit (event 140), this design can through making process (step 150) and encapsulation and assembling process (step 160) to produce finished chip 170.
EDA process (step 110) comprise hereafter only for illustrative purposes and describe and also be not used for limiting step 112-130 of the present invention.Specifically, these steps can be performed in the sequence different from sequence described below.
In system (step 112) period, circuit designers can describe the function that they want to implement.If they also could carry out-how about the planning of (what-if) would be with refinement functionality, inspection cost etc.Hardware-software architecture divides also can appear at this one-phase.The Example EDA software products from Synopsys company that can use in this step comprise Model Architect,
system Studio and Design
In logical design and functional verification (step 114) period, VHDL or the Verilog code for the module in system can be write, and check the function accuracy of this design, such as, this design can be checked to ensure that it produces correct output.The Example EDA software products from Synopsys company that can use in this step comprises
design
magellan
tM,
eSP and
In synthesis and test design (step 116) period, VHDL/Verilog can be translated into net table.In addition, for object technology optimization net table, and can test to check finished chip by design and implementation.The Example EDA software products from Synopsys company that can use in this step comprises Design
physical
test Compiler, Power Compiler
tM, FPGA Compiler, Tetra
and Design
In net table checking (step 118) period, the compatibility of net table and temporal constraint and the correspondence with VHDL/Verilog source code can be checked.The Example EDA software products from Synopsys company that can use in this step comprises
prime
with
In design planning (step 120) period, can construct and analyze the whole floor planning (floor plan) for chip to carry out timing and top layer wiring.The Example EDA software products from Synopsys company that can use in this step comprises Astro
tMwith ICCompiler product.
In physical implementation (step 122) period, can position circuit component in layout (layout), and these circuit components can be electrically coupled (wiring).The Example EDA software products from Synopsys company that can use in this step comprises Astro
tMwith IC Compiler product.
In analysis with extract (step 124) period, ghost effect (parasitics) can be extracted in the function of transistor level proof scheme.The Example EDA software products from Synopsys company that can use in this step comprises AstroRail
tM, PrimeRail, Prime
and Star-RCXT
tM.
In physical verification (step 126) period, can test design to ensure the correctness of manufacture, electrical problems, lithographic issues and circuit.Hercules
tMit is the Example EDA software products from Synopsys company that can use in this step.
Strengthen (step 128) period in resolution, geometric configuration manipulation can be carried out to improve the manufacturability of design to layout.The Example EDA software products from Synopsys company that can use in this step comprises Proteus/Progen, ProteusAF and PSMGen.
In Mask data preparation (step 130) period, " flow " can design to produce the mask used during making.The Example EDA software products from Synopsys company that can use in this step comprises
series of products.
Some embodiments can be used during one or more above-mentioned steps.Specifically, some embodiments (step 114) can be used during functional verification.
constrained random simulation
Correctly being limited by the environment supposing to work wherein given DUV is an important prerequisite for design effectively checking.Traditionally, verify that slip-stick artist has used test board to carry out modeling to the environment of DUV.Hardware description language can be used to describe test board.Note, test board generally includes the set of following test, and these are tested constraint environment in a suitable manner and so that the target covering DUV shows gather.
Some hardware languages (such as System Verilog) support is used for some high level constructs of clearly specifying constraint in test board.Specifically, clearly constraint can be used for restricting Stochastic choice to test board in the mode consistent with the agreement of DUV.Such test board is commonly referred to constrained random test board.
As mentioned above, random stimulus generates performance and usually lags behind logical simulation performance far away.Therefore, the performance improving constraint solver can have a large amount of impact to the overall performance of test board.Therefore, the performance improving constraint solver is wished.
bDD (binary decision diagram)
In typical constrained random simulation occasion, user writes constrain set (such as using System Verilog), and during emulating, the random simulation attempting finding to meet the constraint of being specified by user is stimulated (set of stochastic variable assignment) by constraint solver.Constraint solver can use BDD, ATPG, satisfiability or other similar fashion to find satiable solution (emulation stimulates).
Specifically, based in the constraint solver of BDD, system uses BDD to represent constraint usually.Stochastic variable (for emulation) treated as BDD variable, and the conjunction (conjunction) of (to these variablees) constraint is configured to the Boolean function that represented by BDD.When the value that use that and if only if is given obtains " true (TRUE) " value to Boolean function evaluation, the assignment to these variablees just can meet constraint.
Fig. 2 A illustrates and retrains according to an embodiment of the invention.
Constraint shown in Fig. 2 A is the Boolean function of " a ", " b " and " c " these three stochastic variables.Stochastic variable is commonly used to carry out modeling to DUV, and such as stochastic variable " a " can represent the logic state of the input signal in DUV.Note, among the assignment of all probable values to stochastic variable, only the assignment of some values corresponds to the effective status of DUV.Because constrained random simulation is intended to about effective status checking DUV, so need a kind of technology of the value in order to restrict stochastic variable.Constrained random simulation uses constrain set to restrict the value of stochastic variable usually.Specifically, during the emulation based on constraint, test board can generate the stochastic inputs (such as the assignment of the value of stochastic variable " a ", " b " and " c ") meeting constrain set.In this way, by using constrain set, emulation and verification tool can verify DUV by the stimulation providing expectation to occur in the normal operation period to DUV.
A kind of mode for generating stochastic inputs uses BDD.Specifically, first system can generate the BDD representing constrain set.Then, system can use BDD to generate stochastic inputs.Specifically, corresponding with value " 1 " in the BDD each path from root node to end node can associate with the assignment meeting constrain set.
Fig. 2 B illustrates BDD according to an embodiment of the invention.
BDD 200 can represent and retrains shown in Fig. 2 A.BDD 200 comprises node 202,204,206,208,210,212,214 and 216.Node 202 can be the root node that can be used for representing whole constraint.Node 204 can associate with variable " a ", and node 206 can associate with variable " b " with 208, and node 210 can associate with variable " c " with 212.Node 214 can represent Boolean "True" for Boolean function or " 1 ".In other words, node 214 can represent the situation wherein meeting constraint.In contrast, node 216 can represent Boolean "false" or " 0 ".In other words, node 216 can represent the situation wherein not yet meeting constraint.
Directed edge in BDD 200 can represent the assignment to stochastic variable.Such as, can associate with to stochastic variable " a " imparting " 0 " value with the directed edge between 206 at node 204.Similarly, can associate with to stochastic variable " b " imparting " 1 " value with the directed edge between 212 at node 208.
The following assignment to stochastic variable can be corresponded to from root node (such as node 202) to the directed walk of the end node (such as node 214) for Boolean "True" in BDD, this assignment meets the constrain set represented by BDD, such as, retrain shown in Fig. 2 A.Such as, path 218 starts from node 202 and terminates in node 214.The assignment associated with path 218 is: a=0, b=1 and c=1.Obviously, this assignment causes Boolean function evaluation shown in Fig. 2 A to obtain "True".
Once system constructing BDD, it by determining all diverse paths from root node to the end node corresponding with "True" value, and by Stochastic choice path from the set of all diverse paths, can generate constrained random stimulation.
How Fig. 3 can construct BDD according to constrain set according to an embodiment of the invention if illustrating.
Suppose that constrained random simulation needs to generate the stochastic inputs meeting constrain set 302.Constraint solver can build the BDD for each constraint, and namely a BDD is separately for retraining C
1, C
2and C
3.Then, solver can by the conjunction using the BDD constructed by combining indivedual BDD to represent constrain set.
In certain embodiments, solver can combine BDD by iterative manner.Such as in step 304, solver can from following BDD, and this BDD is used for and constraint C
1identical constraint K
1.Then within step 306, solver can be constructed as follows BDD, and this BDD is used for and constraint C
1and C
2the equal constraint K of conjunction
2.Note, K can be used for by combination
1and C
2bDD come for constraint K
2structure BDD.In step 308, solver can be configured to retrain K finally
3bDD, this constraint K
3equal to retrain C
1, C
2and C
3conjunction.Note, K can be used for by combination
2and C
3bDD be configured to retrain K
3bDD.Be otherwise noted that for K
3bDD be BDD for constrain set 302.For K
3bDD can be used for generating the stochastic inputs meeting constrain set 302.The more details about how building and combine BDD can be found in Constraint-BasedVerification at Springer in January, 2006 people such as Jun Yuan.
Note, user likely writes the constrain set being difficult to use the constraint solver based on BDD to solve.Specifically, when the constraint solver based on BDD is attempted generating BDD for constrain set, BDD " may expand (blow up) ", and the scale of such as BDD may become so big, to such an extent as to structure BDD or use BDD becomes unrealistic to generate the solution being used for constrain set.Note, expansion problem is not limited to the mode based on BDD.Such as, if constraint solver uses the mode based on ATPG (automatic test pattern generation), then user may feel that constraint solver is trying hard to generating solution all the time.
BDD expansion problem is based on one of key performance roadblock in the random stimulus of constraint.In other words, random stimulus generates one of reason lagging behind logical simulation and is BDD expansion problem.If system can help user to identify and repair the situation wherein estimating BDD expansion, then system obviously can improve the overall performance of constraint solver.Specifically, user will want to know that what is constrained to causes BDD to expand usually, and the more important thing is how to repair this problem or how to solve this problem.This expansion is usually caused by some constraints.In some cases, retrain and BDD may be caused to expand with regard to itself, and in other situations, occur that BDD expands due to mutual between multiple constraint.If system can identify the constraint causing BDD to expand, then it can help user to identify about intrafascicular mistake, and also helps user to determine how to rewrite constraint to repair BDD expansion problem.Once user has rewritten constraint to avoid expansion problem, then constraint can be used for generating stochastic inputs by constraint solver.
Note, constrained random checking is only one of many application using BDD.Therefore, above-mentioned BDD expansion problem is not limited to constrained random checking application; BDD expansion problem can come across combination BDD to obtain in any application of combined type BDD.Then a kind of by helping to solve BDD expansion problem and contribute to constructing the technology of BDD or system may be used for combining in any application of BDD.
In addition, expansion problem is not limited to BDD.Specifically, all may there is expansion problem in any canonical representation of logical function.Specifically, system can logic-based collection of functions incompatible structure CR.Expansion problem may be there is when system attempts the indivedual CR of combination to obtain combined type CR.
Note, the canonical representation of logical function can be generally any expression meeting following character: if two logical function equivalences, as long as use identical variables reordering (or equivalent characteristic) while structure canonical representation, then their canonical representation will be identical.The example of canonical representation includes but not limited to binary decision diagram, binary square spirogram (binary momentdiagram), null suppression binary decision diagram, many-valued decision diagram, multiterminal binary decision diagram, algebraically decision diagram etc.
How how following chapters and sections according to constraint set incompatible structure BDD and can construct CR according to logical function set if describing.
according to constraint set incompatible structure BDD
Some embodiments of the present invention provide a kind of system, this system can help user identify constrain set why cause obtain BDD expansion.Specifically, system can arrange for constraint solver any restriction L runtime and/or storer being used to (comprising BDD scale).When structure BDD, if solver exceedes this restriction, then system can infer that BDD expands.
As explained above, in constrained random simulation occasion, given constrain set K={c
1, c
2..., c
n, wherein each c
nfor constraint.In order to generate stochastic inputs, constraint solver is generally each constraint and builds BDD, then combines BDD to obtain the combined type BDD representing the conjunction of indivedual BDD.Cause conjunction result evaluation be 1 or "True" BDD variable assignment will form to constraint solution.During building the process of BDD for each constraint, if BDD expansion (more than BDD restriction, storer restriction or runtime restriction), then system can infer that this constraint is at least one of BDD construction process reason of continuing so.This constraint can be reported to user by system, helps user to identify the root cause of BDD expansion problem thus.
Note, BDD may expand due to bad variables reordering (even and if enable dynamic variable sequence, it still may be expanded due to the about intrafascicular afoul ordering requirements of difference).
Note, variables reordering is fundamentally being different from function sequence.Variables reordering refers to that variable is used for being formed the order of BDD.On the other hand, function sequence refers to the order wherein combining constraint (or logical function).Note, change the order that wherein constraint (or logical function) is carried out combining and do not change variables reordering.Conversely, the order changing choice variable when constructing BDD does not change retraining the order combined.
Identify that in order to help user whether particular variables sequence causes expansion, and some embodiments can use the 2nd BDD manager attempting different variables reordering, comes for problematic constraint builds BDD.Even if if BDD structure is still expanded after different variables reordering attempted by the 2nd BDD manager, then system can be constraint (such as constraint may be too complicated and cannot use BDD to represent) and does not lie in variables reordering by inference problems.Thus, system can to user report: problem is constraint itself and does not lie in particular variables sequence.This can allow user avoid time waste to solve BDD expansion problem in trial by changing variables reordering.On the other hand, if change variables reordering to repair expansion problem, then system can infer that BDD expansion problem is caused by the requirement of afoul BDD variables reordering.System can print and cause the constraint of afoul BDD variables reordering requirement or taking a step forward of they of printing, constraint is diminished.
Namely the BDD being used in each constraint does not expand, and when combining BDD between conjunction operational stage, BDD still can expand.As explained above, some embodiments can build { c iteratively
1, c
2..., c
nconjunction, BDD J wherein
1, J
2..., J
nbe constructed as follows:
J
1＝c
1
J
2＝J
1·c
2
J
i＝J
i-1·c
i
J
n＝J
n-1·c
n
If can construct above-mentioned conjunction without expansion, then whole constrain set will can solve.But as combination two BDD, the BDD obtained may become impractically large.Note, if undertaken retraining { c by different order
1, c
2..., c
nconjunction, then conjunction BDD:J in the middle of
1, J
2..., J
n-1to be different, but final conjunction result J
nto be identical.Possible is cause middle BDD to expand by particular order combination BDD, but if by different order combination BDD, then in the middle of, BDD will not expand.Regrettably, determine that not causing the BDD function of expansion to sort is a NP-Hard problem.
Whether some embodiments of the present invention detect estimates that middle BDD expands and avoids expansion problem to BDD rearrangement with trial.Specifically, some embodiments utilize wherein to increase BDD scale for ordered pair constraint { c
1, c
2..., c
ncarry out the greedy trial method (greedy heuristic) that sorts.Such as, system can sort to constraint based on the interstitial content in corresponding BDD.Those skilled in the art can use other modes to sort to constraint by clear.Such as, system can sort to constraint based on the storer total quantity of the BDD for associating.In addition, system can sort to constraint based on about intrafascicular state variable and/or constant number.Once system sorts to BDD by particular order, then system can carry out conjunction computing as above iteratively.
In order to illustrative system how to constraint rearrangement, can suppose that conjunction computing is attempted calculating J in system
iin time, is expanded.In this point, following message can print to user by system, and this message informs the user can by constraint { c
1, c
2..., c
i-1but all solve together and add constraint c to it
icause the BDD J obtained
iexceed capacity restriction L.Note inform the user which constraint and definitely cause combinatorial operation expansion rather useful for debugging expansion problem.In certain embodiments, system can stop BDD construction process in this point.But other embodiments can be resequenced to constraint and be attempted using new BDD function sequence to build BDD.
In certain embodiments, system can from { c
i+1, c
i+2..., c
nselect constraint c
jand attempt carrying out J
i-1with c
jbetween conjunction.If c
jalso cause expansion, then system can select another constraint still untapped from constrain set.Conjunction process can continue by this mode until limit institute Constrained, if thus each residue constraint combine with middle BDD, will expansion be caused.Then, system can be reported successfully the constrain set of " conjunction " and cause the constrain set of expansion.Such as in above-mentioned occasion, if constraint { c
i, c
i+1, c
i+2..., c
nin each constraint cause expansion, then system can to user report it can successfully carry out to constraint { c
1, c
2..., c
i-1conjunction computing and residue constraint { c
i, c
i+1, c
i+2..., c
nin each constraint cause expansion.This information can help user to identify one or more about intrafascicular mistake.Specifically, when user checks this two constrain sets, user may can identify the about intrafascicular variable or the expression formula that cause expansion.
Such as, suppose that 16 multipliers in circuit cause BDD to expand.When user checks the constraint causing expansion, user can recognize that expansion is caused by 16 multipliers immediately.Such as, user can notice that to cause institute's Constrained of expansion relevant with 16 multipliers in some way, and therefore user correctly can infer that expansion is caused by 16 multipliers.Note, most probable is comprised a large amount of module by circuit, and except nonsystematic definitely report which constraint cause expansion, user just can terminate the plenty of time will be wasted in identification problem.Once user identifies that 16 multipliers cause expansion, user has the many options overcoming problem.Such as, user can rewrite the constraint associated with 16 multipliers, or user can by more easy module as 8 multipliers replace 16 multipliers.
As another illustrative example, suppose that circuit comprises floating-point module and integer module, and suppose that these modules are not all assumed to be and connect simultaneously.When user's review causes the constraint of expansion, user can recognize because constraint allows floating-point module and integer module to connect all simultaneously, so constraint is write improperly.Once user recognizes this mistake, user can rewrite constraint with mis repair.
Based on above description, following paragraph describes the system and technology that can be used for constructing BDD.Note, these systems and technology are not limited to suffer restraints accidental validation and they are not limited to conjunction; They may be used for relating in any application of combination BDD.
Fig. 4 presents the process flow diagram to the process illustrated according to an embodiment of the invention for constructing BDD.
This process can by starting for each constraint in set builds BDD (step 402).Then, system can determine when being constructed, whether have any BDD to expand (step 404).If BDD expands, then interconnection constraint can be reported to user's (step 406) by system.On the other hand, if do not have BDD to expand, then then system can sort (step 408) to the constraint in set.
Then the first constraint in set can be moved to conjunction (step 410) by system.Then, system can from another constraint (step 412) of Resource selection.Then system can determine whether to estimate that the BDD obtained expands (step 414) between conjunction operational stage.
If the BDD expansion obtained, then then system can determine whether it has attempted institute's Constrained (step 418).If system not yet attempts institute's Constrained, then system can be got back to step 412 and be selected another constraint in set.On the other hand, if system has attempted institute's Constrained, then the constraint in set can be reported to user's (step 422) and stop this process by system.Note, the constraint being reported to user is the constraint causing conjunction process to expand.In one change, system can increase the restriction of BDD scale and attempt by using new BDD scale restriction to combine BDD.System can notify user when it increases the restriction of BDD scale.
On the other hand, if the BDD obtained does not expand, then system can upgrade conjunction result and from set, remove selected constraint (step 416).Then system can determine whether to have attempted institute's Constrained (step 420).If like this, then system can be reported conjunction computing success (step 424) and stop this process.On the other hand, if not yet attempt institute's Constrained, then system can be got back to step 412 and be selected another constraint in set.
cR is constructed according to logical function set
Note, expansion problem is not limited to carry out conjunction computing for BDD set.Specifically, expansion problem may occur while combination represents the CR set of logical function set.
Fig. 5 presents the process flow diagram to the process illustrated according to an embodiment of the invention for constructing CR.
By receiving, this process can wish that the logical function set (step 502) for its structure CR starts.
System can use CR scale to limit and become too large to determine that CR is suitable.The restriction of CR scale generally can based on one or more standard, and these standards show whether estimate that structure CR causes performance issue.
Such as, experimental evidence can show, as long as the element in CR (such as node or limit) number exceedes specific threshold, CR construction process uprises needing the possibility of unpractical long period.In such circumstances, the restriction of CR scale can be expressed according to the element of CR (such as node or limit).The other standards that can be used for expressing the restriction of CR scale comprises to store amount of memory that CR needs and in order to construct the processor number of cycles that CR needs.
In certain embodiments, system can express CR scale according to multiple parameter or standard.Such as, system can use two threshold values to express CR scale: storer threshold value and processor Ct value.In this example, if exceed storer threshold value or exceed processor Ct value, then CR will more than CR scale.
Continue process flow diagram shown in Fig. 5, then system can be gathered by logic-based collection of functions incompatible structure CR, the logical function (step 504) in each CR presentation logic function set wherein in CR set.System can monitor the scale of CR while creating CR according to each constraint.If the scale of specific CR is more than the restriction of CR scale, then CR can be reported to user by system.In certain embodiments, when system determines that the scale of CR limits more than CR scale, system can stop this process.In other embodiments, system can continue as other constraints and build CR.
Then, system can sort to obtain CR function sequence (c to CR set
1, c
2..., c
n), wherein c
ibe i-th position in the sequence of CR function, and n is CR cardinality of a set (step 506).Note, variables reordering is fundamentally different from function sequence.Variables reordering refers to following order, selects the variable of concrete logical function to form CR (noting this CR being applicable to need variables reordering) according to this order.On the other hand, function sequence refers to the order of wherein combinational logic function.
Then system can combine the CR c in the sequence of CR function
1to c
j-1to obtain middle CR, wherein 2 < j < n (step 508).Note, combination CR obtains following CR, and this CR represents the logical combination of the logical function associated with CR.Therefore, middle CR represents the CR c in sorting with CR function
1to c
j-1the logical combination of the logical function be associated.When logical operation is used for creating the logical expression comprising two logical functions, thinks and combine two logical functions in logic.Such as, suppose that a, b, c and d are logical functions.Then, the logical combination of following logical expression presentation logic function a, b, c and d: (abcd)+(bc.d).
Then, system can attempt combination CR c
jwith middle CR (step 510).Then system can determine whether more than CR scale restriction (step 512).
If more than the restriction of CR scale, then system can use the middle CR (step 518) in following iteration.On the other hand, in response to determining CR c
jcarry out combining with middle CR and obtain the CR that limits more than CR scale, system can select CR c
k, wherein j+1≤k≤n (step 514).In certain embodiments, system can by CR c
jand/or with CR c
jthe logical function of association is reported to user.Then system can attempt combination CR c
kwith middle CR (step 516).In addition, in certain embodiments, system can be failed owing to limiting more than CR scale between each trial period in response to the trial determined combination CR set, automatically increases the restriction of CR scale.
Fig. 6 presents the process flow diagram to the process illustrated according to an embodiment of the invention for constructing CR.
With the same above, by receiving, this process can wish that the logical function set (step 602) for its structure CR starts.Then, system can receive CR scale restriction (step 604).Then system can be gathered by logic-based collection of functions incompatible structure CR, the logical function (step 606) in each CR presentation logic function set wherein in CR set.
Then, system can combine the subset of CR set to obtain combined type CR (step 608).Note, system can combine CR in any order.As mentioned above, in certain embodiments, system can to sort to CR based on the scale of CR and from minimum to greatest combined CR.Sort to CR in any case, system will combine CR usually one at a time.Therefore, any set point during anabolic process, system is all by CR sub-combinations.Note, combination CR obtains following CR, and this CR represents the logical combination of the logical function associated with CR.
Then system can identify the following CR in CR set, estimates this CR obtains scale and limits more than CR scale CR (step 610) when combining with combined type CR.Then the CR of identification can be reported to user's (step 612) by system.Specifically, system can start CR and combined type CR to carry out combining to generate the CR obtained.Then, system can monitor the scale of the CR obtained when CR and combined type CR combines.If the scale that system determines the CR obtained is more than the restriction of CR scale, then system can stop the combination of CR and combined type CR and CR is reported to user.
Specifically, as Systematic selection CR and attempt by it and combined type CR combines time there are two kinds of possibilities.First possibility is, anabolic process completes and more than CR scale, and the CR obtained is the combination of selected CR and combined type CR.Another possibility is, limits while the selected CR and combined type CR of combination more than CR scale.If there is such situation, then the CR of identification can be reported to user by system, and help user identifies the mistake in constrain set thus.
Fig. 7 illustrates computer system according to an embodiment of the invention.
Computer system 702 comprises processor 704, storer 706 and reservoir 708.Computer system 702 can be coupled with display 714, keyboard 710 and indicating equipment 712.Storer 708 can be stored in when being processed by processor 704 and make computer system 702 construct instruction and/or the data of CR.Specifically, reservoir 708 can stored logic function 716, constructing module 718, order module 720, composite module 722 and reporting modules 724.During operation, instruction and/or data can be loaded into storer 706 from reservoir 708 by computer system 702, and make purpose processor 704 come processing instruction and/or data.
Constructing module 718 can be included in when being performed by processor 704 and make computer system 702 be the instruction that logical function 716 constructs CR.Order module 720 can be included in instruction when being performed by processor 704, the CR of computer system 702 to structure 718 module structure being sorted.Composite module 722 can be included in when being performed by processor 704 and make computer system 702 according to the instruction of combining CR to definite sequence.Reporting modules 724 can be included in when being performed by processor 704 and make computer system 702 report the instruction of the CR that computer system can not combine.In certain embodiments, system can use display 714 to report CR.
Fig. 8 illustrates an apparatus in accordance with one embodiment of the invention.
Device 802 can comprise multiple mechanisms that can intercom mutually via wired or radio communication channel.Specifically, device 802 can comprise receiving mechanism 804, constructive mechanism 806, sorting mechanism 808, combined mechanism 810 and reporting mechanism 812.In certain embodiments, it will be the logical function set of its structure CR that receiving mechanism 804 can be configured to receive, constructive mechanism 806 can be configured to logical function set structure CR, sorting mechanism 808 can be configured to sort to obtain the sequence of CR function to CR, combined mechanism 810 can be configured to combine CR according to the sequence of CR function, and reporting mechanism 812 can be configured to the CR that annunciator 802 can not combine.
Device 802 can be computer system part or can with the specific installation of other computer systems and/or devices communicating.One or more integrated circuit can be used to carry out implement device 802.Specifically, one or more mechanism in device 802 may be embodied as the part of processor.
Conclusion
The data structure described in this embodiment and code are stored in computer readable storage devices usually, and this equipment can be any equipment that can store code for being used by computer system and/or data.Computer readable storage devices includes but not limited to volatile memory, nonvolatile memory, magnetic and optical storage apparatus (such as coil other media that can store computer-readable medium of driving, tape, CD (CD), DVD (digital universal disc or digital video disc) or known or later exploitation now.
The Method and Process described in this joint of embodiment can be embodied as and can be stored in code in computer readable storage devices described above and/or data.When computer system reads with when performing code and/or data that computer readable storage devices stores, that computer system realizes embodying as data structure and code and the Method and Process be stored in computer readable storage devices.
In addition, described Method and Process can be comprised in hardware module.Such as, hardware module can include but not limited to other programmable logic device (PLD) of special IC (ASIC) chip, field programmable gate array (FPGA) and known or in the future exploitation now.When activating hardware module, hardware module realizes the Method and Process comprised in hardware module.
Only present the description above to the embodiment of the present invention for the object of example and description.Original idea not allows their exhaustive the present invention or make the present invention be limited to disclosed form.Thus, those skilled in the art will know many modifications and variations.In addition, original idea not allows above-mentioned disclosure limit the present invention.Scope of the present invention is defined by the following claims.
Claims (20)
1., for contributing to the method for electric design automation performed by computing machine constructing canonical representation CR, the logical combination of described CR presentation logic function set, described method comprises:
Receive the restriction of CR scale;
Construct CR set based on described logical function set, each CR in wherein said CR set represents the logical function in described logical function set;
Combine the subset of described CR set to obtain the first combined type CR;
Identify described CR gather in a CR, a described CR is expected to be and obtains scale when combining with described first combined type CR and exceed the second combined type CR that described CR scale limits; And
The first logical function associated with a described CR is reported to user.
2. the method performed by computing machine according to claim 1, the described subset wherein combining described CR set comprises:
Sort to obtain the sequence of CR function to described CR set; And
Combine described CR according to described CR function sequence to gather.
3. the method performed by computing machine according to claim 2, wherein carries out sequence to described CR set and comprises: sort to described CR set based on scale.
4. the method performed by computing machine according to claim 1, wherein constructs described CR set and comprises: if estimate that the scale of the 2nd CR exceedes the restriction of described CR scale, then the 2nd CR is reported to described user.
5. the method performed by computing machine according to claim 1, wherein identifies that the described CR in described CR set comprises:
Start to combine a described CR and described first combined type CR, to generate the CR obtained;
The scale of the CR obtained described in monitoring when a described CR and described first combined type CR combines; And
Scale in response to the CR determining to obtain has exceeded the restriction of described CR scale and has stopped combining a described CR and described first combined type CR.
6. the method performed by computing machine according to claim 1, wherein CR is binary decision diagram BDD.
7., for contributing to the equipment for electric design automation constructing canonical representation CR, the logical combination of described CR presentation logic function set, described equipment comprises:
Receiving trap, for receiving the restriction of CR scale;
Constructing apparatus, for constructing CR set based on described logical function set, each CR in wherein said CR set represents the logical function in described logical function set;
First combination unit, for combining the subset of described CR set to obtain the first combined type CR;
Recognition device, for identify described CR gather in a CR, a described CR is expected to be and obtains scale when combining with described first combined type CR and exceed the second combined type CR that described CR scale limits; And
Annunciator, for being reported to user by the first logical function associated with a described CR.
8. equipment according to claim 7, wherein said first combination unit comprises:
Collator, for sorting to obtain the sequence of CR function to described CR set; And
Second combination unit, gathers for combining described CR according to described CR function sequence.
9. equipment according to claim 8, wherein said collator carries out sequence to described CR set and comprises: for gathering the device sorted to described CR based on scale.
10. equipment according to claim 7, wherein said constructing apparatus comprises: if for estimating that the scale of the 2nd CR exceedes the restriction of described CR scale, then described 2nd CR is reported to the device of described user.
11. equipment according to claim 7, wherein said recognition device comprises:
A described CR and described first combined type CR is combined to generate the device of the CR obtained for starting;
For the device of the scale of CR obtained described in monitoring when a described CR and described first combined type CR combines; And
Exceed the restriction of described CR scale for the scale in response to the CR determining to obtain, stop the device combining a described CR and described first combined type CR.
12. equipment according to claim 7, wherein CR is binary decision diagram BDD.
13. 1 kinds for constructing the method for electric design automation performed by computing machine of canonical representation CR, the logical combination of described CR presentation logic function set, described method comprises:
Receive the restriction of CR scale;
Construct CR set based on described logical function set, each CR in wherein said CR set represents the logical function in described logical function set;
Sort to obtain CR function sequence { c to described CR set
1, c
2..., c
n, wherein c
ibe the CR of i-th position in described CR function sequence, and n is described CR cardinality of a set;
Combine the CR c in the sequence of described CR function
1to c
j-1, to obtain middle CR, wherein 2 < j < n;
In response to determining combination CR c
jthe CR will obtaining exceeding described CR scale with described middle CR and limit, selects CR c
k, wherein j+1≤k≤n; And
Attempt combination CR c
kwith described middle CR.
14. methods performed by computing machine according to claim 13, wherein carry out sequence to described CR set and comprise: sort to described CR set based on scale.
15. methods performed by computing machine according to claim 13, wherein CR is binary decision diagram BDD.
16. methods performed by computing machine according to claim 13, also comprise: limit and failure owing to exceeding described CR scale between each trial period in response to the trial determined the described CR set of combination, increase the restriction of described CR scale.
17. 1 kinds for constructing the equipment for electric design automation of canonical representation CR, the logical combination of described CR presentation logic function set, described equipment comprises:
Receiving trap, for receiving the restriction of CR scale;
Constructing apparatus, for constructing CR set based on described logical function set, each CR in wherein said CR set represents the logical function in described logical function set;
Collator, for sorting to obtain CR function sequence { c to described CR set
1, c
2..., c
n, wherein c
ibe the CR of i-th position in described CR function sequence, and n is described CR cardinality of a set;
First combination unit, for combining the CR c in the sequence of described CR function
1to c
j-1, to obtain middle CR, wherein 2 < j < n;
Selecting arrangement, for combining CR c in response to determining
jto obtain exceeding CR that described CR scale limits to select CR c with described middle CR
k, wherein j+1≤k≤n; And
Second combination unit, for attempting combination CR c
kwith described middle CR.
18. equipment according to claim 17, wherein said collator comprises: for gathering the device sorted to described CR based on scale.
19. equipment according to claim 17, wherein CR is binary decision diagram BDD.
20. equipment according to claim 17, described equipment also comprises: for limiting and failure owing to exceeding described CR scale between each trial period in response to the trial determined the described CR set of combination, increase the device of described CR scale restriction.
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| CN (1) | CN101789034B (en) |
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| US8099690B2 (en) * | 2009-04-27 | 2012-01-17 | Synopsys, Inc. | Adaptive state-to-symbolic transformation in a canonical representation |
| US9720792B2 (en) | 2012-08-28 | 2017-08-01 | Synopsys, Inc. | Information theoretic caching for dynamic problem generation in constraint solving |
| US11468218B2 (en) | 2012-08-28 | 2022-10-11 | Synopsys, Inc. | Information theoretic subgraph caching |
| US8904320B2 (en) | 2013-03-13 | 2014-12-02 | Synopsys, Inc. | Solving multiplication constraints by factorization |
| US9202005B2 (en) | 2013-08-28 | 2015-12-01 | Synopsys, Inc. | Development and debug environment in a constrained random verification |
| US9477800B1 (en) * | 2015-02-11 | 2016-10-25 | Cadence Design Systems, Inc. | System, method, and computer program product for automatically selecting a constraint solver algorithm in a design verification environment |
| US11906445B2 (en) * | 2018-10-10 | 2024-02-20 | Goodrich Corporation | Automated defect detection for wire rope using image processing techniques |
| US11595267B2 (en) | 2020-12-22 | 2023-02-28 | Huawei Technologies Co., Ltd. | Methods and systems for distributed network verification |
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| US6539531B2 (en) * | 1999-02-25 | 2003-03-25 | Formfactor, Inc. | Method of designing, fabricating, testing and interconnecting an IC to external circuit nodes |
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| TW200604865A (en) * | 2004-07-16 | 2006-02-01 | Hon Hai Prec Ind Co Ltd | System and method for crosstalk checking of nets in a layout |
| US7340473B2 (en) * | 2004-08-26 | 2008-03-04 | International Business Machines Corporation | Method and system for building binary decision diagrams efficiently in a structural network representation of a digital circuit |
| US7668632B2 (en) | 2004-11-22 | 2010-02-23 | The Boeing Company | System, method and computer program product for real-time event identification and course of action interpretation |
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| CN1749769A (en) * | 2004-05-21 | 2006-03-22 | 富士通株式会社 | Invariant detects |
| WO2007021552A2 (en) * | 2005-08-09 | 2007-02-22 | Nec Laboratories America, Inc. | Disjunctive image computation for sequential systems |
| CN1892616A (en) * | 2006-05-12 | 2007-01-10 | 中国科学院计算技术研究所 | Method for realizing kernel-mode programe verification in user-mode random verification of microprocessor |
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| CN101789034A (en) | 2010-07-28 |
| WO2010088147A3 (en) | 2010-10-28 |
| US20100191679A1 (en) | 2010-07-29 |
| EP2382566A2 (en) | 2011-11-02 |
| WO2010088147A2 (en) | 2010-08-05 |
| US8370273B2 (en) | 2013-02-05 |
| EP2382566A4 (en) | 2013-02-27 |
| TWI471747B (en) | 2015-02-01 |
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