CN101788963A - DRAM (Dynamic Random Access Memory) storage control method and device - Google Patents
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Abstract
The invention discloses DRAM storage control method and device. The method comprises the following steps of: A10. decoding read and write requests and rearranging into a plurality of BANK-based read and write request arrays according to BANK addresses; A20. respectively arbitrating the read and write requests; A30. respectively generating respective read and write request commands and activating commands and/or precharge commands; and A40. sending the read and write request commands to a command bus, and on the premise of satisfying the read and write protection time limit of a DRAM, inserting the activating commands and/or percharge commands of the read and write command requests in the other BANKs based read and write request arrays before the read and write command request in the BANK-based read and write request array. In the invention, the activating commands and the precharge commands can be completely hidden in the data transmission process, and seemingly, a DRAM data bus always transmits data, and therefore, the bus efficiency of the DRAM is greatly improved.
Description
Technical field
The present invention relates to DRAM, be specifically related to DRAM storage controlling method and device.
Background technology
Employed terminological interpretation is as follows in the application documents:
BANK, memory cell array;
BC, bank controller, BANK control module;
MC, master controller, MC main control unit.
At present, data communication field is used high capacity external memory storages such as SDRAM, DDR SDRAM and DDR2 SDRAM through regular meeting.And the bus bandwidth of external memory storage has often determined the maximum bandwidth processing power of a data communication system in real work, and therefore, the bus bandwidth that improves DRAM is one of important channel of improving data communication system bandwidth processing ability.
As shown in Figure 1, DRAM is made up of memory cell array 100, command decoder 101, BANK address decoder 103, row-address decoder 102, column address decoder 104, IO interface control section 105 and DLL unit 106.Memory cell array 100 is positioned at the core of DRAM, and each dram chip has 4 or 8 memory cell arrays 100 (being BANK) usually, and each data bit separate, stored is in the storage unit lattice by row address and column address addressing of specifying BANK.So the client requests address correspondingly is divided into 3 parts, i.e. BANK address, row address and column address are respectively by the decode storage unit of corresponding address of BANK address decoder 103, row-address decoder 102 and column address decoder 104.Wherein row address and column address are read into the row address buffer and the column address buffer of storage array respectively when the capable gating of the RAS of command decoder 101 and CAS column selection are logical.All storage instructions of DRAM CS sheet choosing effectively, CKE is effectively and during the rising edge of clock, determined by 3 order wire RAS, the CAS of DRAM and WEN and assembled state, mainly comprise pattern loading instruction, refreshing instruction, write command, read instruction, activation instruction and charging instruction.The IO interface control section 105 of DRAM is finished the bidirectional data transfers of data and is write the data mask function.106 of DLL unit are input clock and the sheet internal clocks of calibration DRAM under high-frequency clock, to reduce because in the sheet, the data AC time sequence difference that causes of sheet external clock difference.
It is different that the access control method of DRAM has the utilization ratio of multiple, different its bus of control method.For example after finishing read-write operation, whether to this activation page charge and close the utilization ratio that will influence bus.Before activation page has not been closed, if follow-up read-write operation is addressed to same one page, just can directly read and write, save activationary time, this is referred to as page or leaf and hits (page hit); If follow-up read-write operation is addressed to the different pages, just must close this page earlier, activate the page of wanting addressing again, just can read and write then, this just causes time-delay very big on the time, is referred to as page or leaf disappearance (page miss); In addition, time loss between page or leaf hit and page or leaf disappearance between be that accessing operation wants the page of addressing to close, only need to carry out activate the back just can read-write operation, be referred to as a page free time (a page idle).
DRAM supports the random read-write access, the access of promptly a plurality of BANK table tennis.When this represents that a certain BANK does the read/write access operation, other BANK can do charging or activation command, utilize this characteristic, avoiding under the conflict of data bus conflict and command line, can overlappingly send instruction and give different B ANK, be the concurrent working that can interlock between the BANK, make full use of bus and reach, this is the important channel of improving the DRAM access performance.
In addition, DRAM writes or switches to when reading by writing by reading to switch to, all losses if having time on the data bus, and client's read write command is at random, must cause a large amount of read-writes, write-read to switch if carry out accessing operation by the client requests order fully, produce a large amount of idle conditions on the data bus, therefore reducing access command, to switch the bandwidth lose that causes also be to improve DRAM access features important channel.
In addition, some special client's reading and writing requests are arranged, the data volume of these requests can not be carried out access by the monoblock data of DRAM, for example DDR2 SDRAM uses 32bit bit wide and BL4 pattern (Burst Lengthmode, implication is a DDR2 burst-length pattern configurations, can be configured to 4 or 8), promptly a DDR piece data quantity transmitted is 4 * 32bit (16BYTE), and certain request only needs to handle 14BYTE, DDR2 can only effectively transmit 14BYTE in the time that can transmit 16BYTE so, has therefore reduced bandwidth availability ratio; Even some clients' reading and writing request in addition, once need data quantity transmitted to have only 1BYTE, for example ethernet frame is stored in the DDR2 application, if press 64BYTE as a data quantity transmitted, the postamble of the ethernet frame of 65BYTE just only remains next BYTE so, this can cause a large amount of losses on the DRAM data bus, and it also is to improve the problem that the DRAM access performance must solve that elimination customer data and DRAM data block size do not match.
This shows that the bus efficiency of DRAM remains to be improved further at present.
Summary of the invention
Technical matters to be solved by this invention is to solve the problem that further improves the bus efficiency of DRAM.
In order to solve the problems of the technologies described above, the technical solution adopted in the present invention provides a kind of DRAM storage controlling method, may further comprise the steps:
A10, client's reading and writing request carried out address decoder after, rearrange into a plurality of reading and writing request queues according to the BANK address, and the back is parallel synchronously sends with above-mentioned a plurality of reading and writing request queues based on each BANK based on each BANK;
A20, respectively each is arbitrated based on a plurality of reading and writing requests in the reading and writing request queue of each BANK, and rank according to priority orders;
A30, according to each based on the reading and writing request in the reading and writing request queue of each BANK, generate separately reading and writing request command and activation command and/or precharge command respectively;
A40, the reading and writing request command is delivered to command line; and, insert the activation command and/or the precharge command of the reading and writing command request in other BANK reading and writing request queues before the reading and writing command request order in this BANK reading and writing request queue satisfying under the DRAM reading and writing prerequisite in protection time limit.
In the such scheme, the write request formation based on each BANK in the steps A 10 generates by following steps:
A101, client's write request of receiving put into write request message queue with certain configurable deep;
A102, successively client's write request in write request message queue exit is carried out address resolution;
A103, according to the BANK address of resolving back client's write request it is rearranged and to form a plurality of write request formations, write in the write request pretreatment unit respectively based on each BANK;
Parallel sending after A104, a plurality of write request formation synchronously based on each BANK.
Read request queue based on each BANK generates by following steps:
A111, client's read request of receiving put into read request message queue with certain configurable deep;
A112, order are carried out address resolution with client's read request in read request message queue exit;
A113, according to the BANK address of resolving back client's read request it is rearranged and to form a plurality of read request queue based on each BANK, write respectively in the read request pretreatment unit, in this step, the current read-out position of the first pointed read request message queue is set, the writing position of this read request of second pointed in the read request pretreatment unit is set, and the read request corresponding with first pointer writes the relevant position in the read request pretreatment unit of second pointed;
A114, the back is parallel synchronously sends with a plurality of read request queue based on each BANK.
In steps A 40, read each BANK reading and writing request queue successively according to the current reading and writing solicited status sign that is sent to command line.
When the data width of a reading and writing request during greater than DRAM interface data bit wide, this reading and writing request msg is cut apart according to DRAM interface data bit wide, and, send reading and writing request after cutting apart to DRAM by the mode continuous of same page according to size of data and the start address of cutting apart each reading and writing request correspondence of back.
The present invention also provides a kind of DRAM memory control device, this DRAM is made up of a plurality of BANK, be provided with a plurality of basic units of storage of determining by row address and column address respectively among each BANK, described memory control device comprises some reading, write request interface processing unit, asynchronous converting unit, read with the BANK number is corresponding, write request formation arbitration unit and BANK control module and read, write buffer queue unit and MC main control unit, described reading, be respectively equipped with in the write request interface processing unit and read, write request address decoder and reading, write request formation pretreatment unit, the BANK address, row address and column address decoder parse reading of client, the write request address, this address is corresponding with the corresponding basic unit of storage of corresponding BANK, described reading, write request formation pretreatment unit is read according to the client after resolving, the BANK address of write request rearranges into a plurality of reading based on each BANK, the write request formation, and with above-mentioned a plurality of reading based on each BANK, the write request formation walks abreast to mail to synchronously through asynchronous converting unit and reads, write request formation arbitration unit; Described reading and writing request queue arbitration buffer cell is arbitrated a plurality of reading and writing requests in the reading and writing request queue of each BANK respectively, and generates a plurality of reading and writing buffer queues according to priority orders and be buffered in the reading and writing buffer queue unit; Described BANK control module, according to the reading and writing request in each BANK reading and writing request queue in the reading and writing buffer queue unit, generate separately reading and writing request command and activation command and/or precharge command respectively, the parallel MC main control unit that mails to of above-mentioned reading and writing request command and activation command and/or precharge command; The MC main control unit; the reading and writing request command of receiving is delivered to command line; and, insert the activation command and/or the precharge command of the reading and writing command request in other BANK reading and writing request queues before the reading and writing command request order in this BANK reading and writing request queue satisfying under the DRAM reading and writing prerequisite in protection time limit.
In the said apparatus, also be provided with solicited message queue unit in the described reading and writing request interface processing unit with certain configurable deep.
Be provided with first, second pointer in client's read request interface processing unit, indicate the read-out position of read request message queue in client's read request interface processing unit and the writing position in the read request pretreatment unit respectively.
Be provided with the collaborative status unit of MC positioning indicator and MC in the MC main control unit, this MC positioning indicator has to be write, writes transition, read, read transition, refreshes protection and refresh six kinds of state Warning Marks of protection releasing, be provided with the collaborative status unit of BC in the BC control module and at each reading and writing request one BC positioning indicator be set all, this BC positioning indicator has write gate, write and read transition, read gate, read and write transition, refresh and refresh six kinds of state Warning Marks of protection;
When the MC main control unit when DRAM sends write request or read request, the Status Flag of its positioning indicator is set to write or read, the collaborative status unit of MC sends to the collaborative status unit of BC and writes collaborative indication or read collaborative indication simultaneously, the Status Flag of the collaborative status unit BC positioning indicator of BC is set to write gate or read gate, and whole the writing buffer queue or read buffer queue of gating, close whole reading buffer queue or write buffer queue, this moment, the MC main control unit can only respond write request or read request at the write or read of configuration in the time period, do not handle read request or write request, the Status Flag of MC positioning indicator was set to write transition or reads transition after the write or read time period finished, after each write request or read request were sent, the Status Flag of this BC positioning indicator is set to write to be read transition or reads and write transition;
When the Status Flag of MC positioning indicator when writing transition or reading transition, the collaborative status unit of MC sends to the collaborative status unit of BC and writes the collaborative indication of transition or read the collaborative indication of transition, the Status Flag of the collaborative status unit BC positioning indicator of BC is set to write to be read transition or reads and write transition, and gating is remaining writes buffer queue or read buffer queue, close whole reading buffer queue or write buffer queue, wait after all remaining write requests or read request all handle, the MC main control unit sends read request or write request to DRAM, and its Status Flag is set to read or write, and the Status Flag of all BC positioning indicators all is set to read or write;
When the Status Flag of MC positioning indicator when reading or writing, the collaborative status unit of MC sends to the collaborative status unit of BC and reads collaborative indication or write collaborative indication, the Status Flag of the collaborative status unit BC positioning indicator of BC is set to read or write, and whole the reading buffer queue or write buffer queue of gating, close whole writing buffer queue or read buffer queue, this moment, the MC main control unit can only respond read request or write request reading or writing in the time period of configuration, not processing write requests or read request, read or write the time period finish after the Status Flag of MC positioning indicator be set to read transition or write transition, after each read request or write request were sent, the Status Flag of this BC positioning indicator is set to read to be write transition or writes and read transition;
When the Status Flag of MC positioning indicator when reading transition or writing transition, the collaborative status unit of MC sends to the collaborative status unit of BC and reads the collaborative indication of transition or write the collaborative indication of transition, the collaborative status unit of BC is write the Status Flag of BC positioning indicator transition or is write and read transition for reading, wait after all remaining read requests or write request all handle, the Status Flag of MC positioning indicator is set to write or read, and the Status Flag of all BC positioning indicators all is set to write gate or read gate;
When the Status Flag of BC positioning indicator when refreshing; the Status Flag of BC positioning indicator is set to refresh protection; the collaborative status unit of BC sends the protection instruction to the collaborative status unit of MC simultaneously; MC main control unit cell response refresh command; after refresh command execution end; the collaborative status unit of BC sends to the collaborative status unit of MC and refreshes protection releasing instruction, and the MC main control unit was in and received the reading and writing solicited status this moment.
Also comprise data partitioning unit in this device, this data partitioning unit is read with one of client, whether the data width of write request is whether basis for estimation obtains needs to be read this greater than DRAM interface data bit wide, the judged result that the write request data block is cut apart, when showing, judged result need read this, when the write request data block is cut apart, this is read, the data based DRAM interface data of write request bit wide is cut apart, calculate and cut apart corresponding data block size and the start address of each request of back, and send read-write requests after cutting apart to DRAM by the mode continuous of same page.
The present invention, based on the BANK address client is read, write request converts reading of corresponding BANK to, write request, BANK is respectively based on reading separately, the write request formation, produce simultaneously reading separately successively, the write order request, and above-mentioned produced simultaneously BANK reads, the write order request is parallel sends, by receiving reading of BANK, the precedence of write order request is sent to command line successively, and reading at current BANK respectively, be inserted in activation command and the precharge command of back BANK before the write order request command, like this, activation instruction and precharge instruction can be hidden in the data transmission procedure fully, the DRAM data bus is carrying out data transmission always on the surface, has therefore improved the bus efficiency of DRAM greatly.
Description of drawings
Fig. 1: traditional DRAM structural representation;
Fig. 2: the structural representation of DRAM memory control device of the present invention;
Fig. 3: BC control module workflow diagram in the DRAM memory control device of the present invention;
Fig. 4: MC control module and BC control module interact and finish the process flow diagram of read write command binding among the present invention;
Fig. 5: the sequential chart under traditional DRAM control method;
Fig. 6: the sequential chart under the DRAM storage controlling method of the present invention.
Embodiment
At the lower problem of present DRAM external memory stores bus efficiency, the invention provides a kind of DRAM memory control device, this device has improved the utilization ratio of DRAM memory bus, thereby has improved the maximum bandwidth processing power of data communication system in real work greatly.Below in conjunction with the drawings and specific embodiments the present invention is made detailed explanation.
Fig. 2 is the structural representation of DRAM memory control device of the present invention, as shown in Figure 2, this device 200 is finished data storage between client and the DRAM220 by memory bus, wherein have a plurality of BANK (present embodiment is BANK1, BANK2, BANK3 and BANK4) among the DRAM (DDR2 or DDR) 220, have a plurality of basic units of storage on each BANK.DRAM memory control device 200 comprises client's write request interface processing unit 210, client's read request interface processing unit 211, the asynchronous converting unit 212 of write request, the asynchronous converting unit 213 of read request, write request arbitration unit 214, read request arbitration unit 215, writes buffer queue unit 216, reads buffer queue unit 217, BC control module 218 and MC control module 219; Wherein write request interface processing unit 210, client's read request interface processing unit 211 can have a plurality of parallel uses according to client's number, and the number of write request arbitration unit 214, read request arbitration unit 215 and BC control module 218 is identical with the BANK number of the DDR2 that selects for use.
Be provided with BANK address, row address and column address decoder in client's write request interface processing unit 210, above-mentioned demoder is used to parse client's write request address, and this address is corresponding with the respective memory unit of corresponding BANK.Also be provided with write request message queue and write request formation pretreatment unit in this client's write request interface processing unit 210 with certain adjustment degree of depth, client's write request that write request message queue buffering client write request interface processing unit 210 is received, when appearring in client's write request, can play peak bandwidth certain " peak disappears " effect, write request formation pretreatment unit is read according to the client after resolving, the BANK address of write request rearranges into a plurality of reading based on each BANK, the write request formation, and with above-mentioned a plurality of reading, the write request formation disperses to mail to concurrently writes asynchronous converting unit, that is to say will give concurrently based on client's write request of different B ANK at one time and write asynchronous converting unit, make client's write request at interface with regard to parallelization.
Client's read request interface processing unit 211 is similar with client's write request interface processing unit 210, it also is provided with BANK address, row address and column address decoder, above-mentioned demoder is used to parse client's read request address, and this address is corresponding with the respective memory unit of corresponding BANK.Also be provided with read request message queue and read request queue pretreatment unit in client's read request interface processing unit 211 with certain depth, " peak disappears " effect is played in the read request message queue when peak bandwidth appears in client's read request, and the read request queue pretreatment unit is used for read request is resequenced by the input sequence of read request, makes the client can directly use the data of reading.Specific practice is, by being provided with first, second liang of cover pointer is indicated the read-out position of read request message queue in client's read request interface processing unit and the writing position in the read request pretreatment unit respectively, this is first years old, second pointer is responsible for control by reading client, as read pointer just can add 1 after reading the data block of a read request correspondence, the indication next one is treated reading location, the read data of other positions if the read data of this position correspondence is not ready for is because out of order execution and ready words, read the client and still can not read this position data, be ready to up to this position data.
In the actual system, the client clock territory is different with the DDR clock zone usually, and generally speaking, DDR adopts very high clock to obtain higher performance, so client's reading and writing request must have asynchronous transfer process before entering the processing of DDR clock zone; The asynchronous conversion 213 of asynchronous converting unit 212 of write request and read request adopts common " making a call to 2 claps " mode to carry out asynchronous conversion, and DDR clock zone and client clock territory are complementary;
Write request arbitration unit 214 and read request arbitration unit 215 determine that respectively the client writes, the priority ranking of read request, earlier processed according to the client to the request of the demand decision limit priority of bandwidth, write request arbitration unit 214 and read request arbitration unit 215 are arbitrated a plurality of reading and writing requests in the reading and writing request queue of each BANK respectively, and generate a plurality of reading and writing buffer queues according to priority orders and be buffered in the reading and writing buffer queue unit 217,216;
Write buffer queue 216 and read buffer queue 217 be write, the read command pipeline, have the function of first in first out; Because above-mentioned asynchronous conversion and arbitration meeting certain processing time of loss, and follow-up BC control module unit 218 and MC control module unit 219 processing speeds are very fast, can cause BC control module unit 218 and MC control module unit 219 often to be in like this and not ask manageable " hunger " state; Write buffer queue 216 and read buffer queue 217 and can guarantee that the request number of unit 218 and unit 219 is abundant.
Step 310: check whether the reading and writing request is arranged, if the reading and writing request is arranged, go to step 311, otherwise return the beginning idle condition;
Step 311: whether page or leaf hits to check the reading and writing request, directly goes to step 317 if page or leaf hits, otherwise goes to step 312;
Step 312: whether the BANK that checks reading and writing request correspondence closes, and goes to if just closed
Step 313: generate charge command for the first time;
Step 314: check whether the charge protection time is satisfied, goes to step 315 if satisfied, otherwise continue to check whether the charge protection time is satisfied;
Step 315: generate activation command;
Step 316: check whether satisfy, go to step 317 if satisfied if activating guard time, otherwise continue to check whether activate guard time satisfies;
Step 317: generate the reading and writing order;
Step 318: whether have new reading and writing request, if there is new reading and writing request to go to step 311, otherwise go to step 319 if checking;
Step 319: check that being activated to of this BANK close minimum guard time and whether satisfy, go to step 320 if satisfy; Otherwise go to step 318;
Step 320: generate charge command for the second time, this charge command is finished " closing page or leaf " function, initiatively closes BANK, and purpose is in order to save next time shut-in time of same page reading and writing request not with BANK.
Step 321: check whether the charge protection time is satisfied, goes to end step if satisfied, otherwise continue to check whether the charge protection time is satisfied.
Each BC control module 218 is parallel carries out above-mentioned flow process simultaneously, if client's reading and writing request can be assigned to different BANK preferably, client's reading and writing request almost can walk abreast resolvedly so, has greatly reduced wait blocking time.
The order that BC control module 218 generates is not directly to give the DDR command line, so the order that BC control module 218 sends can not carried out immediately, and need MC main control unit unit 219 to gather the order of each BANK and consider refresh command after produce the DDR order and give DDR command line by unit 219.
The read-write of DDR is switched frequently also can bring very big data bus loss, as write to switch to and read, write burst and must wait on WTR cycle (time parameter of the DDR) command line after last data and read command could occur, read command must be waited for again and just occur the data of reading on CL cycle (time parameter of DDR) the DDR data bus afterwards; Read to switch to when writing, the conversion space of 1 clock period also must be arranged on the data bus.Therefore reducing unnecessary read-write switching is the important behave that improves the DDR bus efficiency, MC main control unit unit 219 is as ACTIVE CONTROL side among the present invention, read with each BC control module 218 Collaborative Control binding, write order, the concrete practice as shown in Figure 4, be provided with the collaborative status unit of MC positioning indicator and MC in the MC main control unit 219, this MC positioning indicator has writes 410, write transition 411, read 412, read transition 413, refresh protection 414 and refresh 415 6 kinds of state Warning Marks of protection releasing, be provided with the collaborative status unit of BC in the BC control module 218 and read at each, write request all is provided with a BC positioning indicator, and this BC positioning indicator has write gate 420, write and read transition 421, read gate 422, read and write transition 423, refresh 424 and refresh the protection 425 6 kinds of state Warning Marks;
When MC main control unit 219 when DRAM sends write request, the Status Flag of its positioning indicator is set to write 410, the collaborative status unit of MC sends to the collaborative status unit of BC and writes collaborative indication simultaneously, the Status Flag of the collaborative status unit BC positioning indicator of BC is set to write gate 420, and gating whole write buffer queue 216, close whole buffer queues 217 of reading, MC main control unit 219 can only respond write request writing in the time period of configuration at this moment, do not handle read request, write the time period finish after the Status Flag of MC positioning indicator be set to write transition 411, after each write request was sent, the Status Flag of this BC positioning indicator is set to write read transition 421;
When the Status Flag of MC positioning indicator when writing transition 411, the collaborative status unit of MC sends to the collaborative status unit of BC and writes the collaborative indication of transition, the Status Flag of the collaborative status unit BC positioning indicator of BC is set to write reads transition 421, and the remaining buffer queue of writing of gating, close whole buffer queues of reading, wait all remaining write requests all processed after, MC main control unit 219 sends read request to DRAM, and its Status Flag is set to read 412, and the Status Flag of all BC positioning indicators all is set to read 422;
When the Status Flag of MC positioning indicator when reading 412, the collaborative status unit of MC sends to the collaborative status unit of BC and reads collaborative indication, the Status Flag of the collaborative status unit BC positioning indicator of BC is set to read 422, and gating whole read buffer queue 217, close whole buffer queues 216 of writing, MC main control unit 219 can only respond read request in the read time section of configuration at this moment, processing write requests not, the Status Flag of MC positioning indicator was set to read transition 413 after the read time section finished, after each read request was sent, the Status Flag of this BC positioning indicator is set to read write transition 423;
When the Status Flag of MC positioning indicator when reading transition 413, the collaborative status unit of MC sends to the collaborative status unit of BC and reads the collaborative indication of transition, the collaborative status unit of BC is write transition 423 with the Status Flag of BC positioning indicator for reading, wait all remaining read requests all processed after, the Status Flag of MC positioning indicator is set to write 410, and the Status Flag of all BC positioning indicators all is set to write gate 420.
When MC main control unit 219 when DRAM sends read request, the Status Flag of its positioning indicator is set to read 412, the collaborative status unit of MC sends to the collaborative status unit of BC and reads collaborative indication simultaneously, the Status Flag of the collaborative status unit BC positioning indicator of BC is set to read gate 422, and gating whole read buffer queue 217, close whole buffer queues 216 of writing, MC main control unit 219 can only respond read request writing in the time period of configuration at this moment, processing write requests not, the Status Flag of MC positioning indicator was set to read transition 413 after the read time section finished, after each read request was sent, the Status Flag of this BC positioning indicator is set to read write transition 423;
When the Status Flag of MC positioning indicator when reading transition 413, the collaborative status unit of MC sends to the collaborative status unit of BC and reads the collaborative indication of transition, the Status Flag of the collaborative status unit BC positioning indicator of BC is set to read writes transition 423, and the remaining buffer queue of reading of gating, close whole buffer queues of writing, wait all remaining read requests all processed after, MC main control unit 219 sends write request to DRAM, and its Status Flag is set to write 410, and the Status Flag of all BC positioning indicators all is set to write 420;
When the Status Flag of MC positioning indicator when writing 410, the collaborative status unit of MC sends to the collaborative status unit of BC and writes collaborative indication, the Status Flag of the collaborative status unit BC positioning indicator of BC is set to write 420, and gating whole write buffer queue 216, close whole buffer queues 217 of reading, MC main control unit 219 can only respond write request in the read time section of configuration at this moment, do not handle read request, the Status Flag of MC positioning indicator was set to write transition 411 after the read time section finished, after each write request was sent, the Status Flag of this BC positioning indicator is set to write read transition 421;
When the Status Flag of MC positioning indicator when writing transition 411, the collaborative status unit of MC sends to write to the collaborative status unit of BC reads collaborative indication, the collaborative status unit of BC is read transition 421 with the Status Flag of BC positioning indicator for writing, wait all remaining write requests all processed after, the Status Flag of MC positioning indicator is set to read 412, and the Status Flag of all BC positioning indicators all is set to read gate 422.
When the Status Flag of BC positioning indicator when refreshing 424; the Status Flag of BC positioning indicator is set to refresh protection 425; the collaborative status unit of BC sends the protection instruction to the collaborative status unit of MC simultaneously; MC main control unit unit 219 response refresh commands; send protection releasing instruction etc. the collaborative status unit of refresh requests end back BC to the collaborative status unit of MC, this moment, the MC main control unit can receive the reading and writing request.
Among the present invention refresh command being placed on read command and carrying out afterwards, is because read request is higher than write request to the requirement of delaying time.By above-mentioned 2 collaborative status unit collaborative works, client's reading and writing request binding separately within a certain period of time can be produced write the two or more syllables of a word together and connects the interpreting blueprints case, eliminate frequent switching and brought bandwidth lose; Though the way of order binding can be introduced certain response time-delay, control module had also correspondingly improved the response speed of client requests after bandwidth elevated.
During the DRAM of data volume once export greater than to(for) the data volume of client's reading and writing request, the present invention can cut client's reading and writing request, if a large amount of data volumes that once request occurs have only the situation of 1BYTE, the present invention can reduce the data bit width of the DDR2 that selects for use, reduce loss bandwidth on the DDR2 bus, to satisfy the application of DRAM interface.Be provided with data partitioning unit in the MC main control unit, this data partitioning unit is read with one of client, whether the size of write request data block is whether basis for estimation obtains needs to be read this greater than the base memory unit of DRAM, the judged result that the write request data block is cut apart, when showing, judged result need read this, when the write request data block is cut apart, at first determine the address boundary of DRAM burst block (data quantity transmitted), calculate then and cut apart corresponding data block size and the start address of each request of back, and send read-write requests after cutting apart to DRAM by the mode continuous of same page.
The present invention also provides the DRAM storage controlling method, may further comprise the steps:
A10, client's reading and writing request carried out address decoder after, rearrange into a plurality of reading and writing request queues according to the BANK address, and the back is parallel synchronously sends with above-mentioned a plurality of reading and writing request queues based on each BANK based on each BANK;
Write request formation based on each BANK in this step generates by following steps:
A101, client's write request of receiving put into write request message queue with certain configurable deep;
A102, successively client's write request in write request message queue exit is carried out address resolution;
A103, according to the BANK address of resolving back client's write request it is rearranged and to form a plurality of write request formations, write in the write request pretreatment unit respectively based on each BANK;
Parallel sending after A104, a plurality of write request formation synchronously based on each BANK.
Read request queue based on each BANK generates by following steps:
A111, client's read request of receiving put into read request message queue with certain configurable deep;
A112, order are carried out address resolution with client's read request in read request message queue exit;
A113, according to the BANK address of resolving back client's read request it is rearranged and to form a plurality of read request queue based on each BANK, write respectively in the read request pretreatment unit, in this step, the current read-out position of the first pointed read request message queue is set, the writing position of this read request of second pointed in the read request pretreatment unit is set, and the read request corresponding with first pointer writes the relevant position in the read request pretreatment unit of second pointed;
A114, the back is parallel synchronously sends with a plurality of read request queue based on each BANK.
A20, respectively each is arbitrated based on a plurality of reading and writing requests in the reading and writing request queue of each BANK, and rank according to priority orders;
A30, according to each based on the reading and writing request in the reading and writing request queue of each BANK, generate separately reading and writing request command and activation command and/or precharge command respectively;
A40, the reading and writing request command is delivered to command line; and, insert the activation command and/or the precharge command of the reading and writing command request in other BANK reading and writing request queues before the reading and writing command request order in this BANK reading and writing request queue satisfying under the DRAM reading and writing prerequisite in protection time limit.
In the said method, MC main control unit and BC control module associated treatment, the specific implementation method is as previously mentioned.
During greater than DRAM interface data bit wide, this method can be cut client's reading and writing request for the data width of client's reading and writing request, and the specific implementation method as previously mentioned.
The effect of method provided by the invention being brought with an instantiation is described in detail below.
This instantiation is, one group of client requests is W0/R0/W1/R1/W2/R2/W3/R3 sequentially, and wherein W0 represents the write request to BANK0, and R0 is the read request to BANK0, but read-write requests address same page not, the rest may be inferred for other.The sequential of DDR2 protection restriction is in the sequential chart 5: CL (CAS latent period) is 3T; Tras (being activated to the shut-in time) is 8T; Trrd (being activated to activationary time) is 2T; Twr (writing data to the duration of charging) is 3T; Twtr (writing data to the read command time) is 2T; Trcd (being activated to the read write command time) is 3T, and Trp (being charged to activationary time) is 3T, and T is the clock period.
Fig. 5 is the sequential chart by traditional control method; owing to do not support many BANK ping-pong operation and order binding; access command is progressively carried out according to the guardtime restriction of DRAM in order successively; as shown in Figure 5; finishing one group of top required instruction of client requests is 8 activation ACT, and 8 charging PRE write WR for 4; read RD for 4, need 104T to finish above-mentioned 8 client requests altogether.
Fig. 6 adopts access control method access sequential chart of the present invention; owing to support parallel ping-pong operation of BANK and order binding; though required instruction is the same with number of instructions among Fig. 5; but charging and activation all are hidden into effective stage of data bus; when only the write-read after the binding switches since the guardtime limitation loss 5T; only need 42T just to finish all client requests altogether, improved the utilization factor of data bus greatly.
The present invention is not limited to above-mentioned preferred forms, and anyone should learn the structural change of making under enlightenment of the present invention, and every have identical or close technical scheme with the present invention, all falls within protection scope of the present invention.
Claims (10)
1.DRAM storage controlling method is characterized in that may further comprise the steps:
A10, client's reading and writing request carried out address decoder after, rearrange into a plurality of reading and writing request queues according to the BANK address, and the back is parallel synchronously sends with above-mentioned a plurality of reading and writing request queues based on each BANK based on each BANK;
A20, respectively each is arbitrated based on a plurality of reading and writing requests in the reading and writing request queue of each BANK, and rank according to priority orders;
A30, according to each based on the reading and writing request in the reading and writing request queue of each BANK, generate separately reading and writing request command and activation command and/or precharge command respectively;
A40, the reading and writing request command is delivered to command line; and, insert the activation command and/or the precharge command of the reading and writing command request in other BANK reading and writing request queues before the reading and writing command request order in this BANK reading and writing request queue satisfying under the DRAM reading and writing prerequisite in protection time limit.
2. DRAM storage controlling method as claimed in claim 1 is characterized in that, the write request formation based on each BANK in the steps A 10 generates by following steps:
A101, client's write request of receiving put into write request message queue with certain configurable deep;
A102, successively client's write request in write request message queue exit is carried out address resolution;
A103, according to the BANK address of resolving back client's write request it is rearranged and to form a plurality of write request formations, write in the write request pretreatment unit respectively based on each BANK;
Parallel sending after A104, a plurality of write request formation synchronously based on each BANK.
3. DRAM storage controlling method as claimed in claim 1 is characterized in that, in the steps A 10, generates by following steps based on the read request queue of each BANK:
A111, client's read request of receiving put into read request message queue with certain configurable deep;
A112, order are carried out address resolution with client's read request in read request message queue exit;
A113, according to the BANK address of resolving back client's read request it is rearranged and to form a plurality of read request queue based on each BANK, write respectively in the read request pretreatment unit, in this step, the current read-out position of the first pointed read request message queue is set, the writing position of this read request of second pointed in the read request pretreatment unit is set, and the read request corresponding with first pointer writes the relevant position in the read request pretreatment unit of second pointed;
A114, the back is parallel synchronously sends with a plurality of read request queue based on each BANK.
4. as claim 1,2 or 3 described DRAM storage controlling methods, it is characterized in that, in steps A 40, read each BANK reading and writing request queue successively according to the current reading and writing solicited status sign that is sent to command line.
5. the storage controlling method of raising DRAM data bus efficiency as claimed in claim 4, it is characterized in that, when the data width of a reading and writing request during greater than DRAM interface data bit wide, this reading and writing request msg is cut apart according to DRAM interface data bit wide, and, send reading and writing request after cutting apart to DRAM by the mode continuous of same page according to size of data and the start address of cutting apart each reading and writing request correspondence of back.
6.DRAM memory control device, this DRAM is made up of a plurality of BANK, be provided with a plurality of basic units of storage of determining by row address and column address respectively among each BANK, described memory control device comprises some reading and writing request interface processing units, asynchronous converting unit, with BANK number corresponding reading and writing request queue arbitration unit and BANK control module and reading and writing buffer queue unit and MC main control unit, it is characterized in that:
Described reading, be respectively equipped with in the write request interface processing unit and read, write request address decoder and reading, write request formation pretreatment unit, the BANK address, row address and column address decoder parse reading of client, the write request address, this address is corresponding with the corresponding basic unit of storage of corresponding BANK, described reading, write request formation pretreatment unit is read according to the client after resolving, the BANK address of write request rearranges into a plurality of reading based on each BANK, the write request formation, and with above-mentioned a plurality of reading based on each BANK, the write request formation walks abreast to mail to synchronously through asynchronous converting unit and reads, write request formation arbitration unit;
Described reading and writing request queue arbitration buffer cell is arbitrated a plurality of reading and writing requests in the reading and writing request queue of each BANK respectively, and generates a plurality of reading and writing buffer queues according to priority orders and be buffered in the reading and writing buffer queue unit;
Described BANK control module, according to the reading and writing request in each BANK reading and writing request queue in the reading and writing buffer queue unit, generate separately reading and writing request command and activation command and/or precharge command respectively, the parallel MC main control unit that mails to of above-mentioned reading and writing request command and activation command and/or precharge command;
The MC main control unit; the reading and writing request command of receiving is delivered to command line; and, insert the activation command and/or the precharge command of the reading and writing command request in other BANK reading and writing request queues before the reading and writing command request order in this BANK reading and writing request queue satisfying under the DRAM reading and writing prerequisite in protection time limit.
7. DRAM memory control device as claimed in claim 6 is characterized in that also being provided with the solicited message queue unit with certain configurable deep in the described reading and writing request interface processing unit.
8. as claim 6 or 7 described DRAM memory control devices, it is characterized in that being provided with first, second pointer in client's read request interface processing unit, indicate the read-out position of read request message queue in client's read request interface processing unit and the writing position in the read request pretreatment unit respectively.
9. DRAM memory control device as claimed in claim 8, it is characterized in that being provided with in the MC main control unit the collaborative status unit of MC positioning indicator and MC, this MC positioning indicator has to be write, writes transition, read, read transition, refreshes protection and refresh six kinds of state Warning Marks of protection releasing, be provided with the collaborative status unit of BC in the BC control module and at each reading and writing request one BC positioning indicator be set all, this BC positioning indicator has write gate, write and read transition, read gate, read and write transition, refresh and refresh six kinds of state Warning Marks of protection;
When the MC main control unit when DRAM sends write request or read request, the Status Flag of its positioning indicator is set to write or read, the collaborative status unit of MC sends to the collaborative status unit of BC and writes collaborative indication or read collaborative indication simultaneously, the Status Flag of the collaborative status unit BC positioning indicator of BC is set to write gate or read gate, and whole the writing buffer queue or read buffer queue of gating, close whole reading buffer queue or write buffer queue, this moment, the MC main control unit can only respond write request or read request at the write or read of configuration in the time period, do not handle read request or write request, the Status Flag of MC positioning indicator was set to write transition or reads transition after the write or read time period finished, after each write request or read request were sent, the Status Flag of this BC positioning indicator is set to write to be read transition or reads and write transition;
When the Status Flag of MC positioning indicator when writing transition or reading transition, the collaborative status unit of MC sends to the collaborative status unit of BC and writes the collaborative indication of transition or read the collaborative indication of transition, the Status Flag of the collaborative status unit BC positioning indicator of BC is set to write to be read transition or reads and write transition, and gating is remaining writes buffer queue or read buffer queue, close whole reading buffer queue or write buffer queue, wait after all remaining write requests or read request all handle, the MC main control unit sends read request or write request to DRAM, and its Status Flag is set to read or write, and the Status Flag of all BC positioning indicators all is set to read or write;
When the Status Flag of MC positioning indicator when reading or writing, the collaborative status unit of MC sends to the collaborative status unit of BC and reads collaborative indication or write collaborative indication, the Status Flag of the collaborative status unit BC positioning indicator of BC is set to read or write, and whole the reading buffer queue or write buffer queue of gating, close whole writing buffer queue or read buffer queue, this moment, the MC main control unit can only respond read request or write request reading or writing in the time period of configuration, not processing write requests or read request, read or write the time period finish after the Status Flag of MC positioning indicator be set to read transition or write transition, after each read request or write request were sent, the Status Flag of this BC positioning indicator is set to read to be write transition or writes and read transition;
When the Status Flag of MC positioning indicator when reading transition or writing transition, the collaborative status unit of MC sends to the collaborative status unit of BC and reads the collaborative indication of transition or write the collaborative indication of transition, the collaborative status unit of BC is write the Status Flag of BC positioning indicator transition or is write and read transition for reading, wait after all remaining read requests or write request all handle, the Status Flag of MC positioning indicator is set to write or read, and the Status Flag of all BC positioning indicators all is set to write gate or read gate;
When the Status Flag of BC positioning indicator when refreshing; the Status Flag of BC positioning indicator is set to refresh protection; the collaborative status unit of BC sends the protection instruction to the collaborative status unit of MC simultaneously; MC main control unit cell response refresh command; after refresh command execution end; the collaborative status unit of BC sends to the collaborative status unit of MC and refreshes protection releasing instruction, and the MC main control unit was in and received the reading and writing solicited status this moment.
10. DRAM memory control device as claimed in claim 9, it is characterized in that also comprising data partitioning unit, this data partitioning unit is read with one of client, whether the data width of write request is whether basis for estimation obtains needs to be read this greater than DRAM interface data bit wide, the judged result that the write request data block is cut apart, when showing, judged result need read this, when the write request data block is cut apart, this is read, the data based DRAM interface data of write request bit wide is cut apart, calculate and cut apart corresponding data block size and the start address of each request of back, and send read-write requests after cutting apart to DRAM by the mode continuous of same page.
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