CN101788939B - Controller status-monitoring device and method - Google Patents
Controller status-monitoring device and method Download PDFInfo
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- CN101788939B CN101788939B CN2009100775466A CN200910077546A CN101788939B CN 101788939 B CN101788939 B CN 101788939B CN 2009100775466 A CN2009100775466 A CN 2009100775466A CN 200910077546 A CN200910077546 A CN 200910077546A CN 101788939 B CN101788939 B CN 101788939B
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Abstract
The invention discloses controller status-monitoring device, which consists of an information acquisition module, a self information storage module, an information synchronization module and a peer information storage module. The invention also provides a controller status-monitoring method, which can acquire and synchronize the information of each component of a controller to a peer controller and receive the information of each component of the peer controller synchronized by the peer controller, so that two or more controllers can monitor the information of each component of one another. The adoption of the device and the method can ensure that two or more controllers can monitor the information of each component of one another, thus preventing the following problem that: since the failure of the components of the peer controller cannot be timely discovered, the performance of a disk array is affected, and even the storage operation is interrupted.
Description
Technical field
The present invention relates to disk array technology, relate in particular to a kind of controller status-monitoring device and method.
Background technology
Disk array comprises a plurality of hard disks, and through each hard disk of controller centralized management, accomplishes the read-write operation to disk array.In the common disk array two or more controllers are set; By these each hard disks of controller coordinated management; After wherein certain or certain several disabling controllers are imitated; Can its task transfers of being responsible for be handled to other controllers, avoid causing problem, and then improve the reliability of disk array the operation disruption of disk array because of the inefficacy of controller; And after this controller recovers normally; Being transferred before of task is given back this controller again to be handled; Make each controller associated treatment task of whole magnetic disk array; Avoid the task of the two or more controllers of the long-term burden of a controller, and influence the performance of storage system and the serviceable life of controller.
And for realize above-mentioned when controller lost efficacy its being responsible for of task can in time be taken over;, in time to return by the controller that lost efficacy the function of its being responsible for of task after recovering; In above-mentioned disk array with a plurality of controllers; Each controller all needs to monitor the state to square controller in real time, and present monitor mode mainly is divided into the hardware and software dual mode.
Wherein, the basic thought of software approach commonly used is: a controller is replied square controller regularly to square controller is sent information, keeps information interaction, when information interaction takes place to think that then wherein a square controller lost efficacy when unusual.For example the patent No. is the United States Patent (USP) of US005975738A, is the state that comes supervisory control device through the mode of software, and its concrete implementation method is: use a privately owned LUN (LUN) as the communication district; Controller A goes up write data to this LUN, and controller B reads, and controller A re-uses another paths data are sent to controller B; Controller B is two piece of data relatively, if inconsistent, think that then controller A lost efficacy; Controller B restart controller A, and the work of taking over controller A.
The basic thought of hardware approach commonly used is: the state of supervisory control device hardware, if take place unusually then think inefficacy.For example the patent No. is the United States Patent (USP) of US20060010351A1, and it uses central processing unit (CPU) state of house dog monitor controller, occurs promptly thinking unusually that controller lost efficacy, and square controller is restarted this controller and taken over this controller work.
But at present the hardware and software monitor mode all can only monitor the CPU state, therefore, if during the remaining component inefficacy except that CPU of controller; Can not in time find its inefficacy; I.e. timely switch controller and repairing, thus performance of disk arrays influenced, even cause storage operation to be interrupted; Wherein, the remaining component except that CPU of said controller comprises hard disk, optical-fibre channel (FC) chip and fan etc.
Summary of the invention
In view of this; Fundamental purpose of the present invention is to provide a kind of controller status-monitoring device and method; Make two or more controllers can monitor the information of each assembly each other; Thereby avoid because of can not in time finding component failures, and influence performance of disk arrays, even the problem that causes storage operation to be interrupted to square controller.
For achieving the above object, technical scheme of the present invention is achieved in that
A kind of controller status-monitoring device, this device comprises:
The information acquisition module is used to obtain the operation information of each assembly of controller, and each assembly of said controller comprises CPU, FC chip, hard disk, the fan of controller; And be used for the information of being obtained is write the self information memory module;
The self information memory module is used to store the operation information of said each assembly of controller;
The information synchronization module is used for the operation information of each assembly of controller of being stored synchronous extremely to square controller; And be used to receive to square controller the operation information that comes synchronously to each assembly of square controller, received information is write the other side's information storage module;
The other side's information storage module, be used to store to square controller the operation information that comes synchronously to each assembly of square controller;
The central processor CPU of controller is used to read the operation information to each assembly of square controller that said the other side's information storage module is stored, and judges the duty to square controller according to the information that is read; Control square controller according to judged result.
Further, said information acquisition module and information synchronization module are realized by the device that PLD perhaps has microprocessor.
Further, said self information memory module and the other side's information storage module are realized by SRAM SRAM.
Further, the CPU of controller also is used to read the operation information of each assembly of controller that said self information memory module stored, each assembly of supervisory control device.
The present invention also provides a kind of controller status-monitoring method, and this method comprises:
Obtain the operation information and the storage of each assembly of controller, each assembly of said controller comprises CPU, FC chip, hard disk, the fan of controller;
The operation information of each assembly of controller of being stored is synchronous extremely to square controller;
Receive and store the operation information that square controller is come synchronously to each assembly of square controller;
The central processor CPU of controller reads the operation information to each assembly of square controller of storage, and judges the duty to square controller according to the information that is read; Control square controller according to judged result.。
Further, before the said operation information that obtains each assembly of controller was also stored, this method further comprised: confirm in running order to square controller.
It is further, said that control to square controller is according to judged result:
If A is in normal condition to square controller, execution in step B then; If unusual, execution in step C;
B, confirm whether controller has taken over the work to square controller,, then adapter is given back square controller the work of square controller, return and carry out said operation information and storage of obtaining each assembly of controller if taken over; Do not take over if, then return and carry out said operation information and storage of obtaining each assembly of controller;
C, take over this work, and control order closes to square controller to square controller, return carry out said confirm in running order to square controller.
The present invention through with the information synchronization of each assembly of controller that obtains to square controller; And receive the synchronous next information of square controller to each assembly of square controller; Make two or more controllers can monitor the information of each assembly each other; Thereby avoid because of can not in time finding the other side's component failures each other, and influence performance of disk arrays, even the problem that causes storage operation to be interrupted.Apparatus and method provided by the present invention also have following advantage and characteristics:
1, accomplishes controller by device according to the invention and to the mutual monitoring of the information of each assembly of square controller; Save the resource of controller CPU; And can avoid the cpu busy of controller; Can not on time when square controller is sent information, can cause square controller is not takeed for the problem that controller lost efficacy because of receive information at setting-up time;
2, the CPU of controller can be through reading said self information memory module institute each assembly of canned data supervisory control device, is used to scan the resource of peripheral chip when having saved its peripheral chip of cpu monitor of controller.
Description of drawings
Fig. 1 is the structural representation of embodiment of the invention controller status-monitoring device;
Fig. 2 realizes the process flow diagram of controller status-monitoring for adopting controller status-monitoring device according to the invention.
Embodiment
Basic thought of the present invention is: through with the information synchronization of each assembly of controller that obtains to square controller; And receive the synchronous next information of square controller to each assembly of square controller; Make two or more controllers can monitor the information of each assembly each other; Thereby avoid because of can not in time finding component failures, and influence performance of disk arrays, even the problem that causes storage operation to be interrupted to square controller.
Can monitor other one or more controllers simultaneously from body controller, and independent mutually.Among this paper square controller is referred to except that other any controller from body controller.
The structure of embodiment of the invention controller status-monitoring device is as shown in Figure 1, comprising: information acquisition module, self information memory module, information synchronization module and the other side's information storage module.
The information acquisition module is used to obtain the information of each assembly of controller; And be used for the information of being obtained is write the self information memory module;
Wherein, each assembly of controller comprises the CPU, FC chip, hard disk, fan of controller etc., and these component failures if can not get timely reparation, can influence performance of disk arrays, even causes storage operation to be interrupted.For example, when hard disk lost efficacy, can not in time change subsequent use hard disk, continue read-write faulty hard disk data, can influence performance of disk arrays, make operating system can not in time obtain institute's canned data in this hard disk; CPU and FC chip then are the cores of storage operation, and its fault can directly cause the interruption of storage operation.
The self information memory module, the information that is used to store said each assembly of controller;
The information synchronization module is used for the information synchronization of each assembly of controller of being stored to square controller; And be used to receive to square controller the information to each assembly of square controller of coming synchronously, received information is write the other side's information storage module;
The other side's information storage module, be used to store to square controller the information to each assembly of square controller of coming synchronously.
Wherein, said information acquisition module and information synchronization module can perhaps be had the device realization of microprocessor, for example field programmable gate array (FPGA) or single-chip microcomputer by PLD; Said self information memory module and the other side's information storage module can be realized by SRAM (SRAM).
During work; The said device of the embodiment of the invention links to each other with controller; The CPU of controller reads the information to each assembly of square controller that said the other side's information storage module is stored, and judges the duty to square controller according to the information that is read, and controls square controller according to judged result; And the information that can read each assembly of controller that said self information memory module stored, each assembly of supervisory control device; Wherein, specifically comprise according to judged result control the other side controller:
If square controller is in normal condition, confirm that controller taken over the work to square controller, then controller is given back adapter to square controller to the work of square controller; If unusual to square controller, then controller is taken over this work to square controller, and control order is closed square controller.
Here; Also synchronous through the information of obtaining each assembly of controller extremely to square controller; Make to square controller can each assembly of monitor controller information, and, make controller can monitor information to each assembly of square controller through receiving information that square controller is come synchronously to each assembly of square controller; Thereby avoid in time to find component failures to square controller because of controller; Or because of can not in time finding the component failures of controller self to square controller, and influence performance of disk arrays, even the problem that causes storage operation to be interrupted.And device according to the invention is installed at controller with on to square controller; Accomplish controller and to the mutual monitoring of the information of each assembly of square controller by device according to the invention; Save the resource of controller CPU; And can avoid the cpu busy of controller, can not on time when square controller is sent information, can cause square controller is not takeed for the problem of controller inefficacy because of receive information at setting-up time; And the CPU of controller is through reading said self information memory module institute each assembly of canned data supervisory control device, and when having saved the monitoring CPU peripheral chip, CPU is used to scan the resource of peripheral chip.
Adopt controller status-monitoring device according to the invention to realize that the flow process of controller status-monitoring is as shown in Figure 2, may further comprise the steps:
Step 201: confirm in running order to the controller status-monitoring device of square controller;
Here, if not in running order, promptly, then do not carry out following steps to the square controller shutdown to the controller status-monitoring device of square controller.
Step 202: the information acquisition module obtains the information of each assembly of controller and is stored to the self information memory module.
Step 203: the information synchronization module with the information synchronization of each assembly of controller of being stored to square controller.
Step 204: the information synchronization module receive and storage to square controller come synchronously to the information of each assembly of square controller to the other side's information storage module.
Step 205: controller CPU judges according to the other side's information storage module institute canned data whether square controller is in normal condition, if square controller is in normal condition, then execution in step 206; Otherwise, execution in step 207; Saidly square controller is in normal condition comprises: square controller is started after reparation, and its state of monitoring control devices is normal, and like this, the work to square controller that controller can will be taken over is given back square controller, and it is monitored; Square controller is kept normal condition at work, and at this moment, the controller continuation is monitored it and is got final product.
Here, judge that whether square controller is in normal condition specifically comprises:
Judgement if each assembly on the square controller is in normal condition, thinks then that controller is a normal condition to the information of each assembly of square controller; If wherein any one or more assemblies are unusual, think that then controller is unusual.The information of said assembly comprises the operation information of assembly, the date and time information of real-time timepiece chip RTC for example, and the rotating speeds of fan etc. also can comprise the work state information of assembly etc.Can confirm according to the information of assembly whether corresponding assembly is in normal condition.
Step 206: controller CPU confirms whether controller has taken over the work to square controller, if taken over, promptly thinks square controller is repaired, execution in step 2061; Do not take over if, then return step 202.
Step 2061: controller is given back adapter to square controller to the work of square controller, returns step 202.
Step 207: controller is taken over this work to square controller, and control order closes square controller, returns step 201.
Below to realize that through FPGA and SRAM controller status-monitoring according to the invention is an example, specify the course of work of device according to the invention, and adopt device according to the invention to realize the flow process of controller status-monitoring.
FPGA, SRAM1 and SRAM2 are set in controller.
Wherein, FPGA links to each other with the I2C interface of each assembly of controller, links to each other with the CPU of controller through peripheral bus interface (PBI) bus through twin wire serial (I2C) bus, and FPGA also is connected respectively with SRAM2 with SRAM1; SRAM1 is used for the information of each assembly of memory controller as the self information memory module of controller; SRAM2 is used to store the information to each assembly of square controller as the other side's information storage module of controller.
FPGA comprises that Logic control module, I2C read-write control module, SRAM read and write control module, FPGA monitoring module and direct memory access (DMA) control module;
Wherein, Logic control module control I2C reads and writes control module, realizes the function of the information of obtaining each assembly of controller of said information acquisition module; Logic control module control SRAM read-write control module; Realize that the information with each assembly of controller that is obtained of said information acquisition module writes the function of said self information memory module, and realize that said information synchronization module writes the received information to each assembly of square controller the function of said the other side's information storage module; The DMA control module, realize said information synchronization module with the information synchronization of each assembly of controller of being stored to function to square controller, and receive function synchronously to the information of each assembly of square controller to square controller institute;
Concrete, Logic control module, be used for through control PBI bus and SRAM address/data bus or and the SRAM address/data bus between conversion, control the visit of the CPU of controller to SRAM1 and SRAM2; And be used to control timing for scanning, and each SRAM is carried out the sequential of write operation to each assembly of controller; Wherein, the sequential of I2C agreement is followed in said scanning to each assembly of controller; Following SRAM when SRAM is carried out write operation and write sequential, is that unit writes among the corresponding SRAM with the information of each assembly of controller or to the information of each assembly of square controller with position (bit);
Here, with the processing controls PBI bus of apparatus of the present invention in the controller and SRAM address/data bus or and the SRAM address/data bus between the process of conversion specifically comprise:
If the address signal of PBI bus drops in the memory range of SRAM1, and the SRAM1 chip selection signal is effective, the SRAM1 bus is connected to the PBI bus gets on; Wherein, the concrete steps that the SRAM1 bus are connected to the PBI bus comprise: the read/write signal of SRAM1 is linked on the read/write signal of PBI bus, and data/address wire of SRAM1 is connected on the data/address wire of PBI bus;
If the address signal of PBI bus drops in the memory range of SRAM2, and the SRAM2 chip selection signal is effective, the SRAM2 bus is connected to the PBI bus gets on; Wherein, the concrete steps that the SRAM2 bus are connected to the PBI bus comprise: the read/write signal of SRAM2 is linked on the read/write signal of PBI bus, and data/address wire of SRAM2 is connected on the data/address wire of PBI bus.
I2C reads and writes control module, is used for scanning monitor self each assembly except that CPU, to obtain the information of controller self each assembly except that CPU;
Here, store the driving of controller self the I2C interface of each assembly except that CPU that is provided with in advance in the I2C read-write control module; I2C read-write control module is according to the sequential of I2C agreement, and the driving of operation controller self I2C interface of each assembly except that CPU can be accomplished the scanning to controller self each assembly except that CPU;
SRAM reads and writes control module; Be used for confirming that when CPU visits SRAM1 or SRAM2 and do not conflict, that is, the read-write of PBI bus is invalid; And when SRAM1 or SRAM2 chip selection signal are effective; SRAM1 or SRAM2 are carried out write operation, and the information stores of I2C being read and write each assembly of controller that control module obtains is to SRAM1, or with the DMA control module receive to the information stores of each assembly of square controller in SRAM2;
The FPGA monitoring module is used to show the state to the FPGA of square controller, and the FPGA of square controller is powered on, and this FPGA mode bit is a high level, and to the FPGA power down of square controller, this FPGA mode bit is a low level;
The DMA control module is used for when the FPGA mode bit is high level, and the information synchronization of each assembly of controller to square controller, and is received said information to each assembly of square controller that square controller is come synchronously;
Here; The DMA control module through and to the transmission requests between the DMA control module of square controller, etc. to be connected, successful connection, connection failure, transmission data, receive data, send beginning, send and finish, receive beginning, receive that Signalling exchanges such as end are controlled the information of each assembly of controller and the transmission of Information of each assembly of square controller; Completion with the information synchronization of each assembly of controller to square controller, and the function that receives the said information to each assembly of square controller that square controller is come synchronously.
Adopt said apparatus to realize that the flow process of controller status-monitoring is following:
Step a, FPGA confirm the FPGA of square controller is powered on;
Step b, initialization FPGA, promptly the Logic control module of initialization FPGA, I2C read-write control module, SRAM read and write control module, DMA control module, execution in step c;
Step c, FPGA obtain the information of each assembly of controller, and the information of each assembly of controller that is obtained are write SRAM1, execution in step d;
Obtain the information of each assembly of controller, and the information of each assembly of controller that is obtained write specifically comprising of SRAM1:
The I2C read-write control module of step c1, FPGA is according to the sequential of I2C agreement, and the driving of synchronous operation controller self each assembly except that CPU to scan each assembly, is obtained the information of controller self each assembly except that CPU and write SRAM1;
Said controller self each assembly except that CPU comprises: RTC, PCI-e exchange chip, FC chip, loop chip, fan, obtain the information of controller self each assembly except that CPU and write SRAM1 and specifically comprise;
The concrete grammar that obtains controller self information of each assembly except that CPU comprises:
The I2C of FPGA reads and writes the driving of control module operation controller RTC, obtains the date and time information of RTC; Judge date and time information whether in the reasonable time scope, for example, the time if in the reasonable time scope, then is changed to 1 with this RTC Status Flag greater than 1900 and less than 2499, otherwise, this RTC Status Flag is changed to 0; Obtaining date and time information and RTC Status Flag are stored in the storage space of reserving for RTC among the SRAM1; Here, the storage space of reserving for RTC is the storage space of 0～1kbit of SRAM1, and the capacity of this storage space is 1kbit;
The I2C of FPGA reads and writes the driving of control module operation controller PCI-e exchange chip, obtains temperature information, information of voltage and the work state information of PCI-e exchange chip; Judge this temperature information, information of voltage whether respectively in the temperature range that is provided with in advance, voltage range, if, then this PCI-e exchange chip Status Flag is changed to 1, otherwise, this PCI-e exchange chip Status Flag is changed to 0; The temperature information that is obtained, information of voltage, work state information and PCI-e exchange chip Status Flag put be stored among the SRAM1 in the storage space of reserving for the PCI-e exchange chip; Here, the storage space of reserving for the PCI-e exchange chip is 2kbit～3kbit storage space of SRAM1, and the capacity of this storage space is 1kbit;
The I2C of FPGA reads and writes the driving of control module operation controller FC chip, obtains temperature information, information of voltage and the work state information of FC chip; Judge this temperature information, information of voltage whether respectively in the temperature range that is provided with in advance, voltage range, if, then this FC chip status sign is changed to 1, otherwise, this FC chip status sign is changed to 0; The temperature information that is obtained, information of voltage, work state information and FC chip status sign put be stored among the SRAM1 in the storage space of reserving for the FC chip; Here, the storage space of reserving for the FC chip is 3kbit～4kbit storage space of SRAM1, and the capacity of this storage space is 1kbit;
The I2C of FPGA reads and writes the driving of control module operation controller loop chip, obtains temperature information, information of voltage and the work state information of loop chip; Judge this temperature information, information of voltage whether respectively in the temperature range that is provided with in advance, voltage range, if, then this loop chip status sign is changed to 1, otherwise, this loop chip status sign is changed to 0; The temperature information that is obtained, information of voltage, work state information and loop chip status sign put be stored among the SRAM1 in the storage space of reserving for the loop chip; Here, the storage space of reserving for the loop chip is 4kbit～5kbit storage space of SRAM1, and the capacity of this storage space is 1kbit;
The I2C of FPGA reads and writes the driving of control module operation controller fan, obtains rotating speed, supply voltage and the work state information of fan; Judge this rotating speed, supply voltage whether respectively in the range of speeds that is provided with in advance, supply voltage scope, if, then this fan-status sign is changed to 1, otherwise, this fan-status sign is changed to 0; The rotating speed that is obtained, supply voltage and work state information and fan-status sign put be stored in the storage space of reserving for fan among the SRAM1; Here, the storage space of reserving for fan is 5kbit～6kbit storage space of SRAM1, and the capacity of this storage space is 1kbit;
State on the throne and temperature information are obtained in the driving of each hard disk of I2C read-write control module operation controller of FPGA; Judge whether hard disk on the throne, temperature information whether in predetermined temperature range, if hard disk is on the throne and temperature in preset range, then this disk state sign is changed to 1, otherwise, this disk state sign is changed to 0; The state on the throne that is obtained and temperature information and disk state sign put be stored in the storage space of reserving for hard disk among the SRAM1; Here, the state on the throne of each hard disk takies 1bit, and temperature information takies 8bit, is 1024 in SRAM1, to be the storage space of the capacity of hard disk reservation 9kbit, the i.e. 6kbit of SRAM1～15kbit storage space according to the maximum cascade hard disk of disk array quantity;
The CPU of step c2, controller obtains self temperature information, information of voltage and work state information; Judge this temperature information, information of voltage whether respectively in the temperature range that is provided with in advance, voltage range, if, then the CPU Status Flag is changed to 1; Otherwise, the CPU Status Flag is changed to 0; And the temperature information that is obtained, information of voltage, work state information and CPU Status Flag put be written among the SRAM1 in the storage space of reserving for CPU; Here, the storage space of reserving for CPU is 1kbit～2kbit storage space of SRAM1, and the capacity of this storage space is 1kbit.
Steps d, FPGA are synchronized to square controller through the SRAM1 institute canned data of DMA control module with controller; And receive information that square controller is come synchronously through the DMA control module to each assembly of square controller, and with the information stores that receives in SRAM2;
Here, the concrete steps that the SRAM1 institute canned data of controller are synchronized to square controller comprise:
The DMA control module of controller is sent transmission requests to the DMA control module to square controller, and said transmission requests is carried the Status Flag of each assembly of controller;
After the DMA control module of square controller received transmission requests; Whether the Status Flag of the same components that the Status Flag of checking each assembly of controller that square controller is stored and transmission requests are entrained is consistent; If all consistent, the DMA control module of square controller is refused to connect; As crossing the inconsistent assembly of existence sign; The DMA control module of square controller and the DMA control module of controller are connected; And to the DMA of controller control module transmission data signaling, the information of the inconsistent assembly of request this Status Flag of transmission is after the DMA control module of controller is received and sent data signaling; The information of transmitting the inconsistent assembly of this Status Flag is given the DMA control module to square controller, accomplishes and information synchronization to square controller;
Here, when the Status Flag of assembly changes, just transmit the information of this assembly once more, both can be with the state synchronized of each assembly to square controller, guaranteed controller and, reduced synchronous required data quantity transmitted again the mutual monitoring of square controller.
The CPU of step e, controller is every to read institute's canned data in the SRAM2 set on it at a distance from setting-up time, judges the duty to square controller, if the other side's controller state is normal, then returns step c; Otherwise order is shut down to square controller, and returns step a;
Here, judgement comprises the concrete grammar of the duty of square controller:
Judgement if all component on the square controller is in normal condition, thinks then that to square controller be normal condition to the information of each assembly of square controller; If wherein any one or more assemblies are unusual, then think unusual to square controller;
Judgement comprises the concrete grammar of the assembly duty of square controller:
The Status Flag of assembly is 1, thinks that then this assembly is in normal condition; The Status Flag of assembly is 0, thinks that then this assembly is unusual.
Here, the CPU of controller can also read setting SRAM1 institute canned data on it, obtains the information of each assembly of controller, accomplishes the control to the CPU peripheral chip; Like this, in the time of can saving the control peripheral chip, CPU is used to scan the resource of peripheral chip information.
The above is merely preferred embodiment of the present invention, is not to be used to limit protection scope of the present invention.
Claims (7)
1. a controller status-monitoring device is characterized in that, this device comprises:
The information acquisition module is used to obtain the operation information of each assembly of controller, and each assembly of said controller comprises central processing unit (CPU), optical-fibre channel (FC) chip, hard disk, the fan of controller; And be used for the information of being obtained is write the self information memory module;
The self information memory module is used to store the operation information of said each assembly of controller;
The information synchronization module is used for the operation information of each assembly of controller of being stored synchronous extremely to square controller; And be used to receive to square controller the operation information that comes synchronously to each assembly of square controller, received information is write the other side's information storage module;
The other side's information storage module, be used to store to square controller the operation information that comes synchronously to each assembly of square controller;
The central processor CPU of controller is used to read the operation information to each assembly of square controller that said the other side's information storage module is stored, and judges the duty to square controller according to the information that is read; Control square controller according to judged result.
2. according to the said controller state supervising device of claim 1, it is characterized in that said information acquisition module and information synchronization module are realized by the device that PLD perhaps has microprocessor.
3. according to the said controller state supervising device of claim 2, it is characterized in that said self information memory module and the other side's information storage module are realized by SRAM SRAM.
4. according to claim 1 or 2 or 3 said controller state supervising devices, it is characterized in that the CPU of controller also is used to read the operation information of each assembly of controller that said self information memory module stored, each assembly of supervisory control device.
5. a controller status-monitoring method is characterized in that, this method comprises:
Obtain the operation information and the storage of each assembly of controller, each assembly of said controller comprises CPU, FC chip, hard disk, the fan of controller;
The operation information of each assembly of controller of being stored is synchronous extremely to square controller;
Receive and store the operation information that square controller is come synchronously to each assembly of square controller;
The central processor CPU of controller reads the operation information to each assembly of square controller of storage, and judges the duty to square controller according to the information that is read; Control square controller according to judged result.
6. according to the said controller state method for supervising of claim 5, it is characterized in that before the said operation information that obtains each assembly of controller was also stored, this method further comprised: confirm in running order to square controller.
7. according to the said controller state method for supervising of claim 6, it is characterized in that said control to square controller is according to judged result:
If A is in normal condition to square controller, execution in step B then; If unusual, execution in step C;
B, confirm whether controller has taken over the work to square controller,, then adapter is given back square controller the work of square controller, return and carry out said operation information and storage of obtaining each assembly of controller if taken over; Do not take over if, then return and carry out said operation information and storage of obtaining each assembly of controller;
C, take over this work, and control order closes to square controller to square controller, return carry out said confirm in running order to square controller.
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| CN101916217B (en) * | 2010-08-04 | 2014-08-13 | 中兴通讯股份有限公司 | Method, control device and system for switching a plurality of controllers |
| CN101957786B (en) * | 2010-09-30 | 2014-08-20 | 中兴通讯股份有限公司 | Method and device for realizing start and fault switching control in dual-control system |
| CN104063300A (en) * | 2014-01-18 | 2014-09-24 | 浪潮电子信息产业股份有限公司 | Acquisition device based on FPGA (Field Programmable Gate Array) for monitoring information of high-end multi-channel server |
| CN104793896B (en) * | 2015-02-04 | 2018-02-16 | 深圳神州数码云科数据技术有限公司 | Single the dual control switching method and device of a kind of dual control equipment |
| CN105511347A (en) * | 2015-12-02 | 2016-04-20 | 武汉烽火网络有限责任公司 | System and method for simulating information acquisition process of I2C bus by means of FPGA |
| CN106993241B (en) * | 2017-03-31 | 2020-08-07 | 新华三技术有限公司 | Main control board, fan frame and network equipment |
| CN112257217A (en) * | 2019-07-05 | 2021-01-22 | 上汽通用汽车有限公司 | Automobile controller kernel state monitoring system and method |
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| CN101004587A (en) * | 2006-01-13 | 2007-07-25 | 艾默生过程管理电力和水力解决方案有限公司 | Method for redundant controller synchronization during normal and program mismatch conditions |
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