CN101784994B - 用于高速缓存分区分配的方法和系统 - Google Patents

用于高速缓存分区分配的方法和系统 Download PDF

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Publication number
CN101784994B
CN101784994B CN2008801031989A CN200880103198A CN101784994B CN 101784994 B CN101784994 B CN 101784994B CN 2008801031989 A CN2008801031989 A CN 2008801031989A CN 200880103198 A CN200880103198 A CN 200880103198A CN 101784994 B CN101784994 B CN 101784994B
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cache
speed cache
level
speed
subregion
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CN2008801031989A
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Chinese (zh)
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CN101784994A (zh
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里奥·J·克拉克
小詹姆斯·S·菲尔茨
盖伊·L·格思里
威廉·J·斯塔克
德里克·E·威廉斯
菲利普·威廉斯
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International Business Machines Corp
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International Business Machines Corp
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0811—Multiuser, multiprocessor or multiprocessing cache systems with multilevel cache hierarchies
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0844—Multiple simultaneous or quasi-simultaneous cache accessing
    • G06F12/0846—Cache with multiple tag or data arrays being simultaneously accessible
    • G06F12/0851—Cache with interleaved addressing
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/10—Address translation
    • G06F12/1027—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
    • G06F12/1045—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB] associated with a data cache
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0864—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches using pseudo-associative means, e.g. set-associative or hashing

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
CN2008801031989A 2007-08-16 2008-07-29 用于高速缓存分区分配的方法和系统 Expired - Fee Related CN101784994B (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US11/839,663 2007-08-16
US11/839,663 US8433851B2 (en) 2007-08-16 2007-08-16 Reducing wiring congestion in a cache subsystem utilizing sectored caches with discontiguous addressing
PCT/EP2008/059902 WO2009021835A1 (en) 2007-08-16 2008-07-29 Cache sector allocation

Publications (2)

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CN101784994A CN101784994A (zh) 2010-07-21
CN101784994B true CN101784994B (zh) 2013-02-13

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US (1) US8433851B2 (enExample)
EP (1) EP2179361B1 (enExample)
JP (1) JP5241838B2 (enExample)
KR (1) KR101190403B1 (enExample)
CN (1) CN101784994B (enExample)
AT (1) ATE544115T1 (enExample)
WO (1) WO2009021835A1 (enExample)

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US8645404B2 (en) * 2011-10-21 2014-02-04 International Business Machines Corporation Memory pattern searching via displaced-read memory addressing
US8954672B2 (en) * 2012-03-12 2015-02-10 Advanced Micro Devices, Inc. System and method for cache organization in row-based memories
KR101858159B1 (ko) 2012-05-08 2018-06-28 삼성전자주식회사 멀티-ｃｐｕ 시스템과 이를 포함하는 컴퓨팅 시스템
US8862828B2 (en) * 2012-06-28 2014-10-14 Intel Corporation Sub-numa clustering
US10073779B2 (en) 2012-12-28 2018-09-11 Intel Corporation Processors having virtually clustered cores and cache slices
WO2014151043A1 (en) 2013-03-15 2014-09-25 Soft Machines, Inc. A method for emulating a guest centralized flag architecture by using a native distributed flag architecture
US20140337583A1 (en) * 2013-05-07 2014-11-13 Lsi Corporation Intelligent cache window management for storage systems
US10013352B2 (en) * 2014-09-26 2018-07-03 Intel Corporation Partner-aware virtual microsectoring for sectored cache architectures
US9690706B2 (en) 2015-03-25 2017-06-27 Intel Corporation Changing cache ownership in clustered multiprocessor
US9971700B2 (en) * 2015-11-06 2018-05-15 Advanced Micro Devices, Inc. Cache with address space mapping to slice subsets
KR20170056782A (ko) * 2015-11-13 2017-05-24 에스케이하이닉스 주식회사 메모리 시스템 및 메모리 시스템의 동작방법
US9832277B2 (en) * 2015-11-13 2017-11-28 Western Digital Technologies, Inc. Systems and methods for adaptive partitioning in distributed cache memories
CN105550979A (zh) * 2015-12-11 2016-05-04 中国航空工业集团公司西安航空计算技术研究所 一种高数据通量纹理Cache层次结构
US10255190B2 (en) * 2015-12-17 2019-04-09 Advanced Micro Devices, Inc. Hybrid cache
US12293227B2 (en) 2018-06-21 2025-05-06 Telefonaktiebolaget Lm Ericsson (Publ) Memory allocation in a hierarchical memory system
CN117354268A (zh) * 2022-06-27 2024-01-05 深圳市中兴微电子技术有限公司 一种报文的缓存方法、装置、电子设备及存储介质

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US6332179B1 (en) * 1999-08-19 2001-12-18 International Business Machines Corporation Allocation for back-to-back misses in a directory based cache

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JP3770380B2 (ja) * 2000-09-19 2006-04-26 シャープ株式会社 液晶表示装置
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Publication number Publication date
ATE544115T1 (de) 2012-02-15
US8433851B2 (en) 2013-04-30
CN101784994A (zh) 2010-07-21
WO2009021835A1 (en) 2009-02-19
KR20100040317A (ko) 2010-04-19
EP2179361B1 (en) 2012-02-01
JP2010537265A (ja) 2010-12-02
JP5241838B2 (ja) 2013-07-17
EP2179361A1 (en) 2010-04-28
US20090049248A1 (en) 2009-02-19
KR101190403B1 (ko) 2012-10-12

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