CN101783312A - Method for manufacturing shallow groove isolation structure - Google Patents
Method for manufacturing shallow groove isolation structure Download PDFInfo
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- CN101783312A CN101783312A CN200910045971A CN200910045971A CN101783312A CN 101783312 A CN101783312 A CN 101783312A CN 200910045971 A CN200910045971 A CN 200910045971A CN 200910045971 A CN200910045971 A CN 200910045971A CN 101783312 A CN101783312 A CN 101783312A
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- manufacture method
- shallow trench
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- ditch groove
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Abstract
The invention provides a method for manufacturing a shallow groove isolation structure, which comprises the following steps of: providing a semiconductor substrate which is provided with a mask layer and a shallow groove; processing the shallow groove by using oxygen-containing plasma to form protective layers on the bottom surface and the wall surface of the shallow groove; performing back etching on the side wall of the mask layer; and filling an isolation layer in the shallow groove. Compared with the prior art, before performing back etching on the mask layer, the shallow groove is processed by the oxygen-containing plasma, the protective layers are formed on the bottom surface and the wall surface of the shallow groove, so a solvent used by the back etching can be prevented from damaging the bottom surface and the wall surface of the shallow groove.
Description
Technical field
The present invention relates to field of semiconductor manufacture, relate in particular to a kind of manufacture method of fleet plough groove isolation structure.
Background technology
The developing direction of semiconductor integrated circuit is for increasing density and dwindling element.In production of integrated circuits, isolation structure is a kind of important technology, be formed on the silicon base element must with other element separation.Along with the progress of semiconductor fabrication techniques, shallow trench isolation from (Shallow Trench Isolation, STI) technology replaced gradually conventional semiconductor devices make adopted wait other partition methods as localized oxidation of silicon method (LOCOS).
The manufacture method of existing fleet plough groove isolation structure generally comprises: silica wafer in the high-temperature oxydation boiler tube, on silicon substrate, form cushion oxide layer (Pad Oxide) and silicon nitride layer (Nitride), carry out the shallow trench etching again, bottom and sidewall at shallow trench forms interior lining oxide layer (Liner) with thermal oxidation technology afterwards, and on described substrate oxide layer, be formed for filling the filling oxide layer of shallow trench with for example low-pressure chemical vapor phase deposition (LPCVD) technology or high concentration plasma-chemical vapour deposition (CVD) (HDP-CVD) technology, then remove the material that the surface has more with cmp (CMP) technology, and with silicon nitride layer as grinding stop layer, stay a smooth surface, again silicon nitride layer and cushion oxide layer are removed at last, for the making of subsequent technique.About the manufacturing of fleet plough groove isolation structure, can also in No. the 98115052.7th, Chinese invention patent, find more.
As shown in Figure 1, the part that is higher than Semiconductor substrate 101 surfaces for the oxide layer 102 of will fill in the shallow trench is made to the outstanding ear shape structure in side, in order to improve the electric property of made device, acid flux materials such as needs use phosphoric acid carry out etch-back process to silicon nitride layer.Etch-back process need be carried out before the lining oxide layer in the bottom surface of shallow trench and wall form with thermal oxidation technology, because in the process that forms liner oxide, also can be converted into silica on the sidewall of silicon nitride layer, this just eat-backs silicon nitride layer to phosphoric acid and has caused obstacle.And before forming the liner oxide layer, eat-backing silicon nitride layer with phosphoric acid, phosphoric acid can produce damage with the silicon substrate that exposes in the shallow trench, makes that shallow trench inwall 201 surfaces are crude, as shown in Figure 2.This can reduce the isolation characteristic of shallow trench, thereby causes the final quality of semiconductor devices that forms to descend.
Summary of the invention
Technical problem to be solved by this invention is: when making fleet plough groove isolation structure, how can realize eat-backing of mask layer, can prevent that again the inwall of shallow trench from sustaining damage.
For addressing the above problem, the invention provides a kind of manufacture method of fleet plough groove isolation structure, comprise step: provide Semiconductor substrate with mask layer and shallow trench; With containing the described shallow trench of oxygen plasma treatment, at the bottom surface and the wall formation protective layer of shallow trench; Sidewall to mask layer eat-backs; In shallow trench, fill separator.
Alternatively, after eat-backing, fill and also comprise step before the separator: remove protective layer.
Alternatively, also comprise step before after removing protective layer, filling separator: at the bottom surface and the wall formation liner oxide layer of shallow trench.
Alternatively, described removal protective layer is specially the dissolution with solvents protective layer that uses hydrofluoric acid containing.
Alternatively, etch-back amount is 3nm to 6nm.
Alternatively, the material that forms described mask layer is a silicon nitride.
Alternatively, the solvent that eat-backs is the solution that comprises phosphoric acid.
Alternatively, forming the described method that contains oxygen plasma is the oxygenous gas of ionization.
Alternatively, the source power of ionization is 800W to 1200W.
Alternatively, be 80W to 120W to containing the offset power that oxygen plasma applies.
Compared with prior art, the present invention is before eat-backing mask layer, and with containing the oxygen plasma treatment shallow trench, bottom surface and wall formation protective layer at shallow trench can prevent to eat-back employed solvent damage shallow trench bottom surface and wall.
Description of drawings
Fig. 1 is the fleet plough groove isolation structure schematic diagram;
Fig. 2 is the sem photograph of the shallow trench of use prior art formation;
Fig. 3 makes the flow chart of fleet plough groove isolation structure for one embodiment of the invention;
Fig. 4 to Figure 10 is a schematic diagram of making fleet plough groove isolation structure according to flow process shown in Figure 3;
Figure 11 is the sem photograph according to the shallow trench of one embodiment of the invention manufacturing.
Embodiment
The present inventor finds that when making shallow trench, acid flux materials such as use phosphoric acid need carry out the step that mask layer carries out etch-back process before the step of the interior lining oxide layer that forms the shallow trench inwall.Because in forming the process of liner oxide, because prior art adopts about 1000 ℃ high-temperature thermal oxidation method, make also can be oxidized to antiacid dense oxide on the sidewall of mask layer that this has just caused obstacle to the sidewall that phosphoric acid eat-backs mask layer.Yet if just eat-back mask layer with acid flux material before forming the liner oxide layer, acid flux material can produce with the Semiconductor substrate that exposes in the shallow trench and damage, and makes that the shallow trench inner wall surface is crude.This can reduce the isolation characteristic of shallow trench, thereby causes the final quality of semiconductor devices that forms to descend.
For avoiding the problems referred to above, the invention provides a kind of manufacture method of fleet plough groove isolation structure, as shown in Figure 3, comprise step:
S301 forms pad oxide layer, mask layer and shallow trench on Semiconductor substrate;
S302 is with containing the described shallow trench of oxygen plasma treatment, at the bottom surface and the wall formation protective layer of shallow trench;
S303 eat-backs the sidewall of mask layer;
S304 removes protective layer;
S305 is at the bottom surface and the wall formation liner oxide layer of shallow trench;
S306 fills separator in shallow trench;
S307 removes mask layer.
Below in conjunction with accompanying drawing content of the present invention is elaborated.
Execution in step S301 provides Semiconductor substrate, forms cushion oxide layer 401, mask layer 402 and shallow trench 403 on Semiconductor substrate 400 in regular turn, forms structure as shown in Figure 4.
Wherein, described Semiconductor substrate 400 is silicon, the silicon-on-insulator (SOI) that is used to form semiconductor device that is used to form semiconductor device or is II-VI or the Ⅲ-ⅤZu Huahewubandaoti that is used to form semiconductor device.
The material of cushion oxide layer 401 is generally silica.In the prior art, the technology that forms cushion oxide layer 401 is thermal oxidation method, promptly under hot environment, Semiconductor substrate 200 is exposed in the aerobic environment.This technology realizes in boiler tube usually.Usually the thickness of the cushion oxide layer 401 that forms is all on the tens Izod right sides, and for example about 5nm to 25nm is thick.The concrete technology that forms cushion oxide layer 401 is well known to those skilled in the art, so do not repeat them here.
On cushion oxide layer 401, be formed with mask layer 402.The material of described mask layer 402 can be silicon nitride.In the prior art, the concrete grammar of formation mask layer 402 can for example be the method for chemical vapor deposition (CVD).In the present embodiment, the thickness of the mask layer 402 of formation is approximately 100nm to 200nm.And the technology that forms mask layer 402 has been well known to those skilled in the art, so do not repeat them here.
And then pattern mask layer 402, define the position of the shallow trench 403 that will form.The method of pattern mask layer 402 specifically can be, on mask layer 402, form photoresist layer (figure does not show) earlier by spin coating and dry method, with dry lithography machine or immersed photoetching machine photoresist layer is exposed and development treatment then, at the predetermined position hollow out photoresist that forms shallow trench 403, form patterned photoresist layer.Be mask with patterned photoresist layer again, utilize the method etch mask layer 402 of plasma etching, thus with the figure transfer on the photoresist layer to mask layer 402, also promptly on mask layer 402, define the position of shallow trench 403.The concrete technological parameter of pattern mask layer 402 is well known to those skilled in the art, does not repeat them here.
Removing after the photoresist layer by methods such as ashing, be pad oxide layer 401 and the Semiconductor substrate 400 of mask etching under it with the mask layer 402 after graphical again, formation shallow trench 403 on Semiconductor substrate.Shallow trench 403 is to be used for that formed grid structure on the Semiconductor substrate 400 (figure does not show) is carried out electricity to isolate.In the prior art, the method for formation shallow trench 403 is the technology of plasma dry etching.Specifically, it is the mist formation plasma that contains hydrogen bromide, chlorine and carbon tetrafluoride by ionization, the article on plasma body applies bias voltage again, make plasma in high-speed impact Semiconductor substrate 400 also with its reaction, and decompression takes away product, thereby forms the etching to Semiconductor substrate 400.It is dark that the degree of depth of the shallow trench 403 that etching forms on Semiconductor substrate 400 is generally 400nm to 500nm.Certainly, the composition of above-mentioned mist only is an example, one skilled in the art will appreciate that the gas of other compositions of ionization also can be realized identical purpose, and therefore, the above-mentioned gas composition shall not be applied to the scope of restriction claim at this.
Execution in step S302 then with containing oxygen plasma treatment shallow trench 403, forms protective layer 404 at the bottom surface and the wall of shallow trench 403.Protective layer 404 is a kind of oxides, is that silicon substrate is an example with Semiconductor substrate 400, and protective layer 404 is exactly a silica.The concrete grammar of handling shallow trench 403 is the plasma treatment that comprises the mist of oxygen and helium with ionization, wherein the flow of oxygen is 150sccm/min to 250sccm/min, concrete example such as 200sccm/min, the flow of helium is 400sccm/min to 600sccm/min, concrete example such as 500sccm/min; The ambient pressure that forms plasma is 5mT to 15mT, concrete example such as 10mT; Make the source power (Source Power) of gas plasmaization be 800W to 1200W, concrete example such as 1000W; The offset power that the article on plasma body applies (Bias Power) is 50W to 150W, concrete example such as 100W; With the time that contains oxygen plasma treatment be 30 seconds to 90 seconds, concrete example was as 60 seconds.
Through after the above-mentioned plasma treatment, the inwall of shallow trench 403 is oxidized and formed one deck thin protective layer 404, forms structure as shown in Figure 5.The inwall that protective layer 404 can be protected shallow trench can not sustain damage in follow-up process of eat-backing mask layer 402.And, can on the sidewall of mask layer 402, not form the oxide layer that obstruction is eat-back with the process that contains oxygen plasma formation protective layer 404, thereby avoid the defective of prior art.
When use contained oxygen plasma treatment, the article on plasma body had applied offset power, can strengthen the kinetic energy of plasma, and then increased the reactivity of plasma, its objective is in order to improve the oxidation quality to the shallow trench inwall.
According to another embodiment of the invention, the concrete grammar of handling shallow trench 403 is the plasma treatment with ionization oxygen, and the flow of oxygen is 150sccm/min to 300sccm/min, concrete example such as 250sccm/min; The ambient pressure that forms plasma is 5mT to 15mT, concrete example such as 10mT; Make the source power (Source Power) of gas plasmaization be 800W to 1200W, concrete example such as 900W; The offset power that the article on plasma body applies (Bias Power) is 80W to 120W, concrete example such as 110W; With the time that contains oxygen plasma treatment be 30 seconds to 90 seconds, concrete example was as 60 seconds.
In the above-described embodiments, the gas that is used to form the plasma that etching uses is the mist of oxygen or oxygen and helium.But the present invention is not limited to this, and as previously mentioned, in above-mentioned plasma treatment procedure, what it mainly acted on is oxygen plasma, therefore, as long as can ionization go out the gas of oxygen plasma, may be used among the plasma treatment of step S302.
Execution in step S303 then eat-backs the sidewall of mask layer 402, forms structure as shown in Figure 6.The concrete grammar that eat-backs is with faintly acid solvent soaking or flushing mask layer 402, make the sidewall of mask layer 402 be eaten away about 3nm to 6nm by acid flux material, such etch-back amount can form the good separator 406 with ear shape structure of electric property in subsequent technique.
The inventor finds; when the material of mask layer 402 was silicon nitride, the faintly acid solvent that is used to eat-back preferably with the solution that comprises phosphoric acid, so both can obtain the speed of eat-backing preferably; protective layer 404 can not eaten away again, and then can the sidewall of shallow trench 403 not damaged.As shown in figure 11, it is smooth to form the sidewall of shallow trench 403 in this way.
Execution in step S304 removes protective layer 404 then, forms structure as shown in Figure 7.The method of removal protective layer 404 specifically can be to utilize strongly acidic solution to soak or flushing protective layer 404, for example, can adopt dilution water dissolubility hydrofluoric acid (DHF) solution cleaning protection layer 404, promptly reacts and removal protective layer 404 with DHF solution and protective layer 404.The selection of described DHF solution should be with reference to the factors such as thickness of humidity, drying condition and protective layer 404.Another benefit with DHF solution removal protective layer 404 is can not bring extra impurity into.
Execution in step S305 then forms liner oxide layer 405 at the bottom surface and the wall of shallow trench 403, forms structure as shown in Figure 8.Liner oxide layer 405 can for example be that thermal oxidation method forms, and promptly under hot environment, Semiconductor substrate 400 is exposed in the aerobic environment.Preferably; can be that situ steam generates technology (ISSG); specifically; be the hydrogen (having oxygen and atmosphere hydroxy) that in common oxygen atmosphere, has mixed constant; at high temperature; for example 800 ℃ to 1200 ℃; generation is similar to the chemical reaction of detonation; this reaction can produce a large amount of gas-phase activity free radicals; it wherein mainly is the elemental oxygen that is easy to silicon atom reaction; because the strong oxidation of elemental oxygen, protection is not being arranged; exposed silicon surface all can be oxidized and then be formed ISSG oxide skin(coating) (being liner oxide layer 405), and the thickness of the liner oxide layer 405 of formation is roughly 3nm to 20nm.Such liner oxide layer 405 can be repaired substrate lattice defective in the shallow trench 403 and the surface stress that improves shallow trench 403 inner surfaces.
Execution in step S306 fills separator 406 in shallow trench 403 then.The material that forms separator 406 can be silica.The method that forms separator 406 can be low-pressure chemical vapor phase deposition (LPCVD) technology or high concentration plasma-chemical vapour deposition (CVD) (HDP-CVD) technology.Preferably, can be for example as the HDP-CVD technology of plasma gasification body source shallow trench 403 to be filled with the mist of silane, oxygen and argon gas.The specific implementation method of HDP-CVD technology is well known to those skilled in the art, does not repeat them here.And then separator 406 carried out cmp, make the having an even surface of separator 406 to form structure as shown in Figure 9.
Last execution in step S307 removes mask layer 402, as shown in figure 10, forms the separator 406 with ear shape structure, has finished the manufacturing of fleet plough groove isolation structure.
Though the present invention with preferred embodiment openly as above; but it is not to be used for limiting claim; any those skilled in the art without departing from the spirit and scope of the present invention; can make possible change and modification, so protection scope of the present invention should be as the criterion with the scope that claim of the present invention was defined.
Claims (10)
1. the manufacture method of a fleet plough groove isolation structure is characterized in that, comprises step:
Semiconductor substrate with mask layer and shallow trench is provided;
With containing the described shallow trench of oxygen plasma treatment, at the bottom surface and the wall formation protective layer of shallow trench;
Sidewall to mask layer eat-backs;
In shallow trench, fill separator.
2. the manufacture method of shallow ditch groove structure as claimed in claim 1 is characterized in that, fills also to comprise step before the separator after eat-backing: remove protective layer.
3. the manufacture method of shallow ditch groove structure as claimed in claim 2 is characterized in that, also comprises step fill separator after removing protective layer before: at the bottom surface and the wall formation liner oxide layer of shallow trench.
4. the manufacture method of shallow ditch groove structure as claimed in claim 2 is characterized in that: described removal protective layer is specially the dissolution with solvents protective layer that uses hydrofluoric acid containing.
5. the manufacture method of shallow ditch groove structure as claimed in claim 1, it is characterized in that: etch-back amount is 3nm to 6nm.
6. the manufacture method of shallow ditch groove structure as claimed in claim 1, it is characterized in that: the material that forms described mask layer is a silicon nitride.
7. the manufacture method of shallow ditch groove structure as claimed in claim 6, it is characterized in that: the solvent that eat-backs is the solution that comprises phosphoric acid.
8. the manufacture method of shallow ditch groove structure as claimed in claim 1, it is characterized in that: forming the described method that contains oxygen plasma is the oxygenous gas of ionization.
9. the manufacture method of shallow ditch groove structure as claimed in claim 8, it is characterized in that: the source power of ionization is 800W to 1200W.
10. the manufacture method of shallow ditch groove structure as claimed in claim 8 is characterized in that: to containing the offset power that oxygen plasma applies is 80W to 120W.
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| CN200910045971A CN101783312A (en) | 2009-01-19 | 2009-01-19 | Method for manufacturing shallow groove isolation structure |
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| CN200910045971A CN101783312A (en) | 2009-01-19 | 2009-01-19 | Method for manufacturing shallow groove isolation structure |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102468172A (en) * | 2010-11-12 | 2012-05-23 | 中芯国际集成电路制造(上海)有限公司 | Manufacturing method for semiconductor device |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102468172A (en) * | 2010-11-12 | 2012-05-23 | 中芯国际集成电路制造(上海)有限公司 | Manufacturing method for semiconductor device |
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Application publication date: 20100721 |